CN117270626A - Arbitrary waveform generator synchronization method - Google Patents
Arbitrary waveform generator synchronization method Download PDFInfo
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- CN117270626A CN117270626A CN202210666976.7A CN202210666976A CN117270626A CN 117270626 A CN117270626 A CN 117270626A CN 202210666976 A CN202210666976 A CN 202210666976A CN 117270626 A CN117270626 A CN 117270626A
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000000630 rising effect Effects 0.000 claims abstract description 22
- 230000001360 synchronised effect Effects 0.000 claims abstract description 19
- 238000005259 measurement Methods 0.000 claims abstract description 17
- 238000005070 sampling Methods 0.000 claims abstract description 4
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/022—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
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Abstract
The method for synchronizing the arbitrary waveform generator includes setting a delay generator to output two paths of synchronous trigger signals, respectively inputting the two paths of synchronous trigger signals into trigger signal input ports of two PXIe cases, routing the trigger signals of the delay generator to respective system trigger signal modules by the PXIe cases through a case back plate, distributing external trigger signals to the arbitrary waveform generator of the case by the system trigger signal modules through PXI_STAR, sending an instruction for setting the ratio of the period of the external trigger signal to the clock period of an FPGA to the arbitrary waveform generator by a measurement and control computer, sampling the external trigger signal after the arbitrary waveform generator executes the instruction for setting the ratio, counting the clock period of the FPGA by taking the rising edge of the external trigger signal as a starting point, generating an internal trigger signal and re-counting each time when the count value reaches the set ratio, sending waveforms under the trigger of the internal trigger signal after the waveform generator starts waveform sending, and realizing waveform synchronization between the arbitrary waveform generators in the two PXIe cases.
Description
Technical Field
The invention relates to the technical field of instruments, in particular to a synchronization method of an arbitrary waveform generator.
Background
In some leading edge scientific research fields, a plurality of arbitrary waveform generators are required to work cooperatively, and when the number of the arbitrary waveform generators is increased, the waveform sent by the arbitrary waveform generator has a phase jitter phenomenon, which is not allowed in the application with higher requirement on synchronism, so that the provision of the arbitrary waveform generator synchronization method is a technical problem to be solved.
Disclosure of Invention
In order to overcome the defects of the technology, the invention provides a method for synchronizing waveforms between any waveform generators in two PXIe chassis.
The technical scheme adopted for overcoming the technical problems is as follows:
a method of arbitrary waveform generator synchronization comprising the steps of:
a) Establishing a system consisting of a measurement and control computer, a clock source, a delay generator and two PXIe cases, wherein the clock source provides reference clocks for the delay generator and the PXIe cases, and each of the PXIe cases prevents a system trigger signal module and a plurality of arbitrary waveform generators, and the clocks of the system trigger signal module and the arbitrary waveform generators are synchronized to the clock used by the PXIe case;
b) The PXIe case routes trigger signals of the delay generators to a system trigger signal module through a case back plate, the system trigger signal module distributes external trigger signals to all the arbitrary waveform generators, and the arbitrary waveform generators FPGA sample rising edges of the external trigger signals;
c) Setting a delay generator to output two paths of synchronous trigger signals, wherein the two paths of synchronous trigger signals are respectively input into trigger signal input ports of two PXIe chassis;
d) The measurement and control computer sends an instruction for setting the ratio of the external trigger signal period to the FPGA clock period to any waveform generator;
e) Sampling an external trigger signal after the random waveform generator executes a ratio setting instruction;
f) Executing step g) when the arbitrary waveform generator samples the rising edge of the external trigger signal, and returning to executing step e) if the arbitrary waveform generator does not sample the rising edge of the external trigger signal;
g) Starting to count the clock cycles of the FPGA of the arbitrary waveform generator;
h) Executing step i) when the count value of the FPGA clock cycle reaches the ratio of the external trigger signal cycle to the FPGA clock cycle, and returning to executing step g) if the count value of the FPGA clock cycle does not reach the ratio of the external trigger signal cycle to the FPGA clock cycle;
i) The random waveform generator generates an internal trigger signal and recounts the clock cycle of the FPGA;
j) The measurement and control computer loads waveform data for the arbitrary waveform generator and starts waveform transmission;
k) The arbitrary waveform generator transmits waveforms under the triggering of an internal trigger signal.
Further, the clock source in step a) provides a 10MHz reference clock for the delay generator and PXIe chassis.
Further, in step b), the system trigger signal module distributes the external trigger signal to each arbitrary waveform generator through pxi_star, and the arbitrary waveform generator FPGA samples the rising edge of the external trigger signal using the rising edge of the clock with the clock period of 4 ns.
Further, in step c), the delay generator outputs two synchronous trigger signals as square waves with a period of 200 μs.
Further, when the internal trigger signal period of the arbitrary waveform generator needs to be changed, the measurement and control computer sends an instruction to the arbitrary waveform generator to reset the ratio of the external trigger signal period to the FPGA clock period.
The beneficial effects of the invention are as follows: the method comprises the steps that a delay generator is set to output two paths of synchronous trigger signals, the two paths of synchronous trigger signals are respectively input into trigger signal input ports of two PXIe chassis, the PXIe chassis routes the trigger signals of the delay generator to respective system trigger signal modules through a chassis backboard, the system trigger signal modules distribute external trigger signals to any waveform generator of the chassis through PXI_STAR, a measurement and control computer sends an instruction for setting the ratio of the external trigger signal period to the FPGA clock period to any waveform generator, the any waveform generator samples the external trigger signal after executing the instruction for setting the ratio, the rising edge of the external trigger signal is used as a starting point to count the FPGA clock period, an internal trigger signal is generated and recounting is carried out every time the count value reaches the set ratio, and the waveform generator sends waveforms under the triggering of the internal trigger signal after the waveform generator starts waveform sending, so that waveform synchronization between any waveform generators in the two PXIe chassis is realized.
Drawings
FIG. 1 is a schematic diagram of a trigger signal correlation system according to the present invention;
fig. 2 is a schematic diagram of the synchronization method of the present invention.
Detailed Description
The invention is further described with reference to fig. 1 and 2.
A method of arbitrary waveform generator synchronization comprising the steps of:
a) Establishing a system consisting of a measurement and control computer, a clock source, a delay generator and two PXIe cases, wherein the clock source provides reference clocks for the delay generator and the PXIe cases, and each of the PXIe cases prevents a system trigger signal module and a plurality of arbitrary waveform generators, and the clocks of the system trigger signal module and the arbitrary waveform generators are synchronized to the clock used by the PXIe case;
b) The PXIe case routes trigger signals of the delay generators to a system trigger signal module through a case back plate, the system trigger signal module distributes external trigger signals to all the arbitrary waveform generators, and the arbitrary waveform generators FPGA sample rising edges of the external trigger signals;
c) Setting a delay generator to output two paths of synchronous trigger signals, wherein the two paths of synchronous trigger signals are respectively input into trigger signal input ports of two PXIe chassis;
d) The measurement and control computer sends an instruction for setting the ratio of the external trigger signal period to the FPGA clock period to any waveform generator;
e) Sampling an external trigger signal after the random waveform generator executes a ratio setting instruction;
f) Executing step g) when the arbitrary waveform generator samples the rising edge of the external trigger signal, and returning to executing step e) if the arbitrary waveform generator does not sample the rising edge of the external trigger signal;
g) Starting to count the clock cycles of the FPGA of the arbitrary waveform generator;
h) Executing step i) when the count value of the FPGA clock cycle reaches the ratio of the external trigger signal cycle to the FPGA clock cycle, and returning to executing step g) if the count value of the FPGA clock cycle does not reach the ratio of the external trigger signal cycle to the FPGA clock cycle;
i) The random waveform generator generates an internal trigger signal and recounts the clock cycle of the FPGA;
j) The measurement and control computer loads waveform data for the arbitrary waveform generator and starts waveform transmission;
k) The arbitrary waveform generator transmits waveforms under the triggering of an internal trigger signal.
The method comprises the steps that a delay generator is set to output two paths of synchronous trigger signals, the two paths of synchronous trigger signals are respectively input into trigger signal input ports of two PXIe chassis, the PXIe chassis routes the trigger signals of the delay generator to respective system trigger signal modules through a chassis backboard, the system trigger signal modules distribute external trigger signals to any waveform generator of the chassis through PXI_STAR, a measurement and control computer sends an instruction for setting the ratio of the external trigger signal period to the FPGA clock period to any waveform generator, the any waveform generator samples the external trigger signal after executing the instruction for setting the ratio, the rising edge of the external trigger signal is used as a starting point to count the FPGA clock period, an internal trigger signal is generated and recounting is carried out every time the count value reaches the set ratio, and the waveform generator sends waveforms under the triggering of the internal trigger signal after the waveform generator starts waveform sending, so that waveform synchronization between any waveform generators in the two PXIe chassis is realized.
Example 1:
the clock source in step a) provides a 10MHz reference clock for the delay generator and PXIe chassis.
Example 2:
in the step b), the system trigger signal module distributes the external trigger signal to each arbitrary waveform generator through PXI_STAR, and the arbitrary waveform generator FPGA samples the rising edge of the external trigger signal by using the rising edge of the clock with the clock period of 4 ns.
Example 3:
the delay generator in step c) outputs two synchronous trigger signals as square waves with the period of 200 mu s.
Example 4:
when the internal trigger signal period of the arbitrary waveform generator needs to be changed, the measurement and control computer sends an instruction to the arbitrary waveform generator to reset the ratio of the external trigger signal period to the FPGA clock period.
Specific:
it is assumed that there are two arbitrary waveform generators AWG1 and AWG2 in PXIe chassis 1, and two arbitrary waveform generators AWG3 and AWG4 in PXIe chassis 2.
Setting a delay generator to output two paths of synchronous trigger signals, wherein the trigger signals are square waves with the period of 200us, and the trigger signals are input to front panel trigger signal input ports of the PXIe chassis 1 and the PXIe chassis 2;
the measurement and control computer sends an instruction for setting the ratio of the external trigger signal period to the FPGA clock period to AWG1 and AWG2 in the PXIe case 1 and AWG3 and AWG4 in the PXIe case 2, wherein the ratio is 200000/4=50000, and the AWG1 and the AWG2 are firstly set, and then the AWG3 and the AWG4 are set.
The AWG1 receives and executes the instruction for setting the ratio, and samples an external trigger signal after the instruction execution is completed.
AWG1 samples to the rising edge of the external trigger signal, starts to count the FPGA clock period, and starts to count with the timing starting point of 0.
The AWG2 receives and executes the instruction for setting the ratio, and samples the external trigger signal after the instruction execution is completed.
AWG2 samples to the rising edge of the external trigger signal, and starts to count the clock cycles of the FPGA.
The AWG3 receives and executes the instruction for setting the ratio, and samples the external trigger signal after the instruction execution is completed.
AWG3 samples to the rising edge of the external trigger signal, and starts to count the clock cycles of the FPGA.
The AWG4 receives and executes the instruction for setting the ratio, and samples the external trigger signal after the instruction execution is completed.
AWG4 samples to the rising edge of the external trigger signal, and starts to count the clock cycles of the FPGA.
Each time the count value for the FPGA clock cycles reaches 50000, AWG1 and AWG2 and AWG3 and AWG4 each generate an internal trigger signal and re-count the FPGA clock cycles.
The measurement and control computer loads waveform data for AWG1 and AWG2 and AWG3 and AWG4 and starts waveform transmission.
AWG1 and AWG2 and AWG3 and AWG4 transmit waveforms triggered by respective internal trigger signals.
Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. A method for synchronizing arbitrary waveform generators, comprising the steps of:
a) Establishing a system consisting of a measurement and control computer, a clock source, a delay generator and two PXIe cases, wherein the clock source provides reference clocks for the delay generator and the PXIe cases, and each of the PXIe cases prevents a system trigger signal module and a plurality of arbitrary waveform generators, and the clocks of the system trigger signal module and the arbitrary waveform generators are synchronized to the clock used by the PXIe case;
b) The PXIe case routes trigger signals of the delay generators to a system trigger signal module through a case back plate, the system trigger signal module distributes external trigger signals to all the arbitrary waveform generators, and the arbitrary waveform generators FPGA sample rising edges of the external trigger signals;
c) Setting a delay generator to output two paths of synchronous trigger signals, wherein the two paths of synchronous trigger signals are respectively input into trigger signal input ports of two PXIe chassis;
d) The measurement and control computer sends an instruction for setting the ratio of the external trigger signal period to the FPGA clock period to any waveform generator;
e) Sampling an external trigger signal after the random waveform generator executes a ratio setting instruction;
f) Executing step g) when the arbitrary waveform generator samples the rising edge of the external trigger signal, and returning to executing step e) if the arbitrary waveform generator does not sample the rising edge of the external trigger signal;
g) Starting to count the clock cycles of the FPGA of the arbitrary waveform generator;
h) Executing step i) when the count value of the FPGA clock cycle reaches the ratio of the external trigger signal cycle to the FPGA clock cycle, and returning to executing step g) if the count value of the FPGA clock cycle does not reach the ratio of the external trigger signal cycle to the FPGA clock cycle;
i) The random waveform generator generates an internal trigger signal and recounts the clock cycle of the FPGA;
j) The measurement and control computer loads waveform data for the arbitrary waveform generator and starts waveform transmission;
k) The arbitrary waveform generator transmits waveforms under the triggering of an internal trigger signal.
2. The arbitrary waveform generator synchronization method of claim 1 wherein: the clock source in step a) provides a 10MHz reference clock for the delay generator and PXIe chassis.
3. The arbitrary waveform generator synchronization method of claim 1 wherein: in the step b), the system trigger signal module distributes the external trigger signal to each arbitrary waveform generator through PXI_STAR, and the arbitrary waveform generator FPGA samples the rising edge of the external trigger signal by using the rising edge of the clock with the clock period of 4 ns.
4. The arbitrary waveform generator synchronization method of claim 1 wherein: the delay generator in step c) outputs two synchronous trigger signals as square waves with the period of 200 mu s.
5. The arbitrary waveform generator synchronization method of claim 1 wherein: when the internal trigger signal period of the arbitrary waveform generator needs to be changed, the measurement and control computer sends an instruction to the arbitrary waveform generator to reset the ratio of the external trigger signal period to the FPGA clock period.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210666976.7A CN117270626A (en) | 2022-06-14 | 2022-06-14 | Arbitrary waveform generator synchronization method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210666976.7A CN117270626A (en) | 2022-06-14 | 2022-06-14 | Arbitrary waveform generator synchronization method |
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