CN212752227U - High-precision synchronous analog-digital mixed signal generator for image sensor - Google Patents
High-precision synchronous analog-digital mixed signal generator for image sensor Download PDFInfo
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- CN212752227U CN212752227U CN202021507881.3U CN202021507881U CN212752227U CN 212752227 U CN212752227 U CN 212752227U CN 202021507881 U CN202021507881 U CN 202021507881U CN 212752227 U CN212752227 U CN 212752227U
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Abstract
The utility model discloses a synchronous modulus mixed signal generator of high accuracy for image sensor belongs to the image sensor field of formation of image, and it includes a clock integrated circuit board, an at least AWG integrated circuit board and an at least LVDS integrated circuit board. The clock board card comprises a first FPGA system control module, a first clock synchronization module and a first local reference clock module, each AWG board card comprises a second FPGA system control module, a second clock synchronization module and a plurality of DAC modules, and the LVDS board card comprises a third FPGA system control module and a third clock synchronization module. The utility model discloses a clock integrated circuit board provides reference clock and trigger pulse for AWG integrated circuit board and LVDS board, has realized the high accuracy synchronization output control of multichannel DAC output signal and LVDS chronogenesis signal between polylith AWG integrated circuit board and LVDS integrated circuit board.
Description
Technical Field
The utility model relates to an image sensor imaging field especially indicates a synchronous modulus mixing signal generator of high accuracy for image sensor.
Background
Generally, an Arbitrary Waveform Generator (AWG) card is used to generate an analog signal with an arbitrary waveform alone, whereas a digital LVDS signal needs to be generated by an LVDS card. However, in the field of imaging of image sensors, driving signals of the image sensors usually include multiple paths of analog signals and digital timing signals, and meanwhile, phases of the signals have a strict correspondence relationship, and it is necessary to realize that the phase relationship can be accurately adjusted. Especially for a large-area array image sensor, a large number of analog signals and digital time sequence signals are needed, the resource requirement is huge, and the synchronization requirement is high.
In the field of image sensor testing, a high-precision synchronous signal generator for mixing a plurality of paths of analog signals and digital LVDS signals is not provided at present. Therefore, it is very necessary to develop a high-precision synchronous analog-digital mixed signal generator.
SUMMERY OF THE UTILITY MODEL
The utility model provides a synchronous modulus mixed signal generator of high accuracy for image sensor, the utility model discloses a high accuracy synchronization output control of multichannel DAC output signal and LVDS chronogenesis signal between polylith AWG integrated circuit board and LVDS integrated circuit board.
In order to solve the technical problem, the utility model provides a technical scheme as follows:
a high-precision synchronous analog-digital mixed signal generator for an image sensor comprises a clock board card, at least one AWG board card and at least one LVDS board card, wherein:
the clock board card comprises a first FPGA system control module, a first clock synchronization module and a first local reference clock module, each AWG board card comprises a second FPGA system control module, a second clock synchronization module and a plurality of DAC modules, and the LVDS board card comprises a third FPGA system control module and a third clock synchronization module;
the first FPGA system control module is respectively and electrically connected with the second FPGA system control module and the third FPGA system control module and respectively inputs trigger pulses to the second FPGA system control module and the third FPGA system control module;
the first FPGA system control module is electrically connected with a first clock synchronization module, and the first local reference clock module is electrically connected with the first clock synchronization module and inputs a first reference clock to the first clock synchronization module; the first clock synchronization module is respectively and electrically connected with the second clock synchronization module and the third clock synchronization module and respectively inputs reference clocks obtained by taking the first reference clock as a reference clock to the second clock synchronization module and the third clock synchronization module;
the second clock synchronization module is electrically connected with the second FPGA system control module and inputs a first reference clock obtained by taking the reference clock as a reference clock to the second FPGA system control module, the second clock synchronization module is electrically connected with each DAC module and respectively inputs a first sampling clock obtained by taking the reference clock as the reference clock to each DAC module, and the phases of the first reference clock and the first sampling clock are aligned; the second FPGA system control module is respectively and electrically connected with each DAC module and respectively inputs a data clock and a synchronous signal which are obtained by taking the first reference clock as reference to each DAC module;
the third clock synchronization module is electrically connected with the third FPGA system control module and inputs a second reference clock obtained by taking the reference clock as a reference clock to the third FPGA system control module, and the third FPGA system control module outputs an LVDS time sequence signal by taking the second reference clock as a reference.
Furthermore, the clock board further comprises a first network module, and the first network module is electrically connected with the first FPGA system control module; the AWG board card also comprises a second network module, and the second network module is electrically connected with the second FPGA system control module; the LVDS board card further comprises a third network module, and the third network module is electrically connected with the third FPGA system control module; the first network module is respectively and electrically connected with the second network module and the third network module and respectively inputs communication signals to the second network module and the third network module.
Further, the AWG board further includes a second local reference clock module, where the second local reference clock module is electrically connected to the second clock synchronization module and inputs a second reference clock to the second clock synchronization module as a reference clock of the second clock synchronization module; the LVDS board card further comprises a third local reference clock module, wherein the third local reference clock module is electrically connected with the third clock synchronization module and inputs a third reference clock to the third clock synchronization module as a reference clock of the third clock synchronization module.
Further, the LVDS board further includes an FIFO memory, and the FIFO memory is electrically connected to the third FPGA system control module and the third network module, respectively.
Further, the first local reference clock module, the second local reference clock module, and the third local reference clock module are low-noise and low-frequency crystal oscillators, and the first network module, the second network module, and the third network module are ethernet communication modules.
Further, the first local reference clock module, the second local reference clock module, and the third local reference clock module are respectively connected to SEC ports of the first clock synchronization module, the second clock synchronization module, and the third clock synchronization module.
The utility model discloses following beneficial effect has:
the utility model discloses a clock integrated circuit board provides reference clock and trigger pulse for AWG integrated circuit board and LVDS integrated circuit board, can realize multichannel DAC output waveform and self-defined LVDS output sequential signal's phase synchronization, adopts the mode that cascades FPGA between the integrated circuit board, and FPGA through the clock integrated circuit board controls the FPGA of AWG integrated circuit board and LVDS integrated circuit board and is synchronous, makes the output signal of each way DAC and the output sequential signal of LVDS synchronous and controllable completely. Meanwhile, the transmission of high-speed analog clock signals among multiple board cards is abandoned, and only a low-speed reference clock and a trigger pulse are provided by the clock board card, so that the difficulty of hardware design is greatly simplified.
Drawings
Fig. 1 is a schematic diagram of the overall structure of a high-precision synchronous analog-digital mixed signal generator for an image sensor according to the present invention;
fig. 2 is a schematic circuit diagram of the high-precision synchronous analog-digital mixed signal generator for the image sensor of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
The embodiment of the utility model provides a synchronous modulus mixed signal generator of high accuracy for image sensor for realize multichannel DAC output waveform and the phase synchronization of self-defined LVDS output signal of AWG integrated circuit board, solve under the great condition of signal demand quantity a plurality of DAC output signal and the synchronous problem of LVDS output chronogenesis high accuracy. As shown in fig. 1-2, the system includes a clock board 100, at least one AWG board 200, and at least one LVDS board 300, wherein:
the clock board 100 includes a first FPGA system control module 101, a first clock synchronization module 102, and a first local reference clock module 103. The first FPGA system control module 101 is configured to output a synchronous trigger pulse, a control signal and a communication signal,
each AWG card 200 includes a second FPGA system control module 201, a second clock synchronization module 202, and a plurality of DAC modules 203. The second FPGA system control module 201 is used for receiving the synchronous trigger pulse and outputting the control signal and the communication signal, and the DAC module 203 is preferably a high-speed DAC module.
The LVDS board 300 includes a third FPGA-system control module 301 and a third clock synchronization module 302. The third FPGA system control module 301 is configured to receive the synchronization trigger pulse and output the LVDS timing signal and the communication signal.
The first FPGA system control module 101 is electrically connected to the second FPGA system control module 201 and the third FPGA system control module 301 respectively, and inputs a trigger pulse to the second FPGA system control module 201 and the third FPGA system control module 301 respectively.
The first FPGA system control module 101 is electrically connected to the first clock synchronization module 102, the first local reference clock module 103 is electrically connected to the first clock synchronization module 102 and inputs the first reference clock to the first clock synchronization module 102, and the first clock synchronization module 102 obtains a reference clock by using the first reference clock as a reference clock, where the reference clock is a low-speed reference clock. The first clock synchronization module 102 is electrically connected to the second clock synchronization module 202 and the third clock synchronization module 302, and respectively inputs a reference clock obtained based on the first reference clock to the second clock synchronization module 202 and the third clock synchronization module 302.
The second clock synchronization module 202 obtains a first reference clock and a first sampling clock by receiving an externally input reference clock as a reference clock. The second clock synchronization module 202 is electrically connected to the second FPGA system control module 201 and inputs the first reference clock obtained based on the reference clock to the second FPGA system control module 201.
The second clock synchronization module 202 is electrically connected to each DAC module 203 and respectively inputs a first sampling clock obtained with reference to the reference clock to each DAC module 203, and the first reference clock and the first sampling clock are phase-aligned.
The second FPGA system control module 201 is electrically connected to each DAC module 203, and inputs a data clock and a synchronization signal, which are obtained with reference to the first reference clock, to each DAC module 203. After the first reference clock is input to the second FPGA system control module 201, the second FPGA system control module 201 outputs the data clock and the synchronization signal SYNC to each DAC module according to the first reference clock with reference to the first reference clock, so as to ensure that the data clock phases of each DAC module are aligned accurately.
The third clock synchronization module 302 obtains a second reference clock by receiving an externally input reference clock as a reference clock, the third clock synchronization module 302 is electrically connected to the third FPGA system control module 301 and inputs the second reference clock obtained by using the reference clock as a reference to the third FPGA system control module 301, and the third FPGA system control module 301 outputs an LVDS timing signal by using the second reference clock as a reference. After the second reference clock is input to the third FPGA system control module 301, the third FPGA system control module 301 outputs the LVDS timing signal with reference to the second reference clock, so as to ensure that the phase of the output timing signal is accurately aligned with the reference clock.
Take an AWG integrated circuit board and an LVDS integrated circuit board shown in fig. 2 and have two DAC modules in a single AWG integrated circuit board as an example to be right the utility model discloses a working process carries out the following detailed description:
the first clock synchronization module 102 in the clock board 100 outputs two reference clocks with aligned phases, and each reference clock is input to an AWG board or an LVDS board.
The second clock synchronization module 202 in the AWG board 200 outputs two first sampling clocks and two first reference clocks which are aligned in phase with an externally input reference clock as a reference clock, the first sampling clock is input to each corresponding DAC module 203, the first reference clock is input to the second FPGA system control module 201, and the second FPGA system control module 201 outputs a data clock and a synchronization signal SYNC to the DAC module 203 according to the first reference clock with the first reference clock as a reference, so as to ensure that the phases of the data clocks of each DAC module 203 are aligned in phase precision.
Similarly, the third clock synchronization module 302 in the LVDS board 300 uses an externally input reference clock as a reference clock to output a second reference clock having the same phase as the reference clock, the second reference clock is input to the third FPGA system control module 301, and the third FPGA system control module 301 uses the second reference clock as a reference to ensure that the phase of the output timing signal is accurately aligned with the reference clock.
Meanwhile, the clock board 100 provides a synchronous trigger pulse to an AWG board 200 and an LVDS board 300. When the synchronous trigger pulse input is valid, the second FPGA system control module 201 of the AWG board card 200 outputs data streams to each DAC203 according to the aligned phase clock, and the third FPGA system control module 301 of the LVDS board card 300 outputs the user-defined LVDS timing signal according to the aligned phase clock, so as to ensure synchronous output of the plurality of DAC output signals and the LVDS timing signal.
The utility model discloses a clock integrated circuit board provides reference clock and trigger pulse for AWG integrated circuit board and LVDS integrated circuit board, can realize multichannel DAC output waveform and self-defined LVDS output sequential signal's phase synchronization, adopts the mode that cascades FPGA between the integrated circuit board, and FPGA through the clock integrated circuit board controls the FPGA of AWG integrated circuit board and LVDS integrated circuit board and is synchronous, makes the output signal of each way DAC and the output sequential signal of LVDS synchronous and controllable completely. Meanwhile, the transmission of high-speed analog clock signals among multiple board cards is abandoned, and only a low-speed reference clock and a trigger pulse are provided by the clock board card, so that the difficulty of hardware design is greatly simplified.
The clock board 100 may further include a first network module 104, where the first network module 104 is electrically connected to the first FPGA system control module 101; the AWG board card 200 may further include a second network module 204, where the second network module 204 is electrically connected to the second FPGA system control module 201; the LVDS board 300 may further include a third network module 303, where the third network module 303 is electrically connected to the third FPGA system control module 301; the first network module 104 is electrically connected to the second network module 204 and the third network module 303, respectively, and inputs communication signals to the second network module 204 and the third network module 303, respectively.
The utility model discloses communicate through network protocol between clock integrated circuit board and AWG integrated circuit board, the LVDS integrated circuit board, improved communication rate and work efficiency.
As an improvement of the present invention, the single AWG board card or LVDS board card can work independently, and the specific implementation manner is: the AWG board 200 further includes a second local reference clock module 205, where the second local reference clock module 205 is electrically connected to the second clock synchronization module 202 and inputs a second reference clock to the second clock synchronization module 202 as a reference clock of the second clock synchronization module 202; the LVDS board 300 further includes a third local reference clock module 304, and the third local reference clock module 304 is electrically connected to the third clock synchronization module 302 and inputs the third reference clock to the third clock synchronization module 302 as the reference clock of the third clock synchronization module 302.
Under the condition that the AWG board card works independently, the second local reference clock module, the second clock synchronization module and the second FPGA system control module are matched to realize the synchronization of a plurality of DAC modules in a single AWG board card. The specific method comprises the following steps:
the clock source of the second clock synchronization module is a second local reference clock module, the second clock synchronization module outputs a second reference clock according to the second reference clock output by the second local reference clock module, the second FPGA system control module takes the reference clock as an accurate reference clock and outputs a second sampling clock and a second reference clock with aligned phases, the number of the second sampling clock and the second reference clock is in one-to-one correspondence with the DAC modules, the second sampling clock is input into each corresponding DAC module, the second reference clock is input into the second FPGA system control module, the second FPGA system control module takes the second reference clock as a reference and outputs a data clock and a synchronization signal to the DAC modules according to the reference clock so as to ensure that the data clock phases of the DAC modules are aligned accurately in phase, when the trigger pulse signal is input effectively, the second FPGA system control module outputs data flow to each DAC according to the aligned phase clock, to ensure synchronization of multiple DACs in a single board.
Under the condition that the LVDS board works independently, the third FPGA system control module is used for outputting a user-defined LVDS time sequence signal by taking the third reference clock as a reference when the trigger pulse is effective.
The LVDS board 300 further includes a FIFO memory 305, and the FIFO memory 305 is electrically connected to the third FPGA system control module 301 and the third network module 303, respectively.
The first local reference clock module 103, the second local reference clock module 205, and the third local reference clock module 304 are low-noise and low-frequency crystal oscillators, and the first network module 104, the second network module 204, and the third network module 303 are ethernet communication modules.
Specifically, the models of the first FPGA system control module 101, the second FPGA system control module 201, and the third FPGA system control module 301 are an ARTIX-7XC7a200TFBG484S of Xilinx (saint corporation), the model of the low-noise low-frequency crystal oscillator is a TCE4031035GK005008, the models of the first clock synchronization module 102, the second clock synchronization module 202, and the third clock synchronization module 302 are a CDCE72010 of TI (texas instruments), the model of the ethernet communication module is a KSZ9031 of Microchip corporation, and the model of the DAC module is a DAC 5682Z.
The first local reference clock module 103, the second local reference clock module 205 and the third local reference clock module 304 are respectively connected to the SEC ports of the first clock synchronization module 102, the second clock synchronization module 202 and the third clock synchronization module 302, and the ultra-low jitter clock output by the local reference clock module is input to the SEC end of the clock synchronization module as a reference clock.
The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (6)
1. The utility model provides a high accuracy synchronization analog-digital mixed signal generator for image sensor which characterized in that includes a clock integrated circuit board, at least an AWG integrated circuit board and at least an LVDS integrated circuit board, wherein:
the clock board card comprises a first FPGA system control module, a first clock synchronization module and a first local reference clock module, each AWG board card comprises a second FPGA system control module, a second clock synchronization module and a plurality of DAC modules, and the LVDS board card comprises a third FPGA system control module and a third clock synchronization module;
the first FPGA system control module is respectively and electrically connected with the second FPGA system control module and the third FPGA system control module and respectively inputs trigger pulses to the second FPGA system control module and the third FPGA system control module;
the first FPGA system control module is electrically connected with a first clock synchronization module, and the first local reference clock module is electrically connected with the first clock synchronization module and inputs a first reference clock to the first clock synchronization module; the first clock synchronization module is respectively and electrically connected with the second clock synchronization module and the third clock synchronization module and respectively inputs reference clocks obtained by taking the first reference clock as a reference clock to the second clock synchronization module and the third clock synchronization module;
the second clock synchronization module is electrically connected with the second FPGA system control module and inputs a first reference clock obtained by taking the reference clock as a reference clock to the second FPGA system control module, the second clock synchronization module is electrically connected with each DAC module and respectively inputs a first sampling clock obtained by taking the reference clock as the reference clock to each DAC module, and the phases of the first reference clock and the first sampling clock are aligned; the second FPGA system control module is respectively and electrically connected with each DAC module and respectively inputs a data clock and a synchronous signal which are obtained by taking the first reference clock as reference to each DAC module;
the third clock synchronization module is electrically connected with the third FPGA system control module and inputs a second reference clock obtained by taking the reference clock as a reference clock to the third FPGA system control module, and the third FPGA system control module outputs an LVDS time sequence signal by taking the second reference clock as a reference.
2. The high-precision synchronous analog-digital mixed signal generator for the image sensor as claimed in claim 1, wherein the clock board further comprises a first network module, the first network module is electrically connected with the first FPGA system control module; the AWG board card also comprises a second network module, and the second network module is electrically connected with the second FPGA system control module; the LVDS board card further comprises a third network module, and the third network module is electrically connected with the third FPGA system control module; the first network module is respectively and electrically connected with the second network module and the third network module and respectively inputs communication signals to the second network module and the third network module.
3. The high precision synchronous analog-to-digital mixed signal generator for image sensor of claim 2, wherein the AWG board further comprises a second local reference clock module electrically connected to the second clock synchronization module and inputting a second reference clock to the second clock synchronization module as a reference clock of the second clock synchronization module; the LVDS board card further comprises a third local reference clock module, wherein the third local reference clock module is electrically connected with the third clock synchronization module and inputs a third reference clock to the third clock synchronization module as a reference clock of the third clock synchronization module.
4. The high-precision synchronous analog-digital mixed signal generator for the image sensor as claimed in claim 3, wherein the LVDS board further comprises a FIFO memory, and the FIFO memory is electrically connected to the third FPGA system control module and the third network module respectively.
5. The high accuracy synchronous A/D mixed signal generator for image sensor of claim 4, wherein the first, second and third local reference clock modules are low noise low frequency crystal oscillators and the first, second and third network modules are Ethernet communication modules.
6. The high precision synchronous analog-to-digital mixed signal generator for image sensor of claim 5, wherein the first, second and third local reference clock modules are connected with the SEC ports of the first, second and third clock synchronization modules, respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021507881.3U CN212752227U (en) | 2020-07-27 | 2020-07-27 | High-precision synchronous analog-digital mixed signal generator for image sensor |
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| CN202021507881.3U CN212752227U (en) | 2020-07-27 | 2020-07-27 | High-precision synchronous analog-digital mixed signal generator for image sensor |
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