CN117170048B - Three-dimensional packaging photoelectric integrated chip structure and preparation method thereof - Google Patents
Three-dimensional packaging photoelectric integrated chip structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 9
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 54
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Abstract
The invention provides a three-dimensional packaging photoelectric integrated chip structure and a preparation method thereof, relates to the field of integrated optics, and can solve the problem of optical, electrical and thermal crosstalk in a chip. The three-dimensional packaging photoelectric integrated chip structure comprises: a silicon optical chip; the electric chip comprises a first electric chip and a second electric chip which are respectively arranged on the upper side and the lower side of the silicon optical chip; the interconnection layer comprises a first interconnection layer and a second interconnection layer, wherein the first electric chip is connected with the silicon optical chip through flip-chip bonding through the first interconnection layer, and the second electric chip is connected with the silicon optical chip through flip-chip bonding through the second interconnection layer; the PCB bottom plate is fixedly meshed with the silicon optical chip through a slot; and the two ends of the lead group are respectively connected with the silicon optical chip and the PCB bottom plate. The three-dimensional packaging photoelectric integrated chip structure provided by the invention has high integration level, can shorten the electrical interconnection length, reduce the optical, electrical and thermal crosstalk in the structure and improve the optical performance.
Description
Technical Field
The invention relates to the field of integrated optics, in particular to a three-dimensional packaging photoelectric integrated chip structure and a preparation method thereof.
Background
With the continuous development of 5G, everything interconnection, virtual reality and automatic driving, the traditional communication network faces huge pressure and challenges, and the optical communication system is widely applied in the communication field because of the excellent performances of low loss, large bandwidth capacity, electromagnetic interference resistance and the like. As a key device in an optical communication system, an optical module plays roles of photoelectric conversion and electro-optical conversion. The data volume of the global communication system is increased explosively, and when the size of the equipment is fixed, the corresponding interface density is higher and higher, so that the optical module is required to be developed towards the directions of high density, small volume and high speed.
Because the preparation of the silicon-based photonic device can be compatible with the traditional CMOS (complementary metal oxide semiconductor) process, the silicon-based photonic device has the advantages of low cost, high integration level and high reliability, and the silicon-based integration becomes an extremely competitive optoelectronic integration platform. The silicon-based material can integrate most optoelectronic devices such as optical waveguide, modulator, photoelectric detector, array waveguide grating, polarization rotator and the like, can realize functions such as light receiving and transmitting, multiplexing and the like on the same chip, and has great integration potential. Silicon-based optical transceiver modules are also widely used in data centers. However, as the integration level increases, the interval between optoelectronic devices decreases, and the performance degradation caused by crosstalk affects the performance of the optical module to a great extent.
Disclosure of Invention
First, the technical problem to be solved
In view of the above-mentioned shortcomings, the main purpose of the present invention is to provide a three-dimensional packaging optoelectronic integrated chip structure and a preparation method thereof, wherein a silicon substrate in the structure can be shared by an upper layer of optoelectronic chip and a lower layer of optoelectronic chip, so that the packaging density can be further improved, and the development requirement of a high-speed high-density optical module can be met. By arranging the photoelectric devices in the upper layer and the lower layer of the chip structure respectively, crosstalk of the transmitting end and the receiving end of the chip structure is also obviously inhibited.
(II) technical scheme
In order to achieve the above object, according to a first aspect of the present invention, there is provided a three-dimensional packaged optoelectronic integrated chip structure, comprising: a silicon optical chip; the electric chip comprises a first electric chip and a second electric chip which are respectively arranged on the upper side and the lower side of the silicon optical chip; the interconnection layer comprises a first interconnection layer and a second interconnection layer, wherein the first electric chip is connected with the silicon optical chip through flip-chip bonding through the first interconnection layer, and the second electric chip is connected with the silicon optical chip through flip-chip bonding through the second interconnection layer; the PCB bottom plate is fixedly meshed with the silicon optical chip through a slot; and the two ends of the lead group are respectively connected with the silicon optical chip and the PCB bottom plate.
In the scheme, the silicon optical chip comprises a silicon substrate, a first silicon optical chip and a second silicon optical chip, wherein the first silicon optical chip sequentially grows a top silicon dioxide layer, a top silicon layer and a top coating layer on the silicon substrate from bottom to top; the second silicon optical chip is formed by sequentially and inversely growing bottom silicon dioxide, bottom silicon and a bottom coating layer on the silicon substrate from top to bottom.
In the scheme, the thickness of the top layer silicon and the bottom layer silicon is 220nm; the thickness of the top silicon dioxide and the bottom silicon dioxide insulating layers is 2-3 mu m.
In the scheme, the top layer coating layer is directly formed on the top layer silicon growing silicon dioxide, the bottom layer coating layer is directly formed on the bottom layer silicon growing silicon dioxide, and the top layer coating layer and the bottom layer coating layer are used for protecting the device structure, and the thickness is 2-4 mu m.
In the scheme, the interconnection layer comprises welding convex points and filling glue materials, wherein the welding convex points are made of tin materials, and the filling glue is made of epoxy resin materials.
In the scheme, the lead group comprises a first lead group and a second lead group which are vertically and symmetrically arranged, and the silicon optical chip and the left side and the right side of the PCB bottom plate are respectively electrically welded through the first lead group and the second lead group, wherein a welding area is a welding pad.
In the above scheme, the chip structure comprises a transmitting end and a receiving end, wherein the transmitting end comprises a modulator, a wavelength division multiplexing device, an end surface coupling device and a connecting waveguide, and the receiving end comprises a detector, a wavelength division multiplexing device, an end surface coupling device and a connecting waveguide.
In the scheme, the chip structure performs optical signal transmission with the outside through the optical fiber array, and the optical fiber array is arranged on the same side of the chip structure; the optical fiber array comprises a first optical fiber array and a second optical fiber array, wherein the first optical fiber array and the second optical fiber array are symmetrically arranged on the upper side and the lower side of the silicon optical chip respectively.
The invention provides a preparation method of a three-dimensional packaging photoelectric integrated chip structure, which is characterized by comprising the following steps: step S1, providing a silicon substrate, and growing a top silicon dioxide layer, a top silicon layer and a top coating layer on the silicon substrate in sequence from bottom to top; sequentially and inversely growing bottom silicon dioxide, bottom silicon and a bottom coating layer on a silicon substrate from top to bottom to form a silicon optical chip; step S2, arranging a first electric chip and a second electric chip on the silicon optical chip sequentially through the interconnection layer; step S3, providing a PCB base plate, and hollowing the PCB base plate to prepare a positioning groove; hollowing and slotting the silicon substrate of the silicon optical chip; the PCB bottom plate and the silicon optical chip are meshed and fixed; and S4, connecting the silicon optical chip with the PCB bottom plate through a lead group.
In the scheme, the top layer silicon and the bottom layer silicon are respectively etched, doped and subjected to metal epitaxy to form the active and passive photonic devices which are interconnected on the chip.
(III) beneficial effects
The technical scheme of the embodiment of the invention has at least the following beneficial effects:
(1) The upper and lower layers of photoelectric integrated chips are reversely arranged together, and the silicon substrate is shared, so that the integration density can be improved;
(2) The three-dimensional packaging mode is adopted, so that the integration density is improved, the electrical interconnection length is further shortened, and better high-frequency performance can be obtained;
(3) The top silicon layer and the bottom silicon layer of the structure can respectively manufacture photon devices required by the emitting end and the receiving end, and the upper and lower layered design of the structure can reduce internal optical, electrical and thermal crosstalk and improve the structural performance;
(4) Different materials can be selected for the top silicon layer and the bottom silicon layer, heterogeneous integration is facilitated, and the method can be widely applied to optical modules.
Drawings
FIG. 1 shows a schematic diagram of a three-dimensional packaged optoelectronic integrated chip structure in accordance with an embodiment of the present invention;
FIG. 2 illustrates a schematic diagram of a portion of a three-dimensional packaged optoelectronic integrated chip structure in accordance with an embodiment of the present invention;
FIG. 3 shows a schematic diagram of a silicon optical chip structure in accordance with an embodiment of the present invention;
fig. 4 shows a flowchart of a method for fabricating a three-dimensional packaged optoelectronic integrated chip structure according to an embodiment of the present invention.
[ description of reference numerals ]
1-a first electrical chip; 2-silicon photonics chip; 200-top layer coating; 201-top layer silicon; 202-top layer silicon dioxide; 203-a silicon substrate; 204-underlying silicon dioxide; 205-underlying silicon; 206—an underlying cladding layer; 3-a second electrical chip; 4-a first interconnect layer; 5-a second interconnect layer; 6-a PCB base plate; 71-a first set of leads; 72-a second set of leads; 8-bonding pads; 9-a first fiber array; 10-a second fiber array; 11-golden finger.
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
Fig. 1 shows a schematic diagram of a three-dimensional packaged optoelectronic integrated chip structure according to an embodiment of the present invention, and fig. 2 shows a schematic diagram of a portion of the three-dimensional packaged optoelectronic integrated chip structure according to an embodiment of the present invention.
Referring specifically to fig. 1 and 2, an embodiment of the present invention provides a three-dimensional packaged optoelectronic integrated chip structure, including: a silicon optical chip 2; the electric chip comprises a first electric chip 1 and a second electric chip 3 which are respectively arranged on the upper side and the lower side of the silicon optical chip 2; the interconnection layer comprises a first interconnection layer 4 and a second interconnection layer 5, wherein the first electric chip 1 is connected with the silicon optical chip 2 through flip-chip bonding by the first interconnection layer 4, and the second electric chip 3 is connected with the silicon optical chip 2 through the second interconnection layer 5 through flip-chip bonding; the PCB bottom plate 6 is fixedly meshed with the silicon optical chip 2 through a slot; and two ends of the lead wire group are respectively connected with the silicon optical chip 2 and the PCB (printed circuit) bottom plate 6.
Fig. 3 shows a schematic structural diagram of a silicon optical chip according to an embodiment of the present invention.
Specifically, as shown in fig. 3, the silicon optical chip 2 includes a silicon substrate 203, a first silicon optical chip and a second silicon optical chip, wherein the first silicon optical chip is formed by sequentially growing a top silicon dioxide 202, a top silicon 201 and a top cladding layer 200 on the silicon substrate 203 from bottom to top; the second silicon photo chip is formed by flip-chip growing a bottom silicon dioxide 204, a bottom silicon 205 and a bottom cladding layer 206 on a silicon substrate 203 from top to bottom.
Wherein the thickness of the top layer silicon 201 and the bottom layer silicon 205 is 220nm; the thickness of the insulating layer of the top silicon dioxide 202 and the bottom silicon dioxide 204 is 2-3 μm. The top layer 200 is directly formed by growing silicon dioxide on the top layer silicon 201, the bottom layer 206 is directly formed by growing silicon dioxide on the bottom layer silicon 205, and the top layer 200 and the bottom layer 206 are used for protecting the device structure and have the thickness of 2-4 μm.
In the embodiment of the invention, the interconnection layer comprises welding convex points and filling glue materials, wherein the welding convex points are made of tin materials, and the filling glue is made of epoxy resin materials.
In the embodiment of the invention, the lead group comprises a first lead group 71 and a second lead group 72 which are arranged symmetrically up and down, and the silicon optical chip 2 and the left and right sides of the PCB bottom plate 6 are respectively electrically welded through the first lead group 71 and the second lead group 72, wherein the welding area is a bonding pad 8.
In the present chip structure, the top silicon 201 and the bottom silicon 205 are etched, doped, and metal-epitaxially formed to form on-chip interconnected active and passive photonic devices, respectively. For example, a stripe waveguide or a ridge waveguide may be formed by etching. The silicon-based electro-optic modulator or the germanium-silicon photoelectric detector can be prepared through diffusion, doping, etching and other processes.
The top silicon layer can also be a top lithium niobate film, the top lithium niobate film adopts X-cut Y-transmission type lithium niobate with the thickness of 600nm, a waveguide is formed by etching through inductively coupled plasma equipment, and an electro-optic modulator with large modulation bandwidth and low half-wave voltage can be prepared by utilizing the excellent electro-optic characteristic of the lithium niobate.
In the embodiment of the invention, the chip structure comprises a transmitting end and a receiving end, wherein the transmitting end comprises a modulator, a wavelength division multiplexing device, an end surface coupling device and a connecting waveguide, and the receiving end comprises a detector, a wavelength division multiplexing device, an end surface coupling device and a connecting waveguide.
The chip structure performs optical signal transmission with the outside through an optical fiber array, and the optical fiber array is arranged on the same side of the chip structure; the optical fiber array comprises a first optical fiber array 9 and a second optical fiber array 10, wherein the first optical fiber array 9 and the second optical fiber array 10 are symmetrically arranged on the upper side and the lower side of the silicon optical chip 2 respectively. Also, as shown in FIG. 2, the fiber arrays are all located on the left side of the chip structure.
The chip structure performs electrical signal transmission with the outside through the golden finger 11, and the golden finger 11 is located on the right side of the chip structure.
In the embodiment of the invention, the working process of the whole three-dimensional packaging photoelectric integrated chip structure mainly comprises the following steps:
the working process of the transmitting end is that light emitted by a laser is used as an optical carrier carrying information, the first electric chip 1 is driven to enable the modulator to work, then the optical carrier is subjected to signal modulation, and after the optical carrier is transmitted through the waveguide core layer, the optical carrier is coupled with the first optical fiber array 9 of the transmitting end, and light wave signals carrying information are transmitted outside the whole chip structure. The laser may be attached to or grown on the top silicon 201, and the modulator and waveguide core are formed by etching on the top silicon 201.
The working process of the receiving end is that the light wave signal received from the outside is coupled into the waveguide core layer through the second optical fiber array 10 of the receiving end of the chip structure, and is transmitted to the detector for photoelectric conversion, and the electric signal carried by the light wave signal is recovered. Wherein the waveguide core and the detector are both formed by etching on the underlying silicon 205.
It should be noted that, in the embodiment of the present invention, for SOI (silicon on insulator) homogeneous integration system, the waveguide core layer is prepared in the top layer silicon 201 and the bottom layer silicon 205. The transmitting end, for example, selects a 4-path Mach-Zehnder modulator to modulate optical carriers with different wavelengths, and after the optical carriers are combined by a wavelength division multiplexer, signals are sent to the outside of the optical module by the first optical fiber array 9. After receiving the optical signal from the outside of the optical module, the receiving end demultiplexes the optical signal by a wavelength division multiplexer, and the receiving end recovers the signal by adopting a 4-path GeSi detector. When the transmission rate of the Mach-Zehnder modulator and the GeSi detector reaches 100G for a single wave, a 400G optical module can be formed. When the transmission rate of the Mach-Zehnder modulator and the GeSi detector reaches 200G for a single wave, an 800G optical module can be formed.
For SOI (silicon on insulator) and LNOI (lithium niobate thin film on insulator) hybrid integrated systems, the waveguide core layer is fabricated in the top lithium niobate thin film and the bottom silicon 205. The transmitting end selects 4 paths of thin film lithium niobate micro-ring modulators to modulate optical carriers with different wavelengths, wherein the 4 paths of micro-rings respectively resonate at frequencies corresponding to the central wavelengths of the 4 paths of lasers, and meanwhile, the functions of wavelength division multiplexing and modulation are achieved. The receiving end uses a wavelength division multiplexer to demultiplex the 4 paths of optical signals, and then uses a GeSi detector to recover the signals. When the transmission rate of the thin film lithium niobate micro-ring modulator and the GeSi detector reaches 100G of single wave, a 400G optical module can be formed. When the transmission rate of the thin film lithium niobate micro-ring modulator and the GeSi detector reaches 200G of single wave, an 800G optical module can be formed.
In summary, the invention provides a novel photonic chip structure suitable for SOI, LNOI and other material systems, the photonic devices at the emitting end and the receiving end of the optical module can be respectively arranged in the upper layer and the lower layer of the novel photonic chip, and the size of the silicon optical chip is greatly reduced by sharing the silicon substrate, so that the integration level of the optical module can be further improved. In addition, because the transmitting end and the receiving end of the optical module are spatially arranged in a layered manner, crosstalk is also inhibited, and the performance of the optical module is more stable and excellent. The novel photonic chip structure is based on a silicon-based material system, is compatible with the mature CMOS process at present, has potential economic and application values, and is expected to be widely applied in the field of integrated photoelectricity.
Based on the three-dimensional packaging photoelectric integrated chip structure, the invention also provides a preparation method of the three-dimensional packaging photoelectric integrated chip structure.
Fig. 4 schematically illustrates a flowchart of a method for fabricating a three-dimensional packaged optoelectronic integrated chip structure according to an embodiment of the invention.
Referring specifically to fig. 4, a specific process of the method for manufacturing a three-dimensional packaged optoelectronic integrated chip structure according to an embodiment of the present invention includes steps S1 to S4.
In operation S1, a silicon substrate 203 is provided, and a top silicon dioxide 202, a top silicon 201 and a top cladding layer 200 are grown on the silicon substrate 203 in sequence from bottom to top; a bottom silicon dioxide 204, a bottom silicon 205 and a bottom coating 206 are sequentially and inversely grown on the silicon substrate 203 from top to bottom to form a silicon optical chip 2;
in the operation step S2, a first electrical chip 1 and a second electrical chip 3 are sequentially arranged on the silicon optical chip 2 through the interconnection layer;
in the operation step S3, a PCB substrate 6 is provided, and a positioning groove is prepared by hollowing out the PCB substrate 6; hollowing and slotting the silicon substrate 203 of the silicon optical chip 2; the PCB bottom plate 6 is meshed and fixed with the silicon optical chip 2;
in operation S4, the silicon photochip 2 and the PCB substrate 6 are connected by a lead set.
In step S1, the top layer silicon 201 and the bottom layer silicon 205 are etched, doped, and metal-epitaxially formed into on-chip interconnected active and passive photonic devices, respectively.
In summary, the invention provides a three-dimensional packaging photoelectric integrated chip structure and a preparation method thereof, wherein the chip structure adopts an upper layer and a lower layer of photoelectric integrated chips to be inversely arranged together, and the chip structure shares a silicon substrate, so that the integration density can be improved; secondly, a three-dimensional packaging mode is adopted, so that the integration density is improved, the electrical interconnection length is further shortened, and better high-frequency performance can be obtained; the structure is layered up and down, so that the optical, electric and thermal crosstalk in the optical structure can be reduced, and the performance of the optical module is improved; different materials can be selected for the top silicon layer and the bottom silicon layer, heterogeneous integration is facilitated, and the method can be widely applied to optical modules.
The foregoing embodiments have been provided for the purpose of illustrating the general principles of the present invention, and are more fully described herein with reference to the accompanying drawings, in which the principles of the present invention are shown and described, and in which the general principles of the invention are defined by the appended claims.
Claims (8)
1. A three-dimensional packaged optoelectronic integrated chip structure, comprising:
a silicon optical chip (2);
the electric chip comprises a first electric chip (1) and a second electric chip (3) which are respectively arranged at the upper side and the lower side of the silicon optical chip (2);
the interconnection layer comprises a first interconnection layer (4) and a second interconnection layer (5),
the first electric chip (1) is connected with the silicon optical chip (2) through flip-chip bonding through a first interconnection layer (4), and the second electric chip (3) is connected with the silicon optical chip (2) through flip-chip bonding through a second interconnection layer (5);
the PCB bottom plate (6) is fixedly meshed with the silicon optical chip (2) through a slot;
the two ends of the lead group are respectively connected with the silicon optical chip (2) and the PCB bottom plate (6);
the silicon optical chip (2) comprises a silicon substrate (203), a first silicon optical chip and a second silicon optical chip,
the first silicon optical chip is formed by sequentially growing a top silicon dioxide layer (202), a top silicon layer (201) and a top coating layer (200) on a silicon substrate (203) from bottom to top;
the second silicon optical chip is formed by sequentially and inversely growing bottom silicon dioxide (204), bottom silicon (205) and a bottom coating layer (206) on a silicon substrate (203) from top to bottom;
the chip structure comprises a transmitting end and a receiving end,
the transmitting end comprises a modulator, a wavelength division multiplexing device, an end surface coupling device and a connecting waveguide, and the receiving end comprises a detector, a wavelength division multiplexing device, an end surface coupling device and a connecting waveguide.
2. The three-dimensional package optoelectronic integrated chip structure of claim 1, wherein the top layer silicon (201) and the bottom layer silicon (205) have a thickness of 220nm;
the thickness of the insulating layer of the top silicon dioxide (202) and the bottom silicon dioxide (204) is 2-3 μm.
3. The three-dimensional package optoelectronic integrated chip structure of claim 2, wherein the top layer (200) is formed by directly growing silicon dioxide on the top layer silicon (201), the bottom layer (206) is formed by directly growing silicon dioxide on the bottom layer silicon (205), and the top layer (200) and the bottom layer (206) are used for protecting the device structure, and have a thickness of 2-4 μm.
4. The three-dimensional package optoelectronic integrated chip structure of claim 1, wherein the interconnect layer comprises solder bumps and a filler material, the solder bumps being of tin material, the filler material being of epoxy material.
5. The three-dimensional package optoelectronic integrated chip structure according to claim 1, wherein the lead group comprises a first lead group (71) and a second lead group (72) which are arranged symmetrically up and down, the silicon optical chip (2) and the left and right sides of the PCB substrate (6) are electrically welded through the first lead group (71) and the second lead group (72), respectively, wherein the welded area is a bonding pad (8).
6. The three-dimensional package optoelectronic integrated chip structure of claim 1, wherein the chip structure is in optical signal transmission with the outside through an optical fiber array, the optical fiber array being disposed on the same side of the chip structure;
the optical fiber array comprises a first optical fiber array (9) and a second optical fiber array (10), wherein the first optical fiber array (9) and the second optical fiber array (10) are symmetrically arranged on the upper side and the lower side of the silicon optical chip (2) respectively.
7. A method for manufacturing a three-dimensional package optoelectronic integrated chip structure as claimed in any one of claims 1 to 6, comprising:
step S1, providing a silicon substrate (203), and growing a top silicon dioxide (202), a top silicon (201) and a top coating layer (200) on the silicon substrate (203) in sequence from bottom to top; a bottom silicon dioxide (204), a bottom silicon (205) and a bottom coating layer (206) are sequentially and inversely grown on a silicon substrate (203) from top to bottom to form a silicon optical chip (2);
step S2, arranging a first electric chip (1) and a second electric chip (3) on the silicon optical chip (2) sequentially through an interconnection layer;
step S3, providing a PCB base plate (6), and hollowing out the PCB base plate (6) to prepare a positioning groove; hollowing and slotting the silicon substrate (203) of the silicon optical chip (2); the PCB bottom plate (6) and the silicon optical chip (2) are meshed and fixed;
and S4, connecting the silicon optical chip (2) with the PCB base plate (6) through a lead group.
8. The method of manufacturing according to claim 7, further comprising:
etching, doping and metal epitaxy are performed on the top layer silicon (201) and the bottom layer silicon (205) respectively, forming on-chip interconnected active and passive photonic devices.
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