CN117170016B - High-integration photon chip structure - Google Patents
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- CN117170016B CN117170016B CN202311450812.1A CN202311450812A CN117170016B CN 117170016 B CN117170016 B CN 117170016B CN 202311450812 A CN202311450812 A CN 202311450812A CN 117170016 B CN117170016 B CN 117170016B
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- 230000003287 optical effect Effects 0.000 claims abstract description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 37
- 239000010703 silicon Substances 0.000 claims abstract description 37
- 239000002346 layers by function Substances 0.000 claims abstract description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 230000008878 coupling Effects 0.000 claims abstract description 28
- 238000010168 coupling process Methods 0.000 claims abstract description 28
- 238000005859 coupling reaction Methods 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims abstract description 24
- 230000010354 integration Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 16
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 16
- 239000013307 optical fiber Substances 0.000 claims abstract description 12
- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 9
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 238000001514 detection method Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000004904 shortening Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 5
- 239000011247 coating layer Substances 0.000 description 3
- JAYCNKDKIKZTAF-UHFFFAOYSA-N 1-chloro-2-(2-chlorophenyl)benzene Chemical compound ClC1=CC=CC=C1C1=CC=CC=C1Cl JAYCNKDKIKZTAF-UHFFFAOYSA-N 0.000 description 2
- 101100084627 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) pcb-4 gene Proteins 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004038 photonic crystal Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Abstract
The invention provides a high-integration photonic chip structure, which relates to the technical field of integrated optics and comprises the following components: the first photon chip comprises a top functional layer (201), an upper silicon dioxide insulating layer (202) and a silicon substrate (203); the second photon chip comprises a bottom functional layer (205), a lower silicon dioxide insulating layer (204) and a silicon substrate (203); the first and second photonic chips are flip-chip bonded together, sharing a silicon substrate (203). The chip structure is arranged inside the optical module in a vertical packaging mode, can be connected with the optical fiber in a grating coupling mode, is convenient for the on-line detection of the optical chip, and has important significance for shortening the manufacturing flow of the optical module. The chip structure is used for inversely mounting the top-layer photonic integrated chip and the bottom-layer photonic integrated chip together, and sharing the silicon substrate (203), so that the integration density can be improved on the basis that the thickness of the photonic chip is not obviously increased, the crosstalk inside the optical transceiver module can be reduced through layered design, and the performance of the optical module is improved.
Description
Technical Field
The invention relates to the technical field of integrated optics, in particular to a photonic chip structure with high integration level.
Background
The rapid development of the fields of big data, internet of things, cloud computing and the like enables media for information storage and exchange to gradually migrate to a data center, the scale of the data center is rapidly increased, and the corresponding interface density and data bandwidth are continuously increased. Optical communication is characterized by large bandwidth, low loss and electromagnetic interference resistance, and optical modules are widely applied to data centers.
The explosive growth of data traffic requires the development of a data center exchange architecture to higher speed and higher communication capacity on the premise of small volume, the speed of a core photoelectric device in an optical module based on new material new structure systems such as plasmons, photonic crystals and the like is higher, the size of the device is smaller, and the size of a photonic chip can be expected to be reduced to the order of hundred micrometers. At that time, packaging will become an important factor for restricting the speed increase of the optical module and controlling the production cost.
Disclosure of Invention
In view of the above problems, the present invention provides a photonic chip structure with high integration, which solves the problems of limited photonic chip density, inconvenient online test caused by an end-face coupling mode in the conventional optical module, and the like.
One aspect of the present invention provides a high integration photonic chip structure comprising: the first photon chip comprises a top functional layer, an upper silicon dioxide insulating layer and a silicon substrate; the second photon chip comprises a bottom functional layer, a lower silicon dioxide insulating layer and a silicon substrate; and the first photon chip and the second photon chip are in flip-chip bonding together and share the silicon substrate.
Optionally, the top functional layer includes a laser, an electro-optical modulator, a first wavelength division multiplexer, a first waveguide, and a first coupling structure thereon; when the laser emits a first optical signal, the first optical signal carries information to be transmitted after being modulated by the electro-optical modulator, the first optical signal is transmitted to the first coupling structure through the first wavelength division multiplexer and the first waveguide, and is output to a first optical fiber array arranged outside through the first coupling structure; the bottom layer functional layer comprises a second coupling structure, a second waveguide, a second wavelength division multiplexer and a photoelectric detector; when a second optical fiber array arranged outside transmits a second optical signal, the second optical signal is coupled to the second waveguide through the second coupling structure, and is transmitted to the photoelectric detector through the second wavelength division multiplexer to be subjected to photoelectric conversion, so that information carried by the second optical signal is obtained.
Optionally, the first coupling structure and the second coupling structure comprise grating coupling structures.
Optionally, the method further comprises: the driving chip is connected with the electro-optical modulator and used for driving the electro-optical modulator to work; and the transimpedance amplifier chip is connected with the photoelectric detector and used for driving the photoelectric detector to work.
Optionally, the electro-optical modulator is matched with the height of the metal pad of the driving chip, and the photodetector is matched with the height of the transimpedance amplifier chip, so that the bonding wire connected with the metal pad is shortest.
Optionally, the driving chip, the transimpedance amplifier chip, the first photonic chip and the second photonic chip are arranged on the same PCB, wherein the first photonic chip and the second photonic chip are vertically packaged on the PCB, the driving chip is arranged on one side of the first photonic chip facing, and the transimpedance amplifier chip is arranged on one side of the second photonic chip facing.
Optionally, the surfaces of the top functional layer and the bottom functional layer are covered with a silicon dioxide coating layer.
Optionally, the top functional layer material is a silicon or lithium niobate film; the bottom functional layer is made of silicon.
Optionally, the electro-optic modulator is a silicon-based mach-zehnder modulator or a silicon-based micro-ring modulator, and the photodetector is a silicon-based germanium-silicon detector.
Optionally, the electro-optical modulator is a thin film lithium niobate base Mach-Zehnder modulator or a thin film lithium niobate base micro-ring modulator, and the photoelectric detector is a silicon-based germanium-silicon detector.
The above at least one technical scheme adopted in the embodiment of the invention can achieve the following beneficial effects:
the embodiment of the invention provides a high-integration-level vertical packaging photon integrated chip structure, wherein a silicon substrate can be shared by a top layer and a bottom layer functional layer in the structure, so that the packaging density is further improved, and the development requirement of a high-density optical module is met. By arranging the photoelectric devices in the upper functional layer and the lower functional layer of the photon chip respectively, crosstalk of the transmitting end and the receiving end of the optical module is obviously inhibited. In addition, the vertically packaged photon chip can be coupled with an optical fiber array by adopting a grating, so that the on-line batch detection is facilitated. The bonding pad on the photon chip for interconnection with the external electric chip can be adjusted at will according to the height of the electric chip, so that the length of a bonding wire is shortened, the parasitic effect is reduced, and the speed of the optical module is further improved.
Drawings
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
fig. 1 schematically illustrates a schematic diagram of a photonic chip structure with high integration according to an embodiment of the present invention;
fig. 2 schematically illustrates a structural schematic diagram of a PCB board provided by an embodiment of the present invention.
Reference numerals illustrate:
1-driving an electrical chip; a 2-photon chip; a 3-transimpedance amplifier chip; 4-a PCB board; 5-bonding wires; 6-a first fiber array; 7-a second fiber array; 201-top layer functional layer; 202-an upper silicon dioxide insulating layer; 203-a silicon substrate; 204-an underlying silicon dioxide insulating layer; 205-top functional layer.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the invention. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention. It may be evident, however, that one or more embodiments may be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.
As shown in fig. 1, the embodiment of the present invention provides a photonic chip structure with high integration, and the photonic chip 2 includes a first photonic chip and a second photonic chip. A first photonic chip comprising a top functional layer 201, an upper silicon dioxide insulating layer 202, and a silicon substrate 203; a second photonic chip comprising a bottom functional layer 205, a lower silicon dioxide insulating layer 204, and a silicon substrate 203; wherein the first photonic chip and the second photonic chip are flip-chip bonded together, sharing the silicon substrate 203. The top layer and the bottom layer photon integrated chips are inversely arranged together, and share the silicon substrate 203, so that the integration density can be improved on the basis that the thickness of the photon chip 2 is not obviously increased.
Optionally, the top functional layer 201 is made of a silicon or lithium niobate thin film, the silicon thickness is 220nm, and the lithium niobate thin film thickness is 600nm.
Optionally, the thickness of the upper silicon dioxide insulating layer 202 is 2-3 μm.
Optionally, the top functional layer 201 may be etched to cover a silicon dioxide coating layer, so as to protect the device structure, and the thickness is 2-4 μm.
Optionally, the underlayer functional layer 205 is silicon with a thickness of 220nm.
Optionally, the thickness of the underlying silicon dioxide insulating layer 204 is 2-3 μm.
The top functional layer 201 and the bottom functional layer 205 can be used for preparing waveguide structures of active and passive photonic devices by photoetching, etching and other methods. When the novel photon structure is applied to an optical module, a coupling structure of a transmitting end, an electro-optical modulator, a wavelength division multiplexer and the like can be prepared in a first photon chip, and a coupling structure of a receiving end, the wavelength division multiplexer, a photoelectric detector and the like can be prepared in a second photon chip, so that crosstalk between the transmitting end and the receiving end can be restrained, and the integration level is improved.
Optionally, the top functional layer 201 and the bottom functional layer 205 may be etched to cover a silicon dioxide coating layer, where the thickness is 2-4 μm.
In this embodiment, the top functional layer 201 includes a laser, an electro-optical modulator, a first wavelength division multiplexer, a first waveguide, and a first coupling structure thereon. When the laser emits the first optical signal, the first optical signal carries information to be transmitted after being modulated by the electro-optical modulator, the first optical signal is transmitted to the first coupling structure through the first wavelength division multiplexer and the first waveguide, and is output to the first optical fiber array 6 of the peripheral device through the first coupling structure. The bottom functional layer 205 includes a second coupling structure, a second waveguide, a second wavelength division multiplexer, and a photodetector; when the second optical fiber array 7 arranged outside transmits a second optical signal, the second optical signal is coupled to the second waveguide through the second coupling structure, and is transmitted to the photoelectric detector through the second wavelength division multiplexer to perform photoelectric conversion, so that information carried by the second optical signal is obtained. In the chip structure, the photonic devices of the emitting end and the receiving end of the optical module are respectively arranged on the top layer and the bottom layer of the photonic chip 2, so that the optical, electric and thermal crosstalk can be inhibited, and the integration level is improved.
As shown in fig. 1, the chip structure further includes: the driving chip 1 is connected with the electro-optical modulator and used for driving the electro-optical modulator to work; and the transimpedance amplifier chip 3 is connected with the photoelectric detector and used for driving the photoelectric detector to work. The driving chip 1, the transimpedance amplifier chip 3, the first photon chip and the second photon chip are arranged on the same PCB 4, wherein the first photon chip and the second photon chip are vertically packaged in a positioning groove (shown in fig. 2) on the PCB 4, the driving chip 1 is arranged on one side of the first photon chip facing, and the transimpedance amplifier chip 3 is arranged on one side of the second photon chip facing. The vertically packaged photonic chip 2 can be coupled with an optical fiber array by adopting a grating, so that the on-line batch detection is facilitated.
In addition, the electro-optical modulator is matched with the metal bonding pad of the driving chip 1 in height, the photoelectric detector is matched with the transimpedance amplifier chip 3 in height, so that the length of the bonding wire 5 is shortened, the bonding wire connected with the metal bonding pad is shortest, the parasitic effect is reduced, better high-frequency performance can be obtained, and the speed of the optical module is further improved.
Specifically, referring to fig. 1, the working process of the whole photonic chip 2 is that a first optical signal excited by a laser is modulated by an electro-optical modulator and carries information to be transmitted, and the information is transmitted to a grating coupler of a transmitting end through a waveguide in a top functional layer 201. After the periodic structure of the grating diffracts the optical wave signal, the change of the propagation direction of the optical field is realized, so that the optical wave signal is coupled with the first optical fiber array 6 at the transmitting end for output. The second optical signal received from the outside of the module is coupled into the waveguide structure of the bottom functional layer 205 through the second optical fiber array 7 of the receiving end, and is transmitted to the photoelectric detector to perform photoelectric conversion, so as to recover the electrical signal carried by the second optical signal. The electric chip driving the electro-optical modulator to work is a driving chip 1, the electric chip driving the photoelectric detector to work is a transimpedance amplifier chip 3, and bonding pads on the electro-optical modulator and the photoelectric detector are respectively located at the same height in space with bonding pads of the driving chip 1 and the transimpedance amplifier 3, so that the length of a bonding lead 5 is shortened, and the bandwidth of a device is improved.
Alternatively, the first coupling structure and the second coupling structure can adopt grating coupling structures, so that the optical chips can be conveniently detected in batches on line, and the method has important significance in shortening the optical module manufacturing process.
In this embodiment, the photonic chip 2 may be integrated homogeneously based on SOI material, where the electro-optical modulator is a silicon-based mach-zehnder modulator or a silicon-based micro-ring modulator, and the photodetector is a silicon-based sige detector.
In another embodiment, the photonic chip 2 may be heterogeneous integrated with the LNOI material based on SOI, where the electro-optical modulator is a thin-film lithium niobate-based mach-zehnder modulator or a thin-film lithium niobate-based micro-ring modulator, and the photodetector is a silicon-based sige detector.
When the optical module realizes the wavelength division multiplexing function, the wavelength division multiplexer and the Mach-Zehnder modulator can be cascaded, the wavelength division multiplexer and the detector can be cascaded, and the transmitting end can also adopt the micro-ring modulator to realize the modulation and wavelength division multiplexing functions.
When the optical module adopts a 4-channel wavelength division multiplexing mode, if the speed of the modulator and the germanium-silicon detector reaches 100G of single wave, a 400G optical module can be formed; if the modulator and silicon germanium detector rates reach 200G for a single wave, an 800G optical module can be formed. When the optical module takes the form of 8-channel wavelength division multiplexing, 800G and 1.6T optical modules can be formed accordingly.
In summary, the invention provides a vertically packaged photonic chip structure with high integration, the substrate material is silicon, and the photonic devices at the emitting end and the receiving end of the optical module are respectively arranged on the top layer and the bottom layer of the photonic chip 2, so that optical, electrical and thermal crosstalk can be inhibited. In addition, the emitting end and the receiving end share the silicon substrate 203, so that the integration density of the photonic chip is improved, the photonic chip can be coupled with the optical fiber array by using the grating in a vertical packaging mode, the on-line detection is convenient, and the manufacturing flow of the optical module is shortened. Because the photon chip and the electric chip are vertically packaged, the bonding pads for interconnecting the photon chip and the electric chip can be placed at the same height so as to shorten the length of the bonding wire, obtain better high-frequency performance, have potential economic and application values, and are expected to be widely applied in the field of integrated optics.
Those skilled in the art will appreciate that the features recited in the various embodiments of the invention can be combined in a variety of combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the present invention. In particular, the features recited in the various embodiments of the invention can be combined and/or combined in various ways without departing from the spirit and teachings of the invention. All such combinations and/or combinations fall within the scope of the invention.
While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended embodiments and equivalents thereof. Thus, the scope of the invention should not be limited to the embodiments described above, but should be determined not only by the appended embodiments, but also by equivalents of the appended embodiments.
Claims (9)
1. A high integration photonic chip structure, comprising:
the first photon chip comprises a top functional layer (201), an upper silicon dioxide insulating layer (202) and a silicon substrate (203);
the second photon chip comprises a bottom functional layer (205), a lower silicon dioxide insulating layer (204) and a silicon substrate (203);
wherein the first and second photonic chips are flip-chip bonded together, sharing the silicon substrate (203);
the top functional layer (201) comprises a laser, an electro-optical modulator, a first wavelength division multiplexer, a first waveguide and a first coupling structure;
when the laser emits a first optical signal, the first optical signal carries information to be transmitted after being modulated by the electro-optical modulator, the first optical signal is transmitted to the first coupling structure through the first wavelength division multiplexer and the first waveguide, and is output to a first optical fiber array (6) arranged outside through the first coupling structure;
the bottom functional layer (205) comprises a second coupling structure, a second waveguide, a second wavelength division multiplexer and a photoelectric detector;
when a second optical fiber array (7) arranged outside transmits a second optical signal, the second optical signal is coupled to the second waveguide through the second coupling structure and is transmitted to the photoelectric detector through the second wavelength division multiplexer to be subjected to photoelectric conversion, so that information carried by the second optical signal is obtained.
2. The high integration photonic chip structure of claim 1, wherein the first coupling structure and the second coupling structure comprise grating coupling structures.
3. The high integration photonic chip structure of claim 1, further comprising:
the driving chip (1) is connected with the electro-optical modulator and used for driving the electro-optical modulator to work;
and the transimpedance amplifier chip (3) is connected with the photoelectric detector and used for driving the photoelectric detector to work.
4. A high integration photonic chip structure according to claim 3, characterized in that the electro-optical modulator is matched to the height of the metal pads of the driver chip (1), and the photo detector is matched to the height of the transimpedance amplifier chip (3) such that the bonding wires (5) connecting the metal pads are minimized.
5. The high-integration photonic chip structure according to claim 3, wherein the driving chip (1), the transimpedance amplifier chip (3), the first photonic chip and the second photonic chip are arranged on the same PCB (4), wherein the first photonic chip and the second photonic chip are vertically packaged in a positioning groove on the PCB (4), the driving chip (1) is arranged on one side of the first photonic chip facing, and the transimpedance amplifier chip (3) is arranged on one side of the second photonic chip facing.
6. The high integration photonic chip structure according to claim 1, wherein the top functional layer (201) and the bottom functional layer (205) are both covered with a silicon dioxide coating.
7. The high-integration photonic chip structure according to claim 1, wherein the top functional layer (201) material is a silicon or lithium niobate thin film; the bottom functional layer (205) is made of silicon.
8. The high integration photonic chip structure of claim 7, wherein the electro-optic modulator is a silicon-based mach-zehnder modulator or a silicon-based micro-ring modulator and the photodetector is a silicon-based germanium-silicon detector.
9. The high integration photonic chip structure of claim 7, wherein the electro-optic modulator is a thin film lithium niobate based mach zehnder modulator or a thin film lithium niobate based micro-ring modulator and the photodetector is a silicon based germanium silicon detector.
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| US6294415B1 (en) * | 2000-04-26 | 2001-09-25 | United Microelectronics Corp. | Method of fabricating a MOS transistor |
| CN102086024A (en) * | 2010-12-31 | 2011-06-08 | 上海集成电路研发中心有限公司 | Method for preparing silicon nanowire |
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