CN111082305A - Semiconductor laser packaged silicon substrate chip and preparation method thereof - Google Patents
Semiconductor laser packaged silicon substrate chip and preparation method thereof Download PDFInfo
- Publication number
- CN111082305A CN111082305A CN201811217996.6A CN201811217996A CN111082305A CN 111082305 A CN111082305 A CN 111082305A CN 201811217996 A CN201811217996 A CN 201811217996A CN 111082305 A CN111082305 A CN 111082305A
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- Prior art keywords
- silicon substrate
- crystalline silicon
- semiconductor laser
- silicon
- dioxide layer
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- 239000000758 substrate Substances 0.000 title claims abstract description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 26
- 239000010703 silicon Substances 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000002360 preparation method Methods 0.000 title abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 27
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 22
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000004806 packaging method and process Methods 0.000 claims abstract description 5
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000005234 chemical deposition Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000002791 soaking Methods 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 abstract description 15
- 238000002834 transmittance Methods 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000000576 coating method Methods 0.000 abstract description 4
- 230000035800 maturation Effects 0.000 abstract description 3
- 238000004364 calculation method Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012788 optical film Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
- H01S5/021—Silicon based substrates
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0225—Out-coupling of light
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/024—Arrangements for thermal management
- H01S5/02469—Passive cooling, e.g. where heat is removed by the housing as a whole or by a heat pipe without any active cooling element like a TEC
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- Semiconductor Lasers (AREA)
Abstract
The invention discloses a semiconductor laser packaged silicon substrate chip and a preparation method thereof. The semiconductor laser packaging silicon substrate chip comprises a crystalline silicon substrate, and two side surfaces of the crystalline silicon substrate are respectively covered with a silicon dioxide layer; and a silicon nitride layer covers one side surface of the silicon dioxide layer, which is back to the crystalline silicon substrate. The invention can ensure the optical transmittance in 100G and 400G silicon light schemes and avoid optical coating film unmatched with the semiconductor wire maturation process. The process difficulty is reduced, and the production period is shortened.
Description
Technical Field
The invention belongs to the technical field of optical fiber communication equipment, and particularly relates to a semiconductor laser packaged silicon substrate chip and a preparation method thereof.
Background
In the optical fiber communication technology, a semiconductor laser is mainly used as a signal source. At present, the key factor for restricting the characteristics and cost of the signal source mainly lies in the packaging technology. The challenge is to maximize the coupling of the laser light into the fiber, on the one hand, and to provide the laser with a high frequency modulation signal, on the other hand. When a high-frequency modulation signal above 10GHz is provided for a laser, the high-frequency modulation signal is required to pass through a high-frequency transmission coplanar waveguide prepared on a silicon substrate medium. In the 100G and 400G silicon optical schemes, it is required that the light emitted from the laser diode can pass through the silicon substrate. That is, it is necessary to ensure that the silicon substrate chip has a certain light transmittance. In the prior art, a processing method is adopted to generate an optical antireflection film on the surface of a silicon substrate, and the optical antireflection film is generally made of tantalum pentoxide or titanium oxide. The technical scheme has the problems that the silicon substrate chip is required to be coated on an optical processing line, and the standards of a semiconductor production line and the optical processing production line are inconsistent, so that the production period is long, and the production control is difficult. The generated optical film needs to be tested by corrosion of potassium hydroxide in the subsequent process, and the corrosion resistance of the tantalum pentoxide or the titanium oxide is poor, so that the process difficulty is high. Therefore, how to develop a new type of silicon substrate chip for semiconductor laser package to overcome the above problems is the direction of research needed by those skilled in the art.
Disclosure of Invention
The invention provides a silicon substrate chip for packaging a semiconductor laser, which can ensure optical transmittance in 100G and 400G silicon light schemes and avoid optical coating unmatched with a semiconductor wire maturation process. The process difficulty is reduced, and the production period is shortened.
The specific technical scheme adopted is as follows:
a semiconductor laser packaged silicon substrate chip comprises a crystalline silicon substrate, wherein two side surfaces of the crystalline silicon substrate are respectively covered with a silicon dioxide layer; and a silicon nitride layer covers one side surface of the silicon dioxide layer, which is back to the crystalline silicon substrate.
Preferably, in the semiconductor laser package silicon substrate chip: the thickness of the silicon dioxide layer is 100 angstroms; the thickness of the silicon nitride layer (3) is matched with the wavelength and the angle of incident light, so that the optical effect of the antireflection film is achieved.
By adopting the technical scheme: the silicon dioxide plays a role in stress buffering, the thickness of the silicon nitride layer is calculated and optimized to be the maximum transmittance thickness of incident light, the optical transmittance is ensured by the composite laminated structure of the silicon dioxide layer and the silicon nitride layer, and the optical coating which is not matched with the semiconductor wire maturation process is avoided. The process difficulty is reduced, and the production period is shortened.
The invention also discloses a preparation method of the semiconductor laser packaging silicon substrate chip, which is used for preparing the semiconductor laser packaging silicon substrate.
The technical scheme is as follows:
a method for preparing a silicon substrate chip packaged by a semiconductor laser comprises the following steps:
s1: selecting a crystalline silicon substrate, and polishing the two sides of the crystalline silicon substrate;
s2: putting the crystalline silicon substrate into a tube furnace, and simultaneously generating a silicon dioxide layer on the two side surfaces of the crystalline silicon substrate in a high-temperature oxidation mode;
s3: generating a silicon nitride layer on the surface of one side, back to the crystalline silicon substrate, of the silicon dioxide layer in a tubular furnace in a low-pressure chemical deposition mode;
s4: etching a region needing to be etched into a V-shaped groove on the surface of the silicon nitride layer by a photoetching mask method;
s5: forming a gold thin film circuit on the surface of the silicon nitride layer by using a stripping process;
s6: and soaking the product obtained in the step S5 in potassium hydroxide to etch a V-shaped groove with the required depth.
Compared with the prior art, the invention can reduce the processing time, reduce the equipment cost, improve the etching precision, has good thermal conductivity and is beneficial to the heat dissipation of the laser chip.
Drawings
The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIG. 1 is a schematic structural view of example 1 of the present invention;
FIG. 2 is a graph of a calculation of optical transmittance for the product of example 1 according to the thin film interference theory;
FIG. 3 is a graph showing the measured transmittance at 1.2 to 1.4 μm for the product of example 1.
The correspondence between each reference numeral and the part name is as follows:
1. a silicon substrate; 2. a silicon dioxide layer; 3. a silicon nitride layer.
Detailed Description
In order to more clearly illustrate the technical solution of the present invention, the following will be further described with reference to various embodiments.
FIG. 1 shows example 1 of the present invention:
a semiconductor laser packaged silicon substrate chip comprises a crystalline silicon substrate 1, wherein two side surfaces of the crystalline silicon substrate 1 are respectively covered with a silicon dioxide layer 2; and a silicon nitride layer 3 is covered on one side surface of the silicon dioxide layer 2, which faces away from the crystalline silicon substrate 1.
The preparation process comprises the following steps:
s1: selecting a crystalline silicon substrate 1, and carrying out double-sided polishing on the crystalline silicon substrate 1;
s2: putting the crystalline silicon substrate 1 into a tube furnace, and simultaneously generating a silicon dioxide layer 2 on the two side surfaces of the crystalline silicon substrate 1 in a high-temperature oxidation mode;
s2: generating a silicon nitride layer 3 on the surface of the silicon dioxide layer 2 on the side opposite to the crystalline silicon substrate 1 in a tubular furnace in a low-pressure chemical deposition mode;
s3: etching a region needing to be etched into a V-shaped groove on the surface of the silicon nitride layer 3 by a photoetching mask method;
s4: forming a gold thin film circuit on the surface of the silicon nitride layer 3 by a stripping process;
s5: and soaking the product obtained in the step S4 in potassium hydroxide to etch a V-shaped groove with the required depth.
And when a subsequent process is carried out after the V-shaped groove is corroded, if a plasma etching process exists, protecting the silicon nitride in the required light-transmitting area by using photoresist.
For the product, the incident angle is taken for vertical incidence, and the wavelength range is 1.26-1.34 microns. The refractive index of silicon dioxide is 1.44, the refractive index of silicon nitride is 1.98, and the calculation result is shown in fig. 2 according to the thin film interference theory. The transmittance at a center wavelength of 1.31 microns is greater than 99% at 100 angstroms of silicon dioxide, 1550 angstroms of silicon nitride and 4850 angstroms.
FIG. 3 is a calculated curve of transmittance of 1.2-1.4 μm and an actually measured curve after actual coating. The actual measurement is more than 98% in the range of 1.26-1.34 micrometers, and the calculation is consistent with the theoretical calculation. From an economic point of view, 1550 angstrom was selected as an actual plating condition.
By the above example, it can be demonstrated that the film layer simultaneously acts as an optical antireflection and a chemical etching mask. If the wavelength or the incident angle is changed, the required optical anti-reflection effect can be achieved only by readjusting the thicknesses of the silicon dioxide and the silicon nitride according to calculation.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. The protection scope of the present invention is subject to the protection scope of the claims.
Claims (3)
1. A semiconductor laser package silicon substrate chip is characterized in that: the silicon-based solar cell comprises a crystalline silicon substrate (1), wherein two side surfaces of the crystalline silicon substrate (1) are respectively covered with a silicon dioxide layer (2); and a silicon nitride layer (3) covers one side surface of the silicon dioxide layer (2) back to the crystalline silicon substrate (1).
2. A semiconductor laser package silicon substrate chip as claimed in claim 1 wherein: the thickness of the silicon dioxide layer (2) is 100 angstroms.
3. A method for preparing a silicon substrate chip for packaging a semiconductor laser is characterized by comprising the following steps:
s1: selecting a crystalline silicon substrate (1), and carrying out double-sided polishing on the crystalline silicon substrate (1);
s2: putting a crystalline silicon substrate (1) into a tube furnace, and simultaneously generating a silicon dioxide layer (2) on the two side surfaces of the crystalline silicon substrate (1) in a high-temperature oxidation mode;
s3: generating a silicon nitride layer (3) on the surface of one side, which is opposite to the crystalline silicon substrate (1), of the silicon dioxide layer (2) in a tubular furnace in a low-pressure chemical deposition mode;
s4: etching a region needing to be corroded into a V-shaped groove on the surface of the silicon nitride layer (3) by a photoetching mask method;
s5: forming a gold thin film circuit on the surface of the silicon nitride layer (3) by a stripping process;
s6: and soaking the product obtained in the step S5 in potassium hydroxide to etch a V-shaped groove with the required depth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811217996.6A CN111082305A (en) | 2018-10-18 | 2018-10-18 | Semiconductor laser packaged silicon substrate chip and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811217996.6A CN111082305A (en) | 2018-10-18 | 2018-10-18 | Semiconductor laser packaged silicon substrate chip and preparation method thereof |
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| Publication Number | Publication Date |
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| CN111082305A true CN111082305A (en) | 2020-04-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811217996.6A Pending CN111082305A (en) | 2018-10-18 | 2018-10-18 | Semiconductor laser packaged silicon substrate chip and preparation method thereof |
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| Country | Link |
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| CN (1) | CN111082305A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117170016A (en) * | 2023-11-03 | 2023-12-05 | 中国科学院半导体研究所 | High-integration photon chip structure |
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|---|---|---|---|---|
| JP2005136200A (en) * | 2003-10-30 | 2005-05-26 | Univ Nagoya | Nitride semiconductor crystalline layer, manufacturing method therefor, and substrate for manufacturing the same |
| CN102086024A (en) * | 2010-12-31 | 2011-06-08 | 上海集成电路研发中心有限公司 | Method for preparing silicon nanowire |
| CN207442181U (en) * | 2017-10-11 | 2018-06-01 | 上海矽安光电科技有限公司 | A kind of silicon of high power semi-conductor HF laser encapsulation is heat sink |
| CN207490301U (en) * | 2017-10-26 | 2018-06-12 | 上海矽安光电科技有限公司 | A kind of semiconductor laser packaging passive alignment coupling and high-frequency package silicon substrate |
| CN208874053U (en) * | 2018-10-18 | 2019-05-17 | 上海矽安光电科技有限公司 | Semiconductor laser encapsulates silicon substrate board chip |
-
2018
- 2018-10-18 CN CN201811217996.6A patent/CN111082305A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005136200A (en) * | 2003-10-30 | 2005-05-26 | Univ Nagoya | Nitride semiconductor crystalline layer, manufacturing method therefor, and substrate for manufacturing the same |
| CN102086024A (en) * | 2010-12-31 | 2011-06-08 | 上海集成电路研发中心有限公司 | Method for preparing silicon nanowire |
| CN207442181U (en) * | 2017-10-11 | 2018-06-01 | 上海矽安光电科技有限公司 | A kind of silicon of high power semi-conductor HF laser encapsulation is heat sink |
| CN207490301U (en) * | 2017-10-26 | 2018-06-12 | 上海矽安光电科技有限公司 | A kind of semiconductor laser packaging passive alignment coupling and high-frequency package silicon substrate |
| CN208874053U (en) * | 2018-10-18 | 2019-05-17 | 上海矽安光电科技有限公司 | Semiconductor laser encapsulates silicon substrate board chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117170016A (en) * | 2023-11-03 | 2023-12-05 | 中国科学院半导体研究所 | High-integration photon chip structure |
| CN117170016B (en) * | 2023-11-03 | 2024-01-23 | 中国科学院半导体研究所 | High-integration photon chip structure |
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