CN117156668A - Novel bonding pad structure and realization method for reducing heat dissipation bonding pad welding cavity - Google Patents

Novel bonding pad structure and realization method for reducing heat dissipation bonding pad welding cavity Download PDF

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Publication number
CN117156668A
CN117156668A CN202311411144.1A CN202311411144A CN117156668A CN 117156668 A CN117156668 A CN 117156668A CN 202311411144 A CN202311411144 A CN 202311411144A CN 117156668 A CN117156668 A CN 117156668A
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China
Prior art keywords
circular
chip
solder
pad
pcb
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CN202311411144.1A
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CN117156668B (en
Inventor
石玉超
张文忠
何翔
宫玉超
王江坤
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Tianjin Photoelectric Group Co ltd
Tianjin Huigao Magnetics Co ltd
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Tianjin Photoelectric Group Co ltd
Tianjin Huigao Magnetics Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Novel bonding pad structure and realization method for reducing heat dissipation bonding pad welding cavity, and production preparation: cleaning the PCB and pre-baking the PCB and the chip according to the requirement; printing circular solder on the circular bonding pad of the PCB through a steel mesh by using a solder printer; mounting the chip on the circular brazing filler metal by using an automatic chip mounter; the PCB on which the chip is mounted enters a reflow soldering process for soldering, in the reflow soldering process, the round solder is melted and then wets gradually from the center of the chip to gaps between the peripheral inclined planes and the round bonding pads of the PCB, so that the round solder is filled in the bottom of the chip, and meanwhile, volatile gas generated in the reflow soldering process is automatically discharged from the large gap end, so that the purpose of reducing welding holes is achieved; and detecting the void ratio of the welded PCBA by an X-RAY device. The invention can reduce the welding cavity of the chip heat dissipation pad to below 15 percent, and has good welding effect on the coexistence of BGA package and large-quality chip with heat dissipation pad.

Description

Novel bonding pad structure and realization method for reducing heat dissipation bonding pad welding cavity
Technical Field
The invention relates to the technical field of chip packaging, in particular to a novel bonding pad structure and an implementation method for reducing welding cavities of a heat dissipation bonding pad.
Background
If the heat dissipation pad of the chip (such as a mos tube) has a large area void after soldering, it may cause SOA failure. The SOA failure refers to that the generated power consumption cannot be timely dissipated under the condition that the chip bears voltage and current at the same time, and accumulated heat causes the junction temperature of the chip to exceed the standard, so that the chip is thermally damaged.
The conventional design of the chip heat dissipation pad is a cube, as shown in fig. 13, the area ratio of the PCB pad to the chip heat dissipation pad is 1:1, and because the PCB pad and the chip heat dissipation pad are both planar, the design often causes voids due to the fact that volatile gas generated in the reflow soldering process cannot smoothly escape. To solve such problems, the following 2 methods are generally adopted:
1) The steel mesh openings corresponding to the heat dissipation pads are generally divided into a plurality of square shapes (round shapes or other shapes), as shown in fig. 14, the printed solder is also distributed in a matrix of a plurality of small cubes (or other shapes), as shown in fig. 12, so as to provide escape channels for volatile gases generated in the reflow soldering process, but the channels disappear rapidly when the melting point of the solder is reached, but the volatile gases are continuously generated, the general void ratio is more than 30%, the serious void ratio is more than 50%, the IPC-610 standard requirement is not more than 30%, and the QJ-165 standard requirement is not more than 25%.
2) Through holes (without holes or solder resist) are arranged on the heat dissipation pads for exhausting, but solder flows into the through holes in the reflow soldering process to cause insufficient tin quantity between the heat dissipation pads of the chip and the PCB pads to generate holes, and finally holes with different sizes are generated around each through hole, and the cumulative hole rate is also more than 30%.
It should be noted that the reflow temperature profile is particularly well controlled by the way the via vent is provided on the PCB pads, otherwise solder will flow across the PCB to form solder balls, affecting print and product quality.
In actual production, no matter which scheme or combination of the two schemes is adopted, the void ratio can not reach the standard requirement of less than 30%.
Disclosure of Invention
In view of the fact that the prior art is not more than 30% of the IPC-610 standard to void area and not more than 25% of QJ-165 standard to void area are difficult to achieve through improving solder printing to provide escape channels or through increasing through holes on a PCB bonding pad to exhaust, the novel bonding pad structure and the realization method for reducing the welding void of the heat dissipation bonding pad are provided.
The invention adopts the technical proposal for realizing the aim that: the utility model provides a novel pad structure includes chip, PCB board and circular solder, be equipped with the circular pad of PCB board on the PCB board, be equipped with circular solder on the circular pad of PCB board, the chip sets up on circular solder, fixes the chip on the circular pad of PCB board through circular protruding heat dissipation pad through the reflow soldering.
The realization method for reducing the welding cavity of the heat dissipation bonding pad of the novel bonding pad structure comprises the following steps:
step one, preparation of production: cleaning a PCB, pre-drying according to requirements, and pre-drying a chip according to requirements;
printing circular brazing filler metal on a circular bonding pad of a PCB of the PCB through a steel mesh by using a brazing filler metal printer;
thirdly, mounting the chip on the round solder by using an automatic chip mounter;
step four, the PCB on which the chip is mounted enters a reflow soldering process for soldering, in the reflow soldering process, the round solder is melted and then wets gradually from the center of the chip to gaps between the peripheral inclined planes and the round bonding pads of the PCB, so that the round solder is filled in the bottom of the chip, and meanwhile, volatile gas generated in the reflow soldering process is automatically discharged from the large gap ends, so that the purpose of reducing welding holes is achieved;
fifthly, detecting the void ratio of the welded chip through X-RAY equipment.
The invention has the technical effects that: in view of the fact that in the prior art, whether the escape channel is provided by improving solder printing or exhaust is carried out by adding through holes on a PCB bonding pad, the standard requirement that the cavity area is not more than 30% (special products such as aerospace require cavities not more than 15%), particularly, most of existing products are BGA packaging and large-quality chips with heat dissipation bonding pads coexist, and the reflow soldering temperature curve is difficult to achieve. The technical scheme can reduce the welding cavity of the chip radiating pad to below 15%, and has good welding effect on the coexistence of BGA package and a large-quality chip with the radiating pad.
Drawings
FIG. 1 is a schematic diagram of the connection of a chip, PCB and solder structure of the present invention;
fig. 2 is a schematic structural view of a solder disposed on a PCB board according to the present invention;
FIG. 3 is a schematic diagram of a chip according to the present invention;
FIG. 4 is a bottom view of the structure of FIG. 3;
fig. 5 is a schematic diagram of a structure of a chip soldered on a PCB board according to the present invention;
FIG. 6 is a schematic view of the tendency of a solder joint movement;
FIG. 7 is a schematic diagram of the automatic exhaust of the present invention;
FIG. 8 is an exemplary graph of an RP temperature curve according to the present invention;
FIG. 9 is an exemplary graph of an RSP temperature curve according to the present invention;
FIG. 10 is a schematic view of the structure of the steel mesh of the present invention;
FIG. 11 is a flow chart of a method of implementing the present invention;
fig. 12 is a schematic diagram of a prior art PCB, PCB pads and solder;
fig. 13 is a schematic view of a prior art die soldered on a PCB;
fig. 14 is a schematic structural view of a prior art steel mesh.
Detailed Description
As shown in FIG. 1, the novel bonding pad structure comprises a chip 1, a PCB 2 and a solder 3, wherein the PCB 2 is corroded to form a circular bonding pad 2-1, the circular solder 3 is printed on the circular bonding pad 2-1 of the PCB, the circular convex heat dissipation bonding pad 1-2 of the chip 1 is attached to the circular solder 3, and after the circular solder 3 is melted by reflow soldering, the circular convex heat dissipation bonding pad 1-2 of the chip 1 is fixed on the circular bonding pad 2-1 of the PCB.
The chips 1 mentioned in the present technical solution are all specifically chips with heat dissipation pads.
As shown in fig. 2, the circular solder 3 is composed of four fan-shaped protruding solder 3-1 and a plurality of circular protruding solder 3-2, four fan-shaped protruding solder 3-1 are arranged at intervals along the edge of the circular bonding pad 2-1 surface of the PCB board, a circular protruding solder 3-2 is arranged at the center of the four fan-shaped protruding solder 3-1, and a plurality of circular protruding solder 3-2 are arranged at intervals along the edge of the circular protruding solder 3-2 at the center.
As shown in fig. 3 and 4, the chip 1 is composed of a chip body 1-1 and a circular protruding heat dissipation pad 1-2, the circular protruding heat dissipation pad 1-2 is arranged at the center of the chip body 1-1, the circular protruding heat dissipation pad 1-2 is composed of a lower bottom surface 1-21 and an upper bottom surface 1-22 which are integrally structured, and a circle of inclined surface 1-23 is arranged between the lower bottom surface 1-21 and the upper bottom surface 1-22.
Radius R of lower bottom surface 1-21 of round convex heat radiation bonding pad 1-2 1 Is the radius r of the upper bottom surface 1-22 1 1/3 to 1/4 of the height of the round bump heat dissipation pad 1-2 is 0.1 plus or minus 0.02mm.
The height h of the round convex heat dissipation pad 1-2 can be properly adjusted according to the size of the round pad 2-1 of the PCB and the thickness of the steel mesh 4.
2-1 radius R of circular bonding pad of PCB 2 Is larger than the upper bottom surface 1-Radius r of 22 1
The solder 3 is a solder paste or solder paste.
The structural design purposes and the exhaust principle of the circular convex heat dissipation bonding pad 1-2 of the chip 1 and the circular bonding pad 2-1 of the PCB are as follows:
1) Since the capillary force is inversely proportional to the size of the gap, the smaller the gap, the stronger the capillary action. In reflow soldering, when the solder fills the non-parallel gap with one large end and one small end, the non-parallel gap is formed between the peripheral inclined surface 1-23 of the chip 1 and the circular bonding pad 2-1 of the PCB board), the solder has a tendency to preferentially fill the small gap.
The results of the study on the X-ray of the solder caulking process show that when the solder is caulking in the non-parallel gap, the solder is always preferentially filled in the gap of the small end, and then gradually advanced toward the large end, regardless of whether the solder is added from the gap of the large end, the small end or the gap of the side end, as shown in fig. 6, a is the solder addition position, and B, C, D is the solder movement tendency.
As can be seen in fig. 6 a: adding solder from the small ends of the non-parallel gaps, wherein the solder can fill the small ends preferentially;
as can be seen in fig. 6 b: adding solder from the large end of the non-parallel gap, wherein the solder still fills the small end preferentially;
as can be seen in fig. 6 c: the filler metal is added from the side ends of the non-parallel gap, and the filler metal still preferentially fills the small ends.
Volatile gas generated in the reflow soldering process is automatically discharged from the large gap end under the condition of unbalanced additional pressure, as shown in fig. 7, the density of the solder is high, the density of the gas generated in the reflow soldering process is low, and the solder can be preferentially filled into the small end due to capillary action, so that the gas generated in the reflow soldering process can be easily extruded out by the solder.
2) Compatible RP curve and RSP curve;
when the IPC-7530A standard cone suggests a device with large heat quantity difference, the RSP curve is better, because the time of the heat preservation area can be prolonged to reduce the cavity, it is not easy to understand that the temperature of the constant temperature area does not reach the melting point of the brazing filler metal yet, the escape channel does not disappear, and the generated volatile gas can escape through the escape channel. However, when BGA (Ball Grid Array) devices are provided on the board, it is generally recommended to use an RP curve rather than an RSP temperature curve, since the RSP temperature curve may produce HoP (pillow effect).
FIG. 8 is an exemplary graph of RP temperature and FIG. 9 is an exemplary graph of RSP temperature; in the figure, A is temperature and B is time. The RSP temperature curve can clearly see the preheating zone, the heat preservation (constant temperature) zone, the re-flowing zone and the cooling zone, but each temperature zone of the RP temperature curve is not obvious, and the temperature rising slope is not obviously changed.
The main difference between the two temperature curves is that there is no constant temperature area in the RP temperature curve, and extending the constant temperature area can reduce welding voids.
According to the technical scheme, exhaust is mainly achieved through capillary action, rather than an escape channel designed through a process, and the constant temperature area time is prolonged, so that when a BGA device and a chip device with large heat quantity difference exist in a Product (PCBA) at the same time, an RP temperature curve is adopted, and a good welding effect can be achieved.
3) Circular bonding pad R of PCB 2 Should be slightly larger than the circular bump heat dissipation pad r of the chip 1 (conventional design is 1:1) to ensure that sufficient tin can enter the bottom of the chip by capillary action, thereby exhausting volatile gases generated in the welding process. R is R 2 The value of (2) can be calculated by the following formula.
(1) The volume formula of the round table: v (V) Round bench =1/3πh(r 1 ²+r 1 ²+r 1 R 1 );
(2) The cylinder volume formula: v (V) Cylinder column =hπr 1 2
(3) Filling volume of brazing filler metal: v=v Cylinder column -V Round bench
V=(HπR 2 2 -Hπr 1 2 )*50%;
Remarks: 1) The volume ratio of the metal content in the solder is about 50%; 2) The round convex heat dissipation bonding pad 1-2 adopts a round platform design; 3) The radii of the upper bottom surface 1-22 and the lower bottom surface 1-21 of the round table are r respectively 1 ,R 1 The height of the round table is h, and the radiuses of the circular bonding pads of the PCB are respectivelyIs R 2 The solder height of the printed circles is H, pi means the circumference ratio. Dividing R by 2 All are known numbers, so R 2 Can be directly calculated; compared with the traditional scheme, the circular bonding pad of the PCB is larger (the traditional scheme is 1:1), so that the heat dissipation of the chip is facilitated; 4) Steel mesh design, as shown in fig. 10: the steel mesh 4 is composed of a steel plate 4-1, four sector holes 4-2 and a plurality of circular holes 4-3, the four sector holes 4-2 are arranged on the surface of the steel plate 4-1 at intervals, the center of the four sector holes 4-2 is provided with one circular hole 4-3, the plurality of circular holes 4-3 are arranged along the edge of the circular hole at the center at intervals, and escape passages 4-4 are arranged among the four sector holes 4-2 and among the plurality of circular holes 4-3.
Because the round convex heat dissipation pad 1-2 of the chip 1 adopts a round platform design, only the round pad 2-1 of the PCB and the lower bottom surface 1-21 of the round convex heat dissipation pad 1-2 are contacted, when the steel mesh 4 is perforated, only the contact part of the round pad 2-1 of the PCB and the lower bottom surface 1-21 of the round convex heat dissipation pad 1-2 is considered to provide an escape channel 4-4, because the contact part of the round pad 2-1 of the PCB and the lower bottom surface 1-21 of the round convex heat dissipation pad 1-2 can generate volatile gas in the reflow soldering process, the contact area of the round pad 2-1 of the PCB and the lower bottom surface 1-21 of the round convex heat dissipation pad 1-2 is smaller, the generated volatile gas is less, the escape path is shorter, and the chip has a gain effect on reducing cavities; the other parts do not need special consideration, but do not generate volatile gas when welding other parts, but have gaps between the inclined planes 1-23 of the round convex heat dissipation pads 1-2 and the round pads 2-1 of the PCB before the solder is melted, so that the solder can be used as escape channels, and capillary action is generated after the solder is melted to exhaust through the gaps (the exhaust principle is described above).
In embodiment 1, as shown in fig. 5 and 11, a method for realizing a novel pad structure for reducing heat dissipation pad welding voids comprises the following steps:
step one, preparation of production: the PCB 2 is cleaned, the chip 1 is pre-baked according to the requirement, the purpose of pre-baking is to overflow moisture in the PCB 2 and the chip 1, the generation of holes is reduced, the 'popcorn' effect can be relieved, and the programs of all the SMT devices are programmed.
And secondly, printing circular solder 3 on the PCB 2 through a steel mesh 4 by using a solder printer, wherein the printed solder 3 meets the requirements of IPC-7527 on solder printing, and the shape of the printed circular solder is the same as that of a template hole (area and height).
And thirdly, mounting the chip 1 on the printed circular solder 3 of the PCB 2 by using an automatic chip mounter, wherein the mounting of the chip (element) meets GJB-3243 'surface mounting requirement of electronic components', and the mounted chip (element) meets the standard cone requirement that all welding ends are positioned on a welding pad and centered or the deviation is not more than 25% of the width of the welding ends.
Step four, the PCB 2 on which the chip 1 is mounted enters a reflow soldering process for soldering, the chip 1 is mounted on the circular solder 3 of the PCB 2, a non-parallel gap is formed between the inclined plane 1-23 of the circular convex radiating pad 1-2 of the chip 1 and the circular pad 2-1 of the PCB, capillary force is inversely proportional to the size of the gap, and the smaller the gap is, the stronger the capillary action is, so that the circular solder 3 in the reflow soldering process is gradually wetted from the center of the chip 1 to the surrounding gap after being melted, and meanwhile, the circular solder 2-1 of the PCB is larger than the circular convex radiating pad 1-2 of the chip 1, so that the sufficient circular solder 3 enters the bottom of the chip 1 through capillary action; volatile gas generated in the reflow soldering process is automatically discharged from the large gap end under the condition of unbalanced additional pressure, so that the purpose of reducing the soldering cavity is realized.
Fifthly, detecting the void ratio of the welded chip 1 through an X-RAY device, placing the welded chip 1 into the X-RAY device, adjusting parameters (voltage, current, focal length and the like) of the X-RAY device until a welding spot can be clearly seen, and then detecting the void ratio through the X-RAY device, wherein the void ratio is measured according to the specific void ratio detection result shown in the following table 1:
TABLE 1 cavitation detection results
100 plates were tested, and the void fraction was 15% or less.
With respect to the solder 3 of the circular shape in step 2 of example 1, it is necessary to calculate the area of the circular land 2-1 of the PCB board while designing the thickness of the steel mesh 4 (the selection of the thickness of the steel mesh can be referred to IPC-7525).
The area of the circular bonding pad 2-1 of the PCB board can be calculated preliminarily according to the following formula:
the volume formula of the table: v (V) Round bench =1/3πh(r 1 ²+r 1 ²+r 1 R 1 );
Column volume formula: v (V) Cylinder column =hπr 1 2
(3) Filling volume of brazing filler metal: v=v Cylinder column -V Round bench
V=(HπR 2 2 -Hπr 1 2 )*50%;
Remarks: the volume ratio of the metal content in the solder is about 50%;
the radii of the upper bottom surface 1-22 and the lower bottom surface 1-21 of the round table are r respectively 1 ,R 1 The height of the round table is h, and the radiuses of the round pads 2-1 of the PCB are R respectively 2 The height of the solder is H, and pi refers to the circumference ratio.
The area ratio of the steel mesh 4 open holes to the PCB circular bonding pad 2-1 is 1:1, after the area of the circular bonding pad 2-1 of the PCB is calculated, the solder quantity is determined by the area of the circular bonding pad 2-1 of the PCB and the thickness of the steel mesh 4, so that the sufficient solder quantity can be ensured to enter the bottom of the chip 1 through capillary action, and then the gas generated in the welding process is discharged.
Step 4 needs to be specifically described as follows: in practical production, there often occurs a situation that a BGA device (IPC-7530A recommends to use an RP curve, otherwise HoP (pillow effect) is easy to generate) and a high-quality chip (IPC-7530A recommends to use an RSP curve to reduce the problem of voids as much as possible) coexist, and the technical scheme can also well solve the problem because the exhaust principle (described in detail above) of the technical scheme is completely different from that of the conventional process.

Claims (8)

1. A novel bonding pad structure, characterized in that: including chip (1), PCB board (2) and solder (3), be equipped with circular pad (2-1) of PCB board on PCB board (2), be equipped with circular solder (3) on circular pad (2-1) of PCB board, chip (1) set up on circular solder (3), fix chip (1) on circular pad (2-1) of PCB board through circular protruding heat dissipation pad (1-2) through the reflow soldering.
2. The novel bonding pad structure according to claim 1, wherein: the chip (1) is composed of a chip body (1-1) and a round protruding radiating pad (1-2), the round protruding radiating pad (1-2) is arranged at the center of the chip body (1-1), the round protruding radiating pad (1-2) is composed of a lower bottom surface (1-21) and an upper bottom surface (1-22) which are of an integral structure, and a circle of inclined surface (1-23) is arranged between the lower bottom surface (1-21) and the upper bottom surface (1-22).
3. A novel bonding pad structure according to claim 2, characterized in that: the radius R of the lower bottom surface (1-21) of the round convex heat dissipation bonding pad (1-2) 1 Is the radius r of the upper bottom surface (1-22) 1 1/3 to 1/4 of the height of the round bump heat dissipation pad (1-2) is 0.1 plus or minus 0.02mm.
4. A novel bonding pad structure according to claim 3, wherein: radius R of circular bonding pad (2-1) of PCB 2 Is larger than the radius r of the upper bottom surface (1-22) of the round convex heat dissipation pad (1-2) 1
5. The novel bonding pad structure according to claim 1, wherein: the circular solder (3) is composed of four fan-shaped protruding solder (3-1) and a plurality of circular protruding solder (3-2), four fan-shaped protruding solder (3-1) are arranged at intervals along the edge of the surface of the circular bonding pad (2-1) of the PCB, a circular protruding solder (3-2) is arranged at the center of the four fan-shaped protruding solder (3-1), and a plurality of circular protruding solder (3-2) are arranged at intervals along the edge of the circular protruding solder (3-2) at the center.
6. A method for reducing heat dissipation pad solder voids using the novel pad structure of claim 1, comprising the steps of:
step one, preparation of production: cleaning a PCB (2) and pre-drying according to requirements, and pre-drying a chip (1) according to requirements;
secondly, printing a circular solder (3) on a circular bonding pad (2-1) of a PCB (2) through a steel mesh (4) by using a solder printer;
thirdly, mounting the chip (1) on the circular brazing filler metal (3) by using an automatic chip mounter;
step four, the PCB (2) of the mounted chip (1) enters a reflow soldering process for soldering, in the reflow soldering process, the round solder (3) is melted and then gradually wets from the center of the chip (1) to a gap between the peripheral inclined planes (1-23) and the round bonding pad (2-1) of the PCB, so that the round solder (3) is filled in the bottom of the chip (1), and meanwhile, volatile gas generated in the reflow soldering process is automatically discharged from a large gap end, thereby realizing the purpose of reducing welding holes;
fifthly, detecting the void ratio of the welded chip (1) through X-RAY equipment.
7. The method for reducing the welding cavity of the heat dissipation pad with the novel pad structure according to claim 6, wherein a non-parallel gap is formed between the inclined surface (1-23) of the circular protruding heat dissipation pad (1-2) of the chip (1) and the circular pad (2-1) of the PCB, and the circular pad (2-1) of the PCB is larger than the circular protruding heat dissipation pad (1-2) of the chip (1).
8. The realization method for reducing the welding cavity of the heat dissipation welding pad with the novel welding pad structure according to claim 6 is characterized in that the steel mesh (4) is composed of a steel plate (4-1), four sector holes (4-2) and a plurality of circular holes (4-3), four sector holes (4-2) are arranged on the surface of the steel plate (4-1) at intervals, one circular hole (4-3) is arranged at the center of each of the four sector holes (4-2), a plurality of circular holes (4-3) are arranged at the edge of each circular hole at the center at intervals, and escape channels (4-4) are arranged among the four sector holes (4-2) and among the plurality of circular holes (4-3).
CN202311411144.1A 2023-10-29 2023-10-29 Chip packaging structure and realization method for reducing heat dissipation pad welding cavity Active CN117156668B (en)

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Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11307683A (en) * 1998-04-23 1999-11-05 Sony Corp Semiconductor device, printed wiring board mounted therewith and manufacture thereof
JP2001015554A (en) * 1999-06-30 2001-01-19 Fujitsu Ten Ltd Component mounting structure for board
EP1256982A1 (en) * 2001-05-11 2002-11-13 Valtronic S.A. Electronic Module and its Assembling Process
JP2004095864A (en) * 2002-08-30 2004-03-25 Casio Comput Co Ltd Electronic part
KR20110009017A (en) * 2010-04-14 2011-01-27 삼성전기주식회사 Lead pin for package substrate
CN104701291A (en) * 2013-12-05 2015-06-10 深圳市共进电子股份有限公司 PCB (printed circuit board) heat-radiation soldering pad used for QFN (quad flat no-lead package) chip, and QFN chip and PCB soldering method
US20160254241A1 (en) * 2015-02-27 2016-09-01 Fujitsu Limited Printed circuit board and soldering method
CN106658938A (en) * 2016-06-24 2017-05-10 奇酷互联网络科技(深圳)有限公司 Printed circuit board and manufacturing method thereof
CN109616452A (en) * 2018-10-26 2019-04-12 武汉光迅科技股份有限公司 A kind of radiating subassembly, corresponding radiator and corresponding circuit board
CN111757611A (en) * 2020-06-05 2020-10-09 深圳市隆利科技股份有限公司 Mounting structure applied to miniLED and manufacturing method thereof
CN114220826A (en) * 2021-12-14 2022-03-22 上海集成电路装备材料产业创新中心有限公司 Chip packaging structure and chip packaging method
CN114654035A (en) * 2022-04-29 2022-06-24 天津光电惠高电子有限公司 Method for reducing LGA device welding cavity by using prefabricated solder

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11307683A (en) * 1998-04-23 1999-11-05 Sony Corp Semiconductor device, printed wiring board mounted therewith and manufacture thereof
JP2001015554A (en) * 1999-06-30 2001-01-19 Fujitsu Ten Ltd Component mounting structure for board
EP1256982A1 (en) * 2001-05-11 2002-11-13 Valtronic S.A. Electronic Module and its Assembling Process
JP2004095864A (en) * 2002-08-30 2004-03-25 Casio Comput Co Ltd Electronic part
KR20110009017A (en) * 2010-04-14 2011-01-27 삼성전기주식회사 Lead pin for package substrate
CN104701291A (en) * 2013-12-05 2015-06-10 深圳市共进电子股份有限公司 PCB (printed circuit board) heat-radiation soldering pad used for QFN (quad flat no-lead package) chip, and QFN chip and PCB soldering method
US20160254241A1 (en) * 2015-02-27 2016-09-01 Fujitsu Limited Printed circuit board and soldering method
CN106658938A (en) * 2016-06-24 2017-05-10 奇酷互联网络科技(深圳)有限公司 Printed circuit board and manufacturing method thereof
CN109616452A (en) * 2018-10-26 2019-04-12 武汉光迅科技股份有限公司 A kind of radiating subassembly, corresponding radiator and corresponding circuit board
CN111757611A (en) * 2020-06-05 2020-10-09 深圳市隆利科技股份有限公司 Mounting structure applied to miniLED and manufacturing method thereof
CN114220826A (en) * 2021-12-14 2022-03-22 上海集成电路装备材料产业创新中心有限公司 Chip packaging structure and chip packaging method
CN114654035A (en) * 2022-04-29 2022-06-24 天津光电惠高电子有限公司 Method for reducing LGA device welding cavity by using prefabricated solder

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