CN117080093A - 一种高密度线路扇出封装结构及其制作方法 - Google Patents
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 85
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 94
- 229910052751 metal Inorganic materials 0.000 claims abstract description 94
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000004033 plastic Substances 0.000 claims abstract description 31
- 238000002161 passivation Methods 0.000 claims abstract description 25
- 239000003292 glue Substances 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- 238000007789 sealing Methods 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- WMGRVUWRBBPOSZ-UHFFFAOYSA-N [Cu].[Ni].[Ag].[Sn] Chemical compound [Cu].[Ni].[Ag].[Sn] WMGRVUWRBBPOSZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 239000005022 packaging material Substances 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000011161 development Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 238000005429 filling process Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- -1 insufficient filling Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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Abstract
本发明公开了一种高密度线路扇出封装结构及其制作方法;该制作方法获得的封装结构包括互联的第一封装单元和第二封装单元;第一封装单元包括芯片、塑封层、第一金属重布线层、第一钝化层以及金属焊盘,第一金属重布线层与芯片电连接,芯片的背面暴露在外;第二封装单元包括第二金属重布线层、第二钝化层以及金属凸块;金属凸块和金属焊盘连接;最外层的第二金属重布线层还连接有信号导出结构。本发明的方法直接采用塑封材料对芯片正面进行包封,降低成本,提高良率,而且分两阶段同时进行布线,可节约时间,降低扇出封装结构的翘曲,也可降低布线过程中的良率损失,同时可实现高密度布线,能够减小封装尺寸,实现更薄的封装结构。
Description
技术领域
本发明涉及半导体芯片封装技术领域,特别涉及一种高密度线路扇出封装结构及其制作方法。
背景技术
随着高性能计算、人工智能、5G通信、数据中心和云计算的快速发展,单颗芯片上面集成的晶体管数目已超百亿级,因此需要一种高端性能封装以应对高性能计算、数据处理等前沿技术的要求。高密度扇出(HDFO)作为一种性价比优于2.5D转接板的高端封装方案备受青睐。
现有的晶圆级超高密度扇出型封装工艺制程,通常是采用以下方式完成封装结构的制备:在玻璃载板上面涂覆一层临时键合材料;在临时键合材料上面作业RDL线路;在最上面一层线路上面制作连接焊盘;将芯片进行倒装上芯,芯片与连接焊盘通过回流焊方式连接在一起实现电信导通;对芯片与RDL之间间隙进行底部胶水填充;对整个芯片进行塑封料塑封;对底部玻璃载片进行解键合;刻蚀掉临时键合残胶,进行植球回流得到外联锡球。这种扇出型封装工艺采用倒装上芯的方式贴片,由于芯片底部焊点间距小,强度小,容易变型;而且,为了提高电子产品的机械性能以及可靠性,在塑封前需要对芯片和线路板之间的空隙进行底部胶水填充补强,底部胶水填充会存在胶水不流动不固化、填充不充分、气孔等缺陷。
现有的扇出型封装工艺中,随着高密度布线的层数增加,应力随之增加造成晶圆大翘曲;目前扇出型封装结构中,4层5μm/5μm的产品已经进入量产阶段,而布线为1μm/1μm的层数最多为6层,处于试验阶段,难以满足更高I/O密度的芯片间连接,晶圆翘曲使得超过6层的布线越来越困难。而多层重布线的制作工艺中,底层布线的拱起还会影响上层光刻胶图案的涂布,曝光以及显影,造成布线缺陷,从而造成良率损失。塑封料与芯片之间热膨胀系数的不匹配,也会造成晶圆的严重翘曲,造成晶圆后制程工艺困难,同时大量的塑封料不利于器件的散热。
发明内容
为解决上述技术问题,本发明的目的在于提供一种高密度线路扇出封装结构及其制作方法。本发明的方法无需芯片底部填充工艺,直接采用塑封材料对芯片正面进行包封,降低成本,提高良率,而且可分两阶段同时进行布线,可节约时间,降低扇出封装结构的翘曲,便于后制程的制备,也可降低布线过程中的良率损失,同时可实现高密度布线,能够减小封装尺寸,实现更薄的封装结构。
为实现上述技术目的,达到上述技术效果,本发明通过以下技术方案实现:
本发明提供了一种高密度线路扇出封装结构的制作方法,包括如下步骤:
步骤一,制作第一封装结构
S11,取一载片,在该载片上贴装芯片,芯片的功能PAD向上;
S12,对芯片进行塑封,形成塑封层,并使芯片的功能PAD露出,对塑封层进行固化;
S13,在塑封层上形成多层第一金属重布线层和第一钝化层,第一金属重布线层与芯片的功能PAD电连接,在最外层的第一金属重布线层上形成金属焊盘;
步骤二,制作第二封装结构
S21,取一载板,在该载板上形成多层第二金属重布线层和第二钝化层;在最上层的第二金属重布线层上形成金属凸块;
步骤三,制作高密度线路扇出封装结构
S31,将步骤一制作的第一封装结构与步骤二制作的第二封装结构进行键合,通过高温回流使得第一封装结构的金属凸块和第二封装结构的金属焊盘电连接;
S32,去除第二封装结构中的载板,使最外层的第二金属重布线层露出,在最外层的第二金属重布线层上形成信号导出结构;
S33,去除第一封装结构的载片,使芯片的背面露出,最后通过切割形成单颗高密度线路扇出封装结构。
进一步的,步骤S11中,先在载片上涂覆一层临时键合胶,然后将芯片贴装在临时键合胶上。
进一步的,步骤一中,还包括步骤S14,具体为:在最外层的第一钝化层上涂覆干膜,并在干膜的对应金属焊盘的位置形成开口;该干膜能够填充第一封装结构和第二封装结构之间的连接界面。
进一步的,步骤S2中,在形成第二金属重布线层和第二钝化层前,先在载板上涂覆一层临时键合胶。
进一步的,第一金属重布线层和第二金属重布线层的线宽以及线间距为0.8-2.0μm。
进一步的,所述金属凸块为金凸块、铜柱凸块或铜镍锡银凸块。
进一步的,所述信号导出结构为锡球。
本发明进一步提供了一种高密度线路扇出封装结构,其包括互联的第一封装单元和第二封装单元;所述第一封装单元包括芯片、塑封于芯片上的塑封层、多层第一金属重布线层、多层第一钝化层以及连接在最下层的第一金属重布线层上的金属焊盘,第一金属重布线层与芯片电连接,所述芯片的背面暴露在外;所述第二封装单元包括多层第二金属重布线层、多层第二钝化层以及连接在最上层的第二金属重布线层上的金属凸块;所述金属凸块和金属焊盘连接;最外层的第二金属重布线层还连接有信号导出结构。
进一步的,第一封装单元和第二封装单元之间还填充有干膜。
进一步的,所述信号导出结构为锡球。
本发明的有益效果是:
1.本发明分两阶段同时进行布线,可以进行多层(大于10层)高密度布线,线宽以及线间距可以做到更细(小于4μm),降低了布线过程中的良率损失,同时通过高密度布线减小封装尺寸,实现更薄的封装结构。
2.本发明封装完成后的芯片顶部露出,未完全包封在塑封料中,有利于器件的散热。
3.相比于一次布线,本发明采用分两阶段同时进行布线的方式,可节约时间,降低扇出封装结构的翘曲,便于后制程的制备。
4.本发明无需芯片底部填充工艺,直接采用塑封材料对芯片正面进行包封,可降低成本,提高良率。
附图说明
图1为本发明制作方法中的步骤一的制作流程图。
图2为本发明制作方法中的步骤二制得的第二封装结构的示意图。
图3为本发明制作方法中的步骤三的制作流程图。
具体实施方式
下面结合附图对本发明的较佳实施例进行详细阐述,以使本发明的优点和特征能更易于被本领域技术人员理解,从而对本发明的保护范围做出更为清楚明确的界定。
如图1至图3所示的一种高密度线路扇出封装结构的制作方法,其包括如下步骤:
步骤一,制作第一封装结构
S11,取一载片1,在该载片1上面涂覆一层临时键合胶,在临时键合胶上贴装芯片2,芯片2的功能PAD向上;
临时键合胶的作用是对芯片2与载片1之间进行键合;完成相关制程后可进行解键合。临时键合胶可选自激光临时解键合膜、热塑性树脂、热固性树脂、光刻胶等树脂体系;其中的载片1可为玻璃、硅片、钢片等材质。
S12,对芯片2进行塑封,形成塑封层,并使芯片2的功能PAD露出,对塑封层3进行固化;塑封材料要求能够经过高温制程不变型。
S13,在塑封层3上形成多层第一金属重布线层4和第一钝化层5,第一金属重布线层4与芯片2的功能PAD电连接,在最外层的第一金属重布线层4上形成金属焊盘6;
具体过程为:首先,在塑封层3上通过涂覆光刻胶、曝光、显影工艺形成第一层的线路图案,通过电镀工艺形成第一层第一金属重布线层4后,去除光刻胶,第一层第一金属重布线层4与芯片2的功能PAD连接;然后在塑封层3上涂覆一层钝化材料,形成第一层第一钝化层5,钝化材料为光刻胶,通过曝光、显影的方式在第一钝化层5的对应第一金属重布线层4的位置开孔;通过溅射工艺在开孔内表面和第一钝化层5表面沉积一层种子层;在种子层上面涂覆光刻胶,通过曝光、显影工艺使光刻胶上显露出线路图形,通过电镀工艺形成金属线路;去除光刻胶以及多余的种子层,形成第二层第一金属重布线层4;按照上述工艺交替形成多层第一金属重布线层4、多层第一钝化层5以及金属焊盘6。
S14,将干膜7涂覆在最外层的第一钝化层5上,通过曝光、显影方式将金属焊盘区域打开,对干膜7进行固化。
步骤二,制作第二封装结构
S21,取一载板8,在该载板8上涂覆一层临时键合胶,在该临时键合胶上形成多层第二金属重布线层9和第二钝化层10;在最上层的第二金属重布线层9上形成金属凸块11;金属凸块可以为金凸块、铜柱凸块、铜镍锡银凸块等。
步骤一和步骤二可同时进行。
步骤三,制作高密度线路扇出封装结构
S31,通过晶圆键合机将步骤一制作的第一封装结构与步骤二制作的第二封装结构进行键合,通过高温回流使得第二封装结构的金属凸块11和第一封装结构的金属焊盘6连接在一起;干膜7能够填覆第一封装结构和第二封装结构之间的连接界面;
S32,通过解键合的方式去除第二封装结构中的载板8,并去除临时键合胶,使最外层的第二金属重布线层9露出,在最外层的第二金属重布线层9上形成信号导出结构12;解键合方式可选择激光解键合、热释放、化学释放、机械释放等。信号导出结构可以为通过植球方式形成的锡球。
S33,通过解键合的方式去除第一封装结构的载片1,并去除临时键合胶,使芯片2的背面露出,最后通过切割形成单颗高密度线路扇出封装结构。
上述制作方法获得的高密度线路扇出封装结构,包括互联的第一封装单元和第二封装单元;所述第一封装单元包括芯片2、塑封于芯片2上的塑封层3、多层第一金属重布线层4、多层第一钝化层5以及连接在最下层的第一金属重布线层4上的金属焊盘6,第一金属重布线层4与芯片2电连接,所述芯片2的背面暴露在外;所述第二封装单元包括多层第二金属重布线层9、多层第二钝化层10以及连接在最上层的第二金属重布线层9上的金属凸块11;所述金属凸块11和金属焊盘6连接;最外层的第二金属重布线层9还连接有信号导出结构12。该信号导出结构12可以为锡球。第一封装单元和第二封装单元之间还填充有干膜7。第一金属重布线层4和第二金属重布线层9的线宽以及线间距为0.8-2.0μm。
本发明的制备方法无需芯片底部填充工艺,直接采用塑封材料对芯片正面进行包封,降低成本,提高良率,而且可分两阶段同时进行布线,可节约时间,降低扇出封装结构的翘曲,便于后制程的制备,也可降低布线过程中的良率损失,同时可实现高密度布线,能够减小封装尺寸,实现更薄的封装结构。
以上所述仅为本发明的实施例,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。
Claims (10)
1.一种高密度线路扇出封装结构的制作方法,其特征在于,包括如下步骤:
步骤一,制作第一封装结构
S11,取一载片,在该载片上贴装芯片,芯片的功能PAD向上;
S12,对芯片进行塑封,形成塑封层,并使芯片的功能PAD露出,对塑封层进行固化;
S13,在塑封层上形成多层第一金属重布线层和第一钝化层,第一金属重布线层与芯片的功能PAD电连接,在最外层的第一金属重布线层上形成金属焊盘;
步骤二,制作第二封装结构
S21,取一载板,在该载板上形成多层第二金属重布线层和第二钝化层;,在最上层的第二金属重布线层上形成金属凸块;
步骤三,制作高密度线路扇出封装结构
S31,将步骤一制作的第一封装结构与步骤二制作的第二封装结构进行键合,通过高温回流使得第一封装结构的金属凸块和第二封装结构的金属焊盘电连接;
S32,去除第二封装结构中的载板,使最外层的第二金属重布线层露出,在最外层的第二金属重布线层上形成信号导出结构;
S33,去除第一封装结构的载片,使芯片的背面露出,最后通过切割形成单颗高密度线路扇出封装结构。
2.根据权利要求1所述的一种高密度线路扇出封装结构的制作方法,其特征在于,步骤S11中,先在载片上涂覆一层临时键合胶,然后将芯片贴装在临时键合胶上。
3.根据权利要求1所述的一种高密度线路扇出封装结构的制作方法,其特征在于,步骤一中,还包括步骤S14,具体为:在最外层的第一钝化层上涂覆干膜,并在干膜的对应金属焊盘的位置形成开口;该干膜能够填充第一封装结构和第二封装结构之间的连接界面。
4.根据权利要求1所述的一种高密度线路扇出封装结构的制作方法,其特征在于,步骤S21中,在形成第二金属重布线层和第二钝化层前,先在载板上涂覆一层临时键合胶。
5.根据权利要求1所述的一种高密度线路扇出封装结构的制作方法,其特征在于:第一金属重布线层和第二金属重布线层的线宽以及线间距为0.8-2.0μm。
6.根据权利要求1所述的一种高密度线路扇出封装结构的制作方法,其特征在于:所述金属凸块为金凸块、铜柱凸块或铜镍锡银凸块。
7.根据权利要求1所述的一种高密度线路扇出封装结构的制作方法,其特征在于:所述信号导出结构为锡球。
8.一种高密度线路扇出封装结构,其特征在于:包括互联的第一封装单元和第二封装单元;所述第一封装单元包括芯片、塑封于芯片上的塑封层、多层第一金属重布线层、多层第一钝化层以及连接在最下层的第一金属重布线层上的金属焊盘,第一金属重布线层与芯片电连接,所述芯片的背面暴露在外;所述第二封装单元包括多层第二金属重布线层、多层第二钝化层以及连接在最上层的第二金属重布线层上的金属凸块;所述金属凸块和金属焊盘连接;最外层的第二金属重布线层还连接有信号导出结构。
9.根据权利要求8所述的一种高密度线路扇出封装结构,其特征在于:第一封装单元和第二封装单元之间还填充有干膜。
10.根据权利要求8所述的一种高密度线路扇出封装结构,其特征在于:所述信号导出结构为锡球。
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