CN117042317B - Surface conducting layer removing method in circuit board processing, circuit board and processing method thereof - Google Patents
Surface conducting layer removing method in circuit board processing, circuit board and processing method thereof Download PDFInfo
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- CN117042317B CN117042317B CN202311279797.9A CN202311279797A CN117042317B CN 117042317 B CN117042317 B CN 117042317B CN 202311279797 A CN202311279797 A CN 202311279797A CN 117042317 B CN117042317 B CN 117042317B
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- 238000012545 processing Methods 0.000 title claims abstract description 47
- 238000003672 processing method Methods 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 370
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 129
- 229910052802 copper Inorganic materials 0.000 claims abstract description 129
- 239000010949 copper Substances 0.000 claims abstract description 129
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/07—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process being removed electrolytically
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a method for removing a surface layer conducting layer in circuit board processing, a circuit board and a processing method thereof, wherein the method for removing the surface layer conducting layer comprises the following steps: providing a separable substrate comprising an insulation base layer, an ultrathin copper layer and a carrier copper layer which are stacked from inside to outside; after double-sided multilayer circuit manufacturing and board dividing operation are carried out on the separable substrate, an intermediate board is obtained; the middle plate comprises a carrier copper layer and a plurality of circuit layers, effective pattern areas in the plurality of circuit layers are communicated with each other, at least two detection pads are arranged in two outermost circuit layers, and the carrier copper layer is used as a surface layer conducting layer of the middle plate; the surface conduction layer is removed through an electrolytic polishing process, the change condition of the physical quantity of a circuit between two detection pads positioned on the same layer or different layers is obtained in real time by utilizing a monitoring control system in the electrolytic polishing process, and the electrolytic parameters in the electrolytic polishing process are adjusted accordingly. The removing method has high processing accuracy, improves the processing quality and efficiency of the circuit board, and reduces the waste of productivity.
Description
Technical Field
The invention relates to the technical field of circuit board processing, in particular to a method for removing a surface conduction layer in circuit board processing, a circuit board and a processing method thereof.
Background
At present, electronic products are gradually miniaturized, and have high wiring density, small size and light weight. As an important carrier for electronic products, printed wiring boards and packaging substrates are increasingly developed toward high-precision circuits, dense pinholes and ultra-thin plates.
In the fabrication of ultra-thin plates, ultra-thin copper is often used as the surface via layer for the embedded wiring process, and the surface via layer is etched away in a later process. However, in the etching treatment of the surface conductive layer, the following disadvantages inevitably occur: 1) The device is affected by equipment precision, chemical liquid stability and processing parameters, and chemical liquid can attack a circuit layer when removing the surface conduction layer, so that circuit dishing is bad, and the surface flatness of a product and the downstream sealing and measuring technical requirements are affected. 2) The thickness of the ultra-thin copper is generally 1.5 to 5 μm, and thus the copper cannot be handled alone. Thus, the following operation modes are conventionally adopted: firstly, providing a sheet of raw foil with the thickness of 17 mu m as carrier copper, and utilizing a separable technology to detachably arrange ultrathin copper on the raw foil to obtain a composite copper layer; then the composite copper layer is pressed and fixed on the middle insulating layer in a manner that the green foil faces the middle insulating layer; and then, manufacturing circuits and the like on the ultrathin copper. However, the intermediate insulating layer of the double-sided green foil obtained in the above-described operation cannot be used for manufacturing other products (mainly because the green foil has a small surface roughness and cannot form a firm bond with the intermediate insulating layer), resulting in a certain waste.
In view of this, the present invention has been made.
Disclosure of Invention
In order to overcome the defects, the invention provides a method for removing a surface conduction layer in circuit board processing, a circuit board and a processing method thereof.
The technical scheme adopted by the invention for solving the technical problems is as follows: a method for removing a middle-surface conducting layer in circuit board processing comprises the following steps:
s1: providing a separable substrate, wherein the separable substrate comprises an insulating base layer, two ultrathin copper layers respectively arranged on two opposite sides of the insulating base layer, and two carrier copper layers respectively detachably arranged on two opposite sides of the ultrathin copper layers;
s2: after double-sided multilayer circuit manufacturing and board separation operation are carried out on the separable substrate, two middle boards are obtained;
each intermediate plate comprises a carrier copper layer and a plurality of circuit layers which are stacked on the carrier copper layer, effective pattern areas in the plurality of circuit layers are communicated with each other, and at least two detection pads are arranged at positions outside the effective pattern areas in the two outermost circuit layers; the carrier copper layer is communicated with the effective pattern area in the circuit layer adjacent to the carrier copper layer and the detection bonding pad, namely the carrier copper layer is used as a surface layer conducting layer of the intermediate plate;
S3: removing the surface conduction layer of the middle plate through an electrolytic polishing process; the method comprises the steps of utilizing a monitoring control system to acquire the change condition of the circuit physical quantity between two detection bonding pads positioned on the same layer in real time in the electrolytic polishing process, or acquiring the change condition of the circuit physical quantity between two detection bonding pads positioned on different layers in real time; and the monitoring control system correspondingly adjusts the electrolysis parameters in the electrolytic polishing process according to the obtained change condition of the physical quantity of the circuit between the two detection pads.
As a further improvement of the present invention, in the above S3, the circuit physical quantity between the two detection pads obtained in real time by the monitoring control system includes one of voltage, current, resistance and capacitance;
the electrolysis parameters in the electrolytic polishing process include at least one of an electrolysis voltage, an electrolysis current, an electrolysis time, and an electrolyte temperature.
As a further improvement of the present invention, in S2, the circuit layer in each intermediate board is N layers, where N is any natural number greater than 2; defining one circuit layer adjacent to the carrier copper layer as a first circuit layer, and correspondingly, defining one circuit layer farthest from the carrier copper layer as an Nth circuit layer;
The positions outside the effective pattern areas in the first circuit layer and the Nth circuit layer are respectively provided with a plurality of detection pads, the plurality of detection pads in the Nth circuit layer are mutually independent and are not communicated with the effective pattern areas in the detection pads, and the plurality of detection pads in the first circuit layer are mutually independent and are not communicated with the effective pattern areas in the detection pads without considering the carrier copper layer;
in this way, in the electrolytic polishing process, the voltage change value or the current change value or the resistance change value between the two detection pads in the first circuit layer is obtained in real time by utilizing the monitoring control system; or acquiring capacitance change values between the two detection pads respectively located on the first circuit layer and the Nth circuit layer in real time.
As a further improvement of the invention, the monitoring control system comprises a monitoring component and a controller, wherein the monitoring component comprises two probes, a current limiting resistor and a voltmeter, the two probes and the current limiting resistor are connected in series to an external power supply, and the two probes are respectively used for contacting with the two detection pads in the first circuit layer; the voltmeter is respectively connected with the two detection pads in the first circuit layer, and the voltmeter is also in communication connection with the controller.
As a further improvement of the invention, the monitoring control system comprises a monitoring component and a controller, wherein the monitoring component comprises two probes, a current limiting resistor, an ammeter and the controller, the two probes, the current limiting resistor and the ammeter are connected in series to an external power supply, the two probes are respectively used for contacting with the two detection bonding pads in the first circuit layer, and the ammeter is also connected with the controller in a communication way.
As a further improvement of the invention, the monitoring control system comprises a monitoring component and a controller, wherein the monitoring component comprises two probes, a detection resistor, a voltmeter and a controller, the two probes are respectively connected with an external power supply, and the two probes are respectively used for being in contact with two detection pads in the first circuit layer; the detection resistor is respectively connected with two detection pads in the first circuit layer and simultaneously forms a parallel connection relation with the carrier copper layer; the voltmeter is connected with the detection resistor in parallel, and the voltmeter is also connected with the controller in a communication mode.
As a further improvement of the present invention, the inspection pad in the first wiring layer is defined as an inspection pad a, the inspection pad in the nth wiring layer is defined as an inspection pad B, and an area of the inspection pad B is larger than an area of the inspection pad a;
The monitoring control system comprises a monitoring assembly and a controller, wherein the monitoring assembly comprises two probes and a universal meter, the two probes and the universal meter are connected in series with an external power supply, the two probes are respectively used for being in contact with one detection pad A and one detection pad B, the universal meter is used for detecting capacitance values of the detection pad A and the detection pad B, and the universal meter is also in communication connection with the controller.
As a further improvement of the present invention, the plurality of inspection pads in the first wiring layer and the plurality of inspection pads in the nth wiring layer are arranged in one-to-one correspondence.
As a further improvement of the invention, limiting holes are arranged beside a plurality of the detection pads in the first circuit layer.
As a further improvement of the present invention, the initial thickness of the carrier copper layer is defined as H; dividing the electrolytic polishing process in the step S3 into two stages according to the thickness change condition of the carrier copper layer, wherein the two stages are respectively as follows: a first stage when the thickness of the carrier copper layer is reduced from H to H/5, and a second stage when the thickness of the carrier copper layer is reduced from H/5 to 0;
wherein in the first stage of the electrolytic polishing process, the electrolytic voltage is 1-3V, the electrolytic current is 20-40 ASF, and the temperature of the electrolyte is 20-30 ℃;
In the second stage of the electrolytic polishing process, the electrolytic voltage is 1-3V, the electrolytic current is 5-20 ASF, and the temperature of the electrolyte is 20-30 ℃.
The invention also provides a circuit board processing method, which comprises the following steps:
s1: providing an intermediate plate with a surface layer conducting layer removed, wherein the intermediate plate with the surface layer conducting layer removed is manufactured by adopting the method for removing the surface layer conducting layer in the circuit board processing;
s2: and carrying out conventional film stripping, welding prevention, surface treatment and finished product testing processes on the intermediate plate with the surface conducting layer removed in sequence to finish the subsequent manufacturing of the required circuit board finished product.
The invention also provides a circuit board which is manufactured by adopting the circuit board processing method.
The beneficial effects of the invention are as follows: compared with the prior art, the method for removing the surface conduction layer in the circuit board processing has the following advantages: 1) The surface conduction layer of the intermediate plate is removed through an electrolytic polishing process, and a physical method is used for monitoring the reaction end point in the electrolytic polishing process, so that a monitoring control system can be ensured to timely, accurately and effectively output a signal for stopping the electrolytic reaction, the product is prevented from staying in the liquid medicine for too long or insufficient time, the processing quality of the product is further improved, and the waste of productivity is reduced; in addition, by adopting the electrolytic polishing process, the operation is simple, and the undercut risk brought by the etching process can be well overcome, so that the circuit flatness can be effectively improved. 2) By using the physical method to monitor the reaction end point in the electrolytic polishing process, the monitoring control system can properly adjust the electrolytic parameters in the electrolytic polishing process, thereby obtaining finer polishing effect and better improving the production efficiency. 3) The method for removing the surface conduction layer in the circuit board processing is novel and reasonable, flexible in processing and easy to implement, and can improve the utilization rate of raw materials and reduce the waste of the raw materials.
Drawings
FIG. 1 is a flow chart of a method for removing a surface conduction layer in circuit board processing;
FIG. 2 is a schematic cross-sectional view of a separable substrate according to the present invention;
FIG. 3 is a schematic cross-sectional view of a substrate A according to the present invention;
FIG. 4 is a schematic cross-sectional view of a substrate B according to the present invention;
FIG. 5 is a schematic cross-sectional view of a substrate C according to the present invention;
FIG. 6 is a schematic cross-sectional view of a substrate E according to the present invention;
FIG. 7 is a schematic cross-sectional view of a substrate F according to the present invention;
FIG. 8 is a schematic cross-sectional view of an intermediate plate according to the present invention;
FIG. 9 is a schematic diagram showing a partial structure of a monitoring control system according to embodiment 1 of the present invention;
FIG. 10 is a schematic diagram showing a partial structure of a monitoring control system according to embodiment 2 of the present invention;
FIG. 11 is a schematic diagram showing a partial structure of a monitoring control system according to embodiment 3 of the present invention;
fig. 12 is a flowchart of a circuit board processing method according to the present invention.
The following description is made with reference to the accompanying drawings:
1. a separable substrate; 10. an insulation base layer; 11. an ultra-thin copper layer; 12. a carrier copper layer; 2. an intermediate plate; 20. a first effective pattern area; 21. detecting the bonding pad A; 22. a second effective pattern area; 23 Nth active graphic region; 24. detecting a bonding pad B; 30. a probe; 31. detecting a resistor; 4. laminating the layer A; 40. an ultrathin copper layer A; 41. a carrier copper layer A; 42. an insulation base layer a; 5. laminating the layer B; 50. an ultrathin copper layer B; 51. a carrier copper layer B; 52. and an insulation base layer B.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Example 1
Referring to fig. 1, embodiment 1 provides a method for removing a middle-surface conductive layer in circuit board processing, which mainly includes the following steps:
s1: referring to fig. 2, a separable substrate 1 is provided, wherein the separable substrate 1 includes an insulation base layer 10, two ultrathin copper layers 11 respectively disposed on opposite sides of the insulation base layer 10, and two carrier copper layers 12 respectively detachably disposed on opposite sides of the ultrathin copper layers 11.
Specifically, the separable substrate 1 used in this example 1 was manufactured by the following manufacturing method:
s10: providing an insulation base layer 10;
the insulation base layer 10 is preferably made of PP glass fiber cloth, and the types and the number of the PP glass fiber cloth can be matched according to the thickness requirement of the product, and the invention does not limit the PP glass fiber cloth too much.
S11: manufacturing a composite copper layer;
firstly, providing two carrier copper layers 12, wherein the thickness of the carrier copper layers 12 is preferably 15-35 mu m (20 mu m or 30 mu m can be further preferred);
next, after the two copper layers 12 are subjected to a chemical treatment, an ultra-thin copper layer 11 with a thickness of 1.5-3 μm (the thickness of the ultra-thin copper layer 11 may be more preferably 2 μm or 2.5 μm) is deposited on the two copper layers 12 by an electrodeposition process, respectively, to obtain two composite copper layers.
Description: before the electrodeposition process, the carrier copper layer 12 is subjected to a liquid medicine treatment in order to ensure that a predetermined peeling force is provided between the ultra-thin copper layer 11 and the carrier copper layer 12, so that good separation can be achieved. This is a conventional technical means in the technical field of circuit boards, and therefore will not be described in detail here.
S12: firstly, placing the insulating base layer 10 between two composite copper layers, specifically, placing the insulating base layer 10 between two ultrathin copper layers 11; and then, the two composite copper layers are firmly combined with the insulating base layer 10 through a hot pressing process, so that the separable substrate 1 is obtained.
Description: (1) the hot pressing process belongs to a conventional technical means in the technical field of circuit boards, and therefore, is not described in detail herein. (2) By directly combining the ultrathin copper layer 11 with the insulation base layer 10, the obtained substrate G composed of the insulation base layer 10 and the ultrathin copper layer 11 can be used for manufacturing other products after the plate separation operation of the post-processing is completed, thereby improving the utilization rate of raw materials and reducing the cost waste.
S2: after double-sided multilayer circuit manufacturing and board dividing operation are carried out on the separable substrate 1, two middle boards 2 are obtained; each intermediate plate 2 comprises a carrier copper layer 12 and a plurality of circuit layers which are stacked on the carrier copper layer 12, wherein effective pattern areas in the plurality of circuit layers are mutually communicated, and at least two detection pads are arranged at positions outside the effective pattern areas in the two outermost circuit layers; the carrier copper layer 12 is connected to the effective pattern area and the inspection pad in the adjacent circuit layer, i.e. the carrier copper layer 12 is used as the surface conduction layer of the intermediate plate 2.
Specifically, in this embodiment 1, when the separable substrate 1 is subjected to the double-sided multi-layer circuit manufacturing and the board dividing operation, the manufacturing method is as follows:
s20: after the separable substrate 1 is sequentially subjected to plating resist photosensitive film, exposure, development, pattern plating, film stripping and browning pretreatment processing, a first circuit layer L1 is respectively formed on the two carrier copper layers 12 (it is understood that the first circuit layer L1 is adjacent to the carrier copper layers 12), and a substrate a is obtained (see fig. 3); each first circuit layer L1 includes an effective pattern area and at least two detection pads located outside the effective pattern area (such as a board edge).
Description: (1) at least two of the inspection pads in the first wiring layer L1 are independent of each other and are not in communication with the effective pattern area therein, regardless of the carrier copper layer 12 (i.e., based on the structure of the first wiring layer L1 alone), so as to prevent electrolysis under power-on conditions. (2) Because the circuit layer in each middle plate 2 is N layers, N is any natural number greater than 2; for convenience of description (not limiting the scope of the invention, which can be implemented by the patent), the structure of the N-layer circuit layer will be defined and differentiated, for example: the effective pattern areas in the first line layer L1 to the nth line layer LN are defined as: a first effective pattern area … … nth effective pattern area; the detection pads in the first line layer L1 and the nth line layer LN are defined as: a sense pad a and a sense pad B.
Based on the above definition, the first line layer L1 may be described as: the first circuit layer L1 includes a first effective pattern area 20 and at least two inspection pads a21 located outside the first effective pattern area 20 (e.g., at a board edge).
And further preferably, the inspection pads a21 in the first circuit layer L1 may be configured in a plurality and in pairs, and of course, two inspection pads a21 in a pair are located on the same side of the product and adjacent to each other, so that the probes 30 in the monitoring and controlling system can be conveniently contacted with the two inspection pads a21 in a pair when the electropolishing operation is performed later. In addition, in order to realize that the monitoring of the product covers the whole product, and improve the monitoring accuracy, it is also preferable that a pair of detection pads a21 (a pair of detection pads a21 may be collectively referred to as a detection pad pair) are respectively provided at four corners and a middle position in the first circuit layer L1.
Further preferably, limiting holes are further formed beside the plurality of detecting pads a21 in the first circuit layer L1. Since the inspection pad a is visually difficult to identify when the carrier copper layer 12 is not removed, the limit holes are mechanically drilled beside the inspection pad a to perform a good limit and identification function.
S21: firstly, carrying out double-sided lamination operation on the substrate A so as to respectively press-fit a pressing layer A4 on the two first circuit layers L1 to obtain a substrate B (refer to fig. 4); wherein, compared with the double-sided structure of the separation substrate 1, the lamination layer A4 is a single-sided structure, i.e.: the lamination layer A4 comprises an insulation base layer, an ultrathin copper layer arranged on one surface of the insulation base layer and a carrier copper layer detachably arranged on the ultrathin copper layer; the molding method of the lamination layer A4 is the same as that of the separation substrate 1, so that no description is given here; however, in order to distinguish the lamination layer A4 from the separation substrate 1, the insulation base layer, the ultra-thin copper layer and the carrier copper layer in the lamination layer A4 are now defined as: an insulation base layer a (labeled 42, respectively), an ultra-thin copper layer a (labeled 40, respectively) and a carrier copper layer a (41, respectively); moreover, the model and thickness of the two lamination layers A4 must be kept consistent, so as to reduce the warping risk caused by the asymmetric structure; in addition, for each first circuit layer L1, the first effective pattern area 20 and the detection pad a21 thereof are completely covered by the lamination layer A4;
Then sequentially removing a carrier copper layer, laser windowing, laser drilling, copper deposition, film coating pretreatment, plating an anti-plating photosensitive film, exposing, developing, pattern electroplating, film stripping, etching and browning pretreatment processing are carried out on the obtained substrate B, and respectively forming a second circuit layer L2 on the ultrathin copper layers A40 of the two lamination layers A4, thereby obtaining a substrate C (refer to fig. 5); wherein each of the second circuit layers L2 includes a second effective pattern area 22, but does not include a detection pad. And the second effective pattern area 22 communicates with the first effective pattern area 20.
S22: repeating the step S21 (N-3) for a plurality of times to obtain a substrate D containing the first to (N-1) -th circuit layers L1 to L (N-1); the second line layer L2 to the (N-1) th line layer L (N-1) comprise effective pattern areas, but do not contain detection pads. Further, the effective pattern areas in the second line layer L2 to the (N-1) th line layer L (N-1) are communicated with each other.
S23: firstly, carrying out double-sided lamination operation on the obtained substrate D to respectively press-fit a pressing layer B5 on the two (N-1) th circuit layers to obtain a substrate E (refer to fig. 6); the structure and the forming manner of the lamination layer B5 are the same as those of the lamination layer A4, so that detailed description is omitted herein, but in order to distinguish the lamination layer B5 from the lamination layer A4, the insulation base layer, the ultrathin copper layer and the carrier copper layer in the lamination layer B5 are defined as follows: an insulation base layer B (corresponding labeled 52), an ultra-thin copper layer B (corresponding labeled 50), and a carrier copper layer B (corresponding labeled 51); the model and thickness of the two pressing layers B5 are required to be kept consistent, so that the warping risk caused by an asymmetric structure is reduced;
Then sequentially removing the carrier copper layer, laser windowing, laser drilling, copper deposition, film coating pretreatment, plating an anti-plating photosensitive film, exposing, developing, pattern electroplating, film stripping and etching the obtained substrate E, and respectively forming an Nth circuit layer LN (the distance between the Nth circuit layer and the carrier copper layer 12 of the separable substrate 1 is the farthest) on the ultrathin copper layers B50 of the two pressing layers B5, thereby obtaining a substrate F (refer to the figure 7); each of the nth circuit layers LN includes an nth effective pattern area 23 and at least two detection pads B24 located outside the nth effective pattern area 23 (e.g. at a board edge), and the nth effective pattern area 23 is mutually communicated with the effective pattern areas in the first circuit layer L1 to the (N-1) th circuit layer L (N-1).
Description: at least two of the detection pads B24 in the nth wiring layer are independent from each other and are not communicated with the nth effective pattern area 23 therein, so as to prevent electrolysis under the condition of power-on.
Further preferably, the inspection pads B24 in the nth wiring layer are also configured in plural and paired, that is: the plurality of detection pads B24 in the Nth line layer LN are arranged in one-to-one opposite to the plurality of detection pads A21 in the first line layer L1; thus being convenient for processing and manufacturing.
S24: the obtained substrate F is subjected to a dividing operation to obtain two of the intermediate plates 2 (see fig. 8) and one of the substrates G.
Further preferably, the processing technologies of "removing the carrier copper layer, laser windowing, laser drilling, copper deposition, pretreatment of coating, coating of plating resist, exposure, development, pattern electroplating, film stripping, etching and pretreatment of browning" described in S20 to S23 all belong to the technical means commonly used in the technical field of circuit board processing, and therefore are not described in detail herein, but only briefly described as follows:
(1) and (3) removing the carrier copper layer: the operation is used in S21 to S23, in which the carrier copper layer (such as the carrier copper layer a41, the carrier copper layer B51, etc.) in the bonding layer (such as the bonding layer a, the bonding layer B, etc.) is removed by mechanical stripping.
(2) Laser windowing and laser drilling operation: the operation is performed in S21 to S23 by using CO 2 The laser drills the substrate B, the substrate E and the like to form blind holes communicated with the effective pattern areas in the circuit layer.
(3) Copper deposition operation: the operation is used in S21 to S23, wherein a copper layer is deposited in the obtained blind hole so as to form a connection copper layer which is electrically communicated with an effective pattern area in the circuit layer; namely, the mutual communication of the effective pattern areas in the multi-layer circuit layer is realized.
(4) Coating pretreatment and coating plating-resistant photosensitive film operation: the pretreatment operation of coating is used in S21 to S23, which is to clean, heat and dry the substrate B, the substrate E, etc. after completing the copper deposition operation, so as to facilitate the subsequent operations of coating plating-resistant photosensitive film, etc.;
plating-resistant photosensitive film work is used in S20 to S23, and for S20, the work is to apply a photosensitive dry film to two of the carrier copper layers 12, or to apply a photosensitive wet film to two of the carrier copper layers 12; for S21 to S23, the operation is to attach the photosensitive dry film to the ultra-thin copper layer (such as ultra-thin copper layer a40, ultra-thin copper layer B50, etc.) of the lamination layer, or to coat the photosensitive wet film to the ultra-thin copper layer (such as ultra-thin copper layer a40, ultra-thin copper layer B50, etc.) of the lamination layer.
(5) Exposure and development operation: this operation is used in S20 to S23, where the exposure operation is to expose a partial region of the photosensitive film and the development operation is to remove an unexposed region of the photosensitive film.
(6) Graphic electroplating operation: the operation is used in S20 to S23, in which a copper layer is electrodeposited on the exposed region of the photosensitive film to form an effective pattern region in the wiring layer, or an effective pattern region and a detection pad in the wiring layer;
(7) Film removing operation: this operation is used in S20 to S23, in which the photosensitive film is removed using a strongly alkaline solution.
(8) Etching: the operation is used in S21 to S23, in which the portions of the ultra-thin copper layer (such as ultra-thin copper layer a40, ultra-thin copper layer B50, etc.) of the lamination layer exposed outside the circuit layer are etched away;
(9) and (3) browning pretreatment operation: the operation is used in S20 to S22, and a layer of uniform fluff is formed on the circuit layer so as to increase the binding force between the circuit layer and the lamination layer and avoid the problems of layering and board explosion and the like.
Further preferably, the lamination operations described in S21 to S23 are hot press processes, which are conventional techniques in the field of circuit board processing technology, and therefore are not described in detail herein.
Further preferably, the above-mentioned board separation operation in S24 can be implemented by a conventional mechanical stripping method, which is also a conventional technical means in the technical field of circuit board processing, and therefore will not be described in detail herein.
In addition, after the above S24 is completed, the obtained intermediate plate 2 is also required to be subjected to conventional positioning hole drilling and tool hole drilling operations, outer layer line protection operations, and the like, according to the product processing requirements, so as to prepare for the subsequent electropolishing operations.
Description: the positioning holes and the tool holes are used for work fool-proofing. The outer layer circuit protection operation is realized by covering (protecting) the Nth effective pattern area 23 in the Nth circuit layer and completely exposing the detection pad B24, the detection pad A21 and the carrier copper layer 12 after the plating-resistant photosensitive film, the exposure and the development operation.
S3: removing the surface conduction layer of the middle plate 2 through an electrolytic polishing process; the method comprises the steps of utilizing a monitoring control system to acquire the change condition of the circuit physical quantity between two detection bonding pads positioned on the same layer in real time in the electrolytic polishing process, or acquiring the change condition of the circuit physical quantity between two detection bonding pads positioned on different layers in real time; and the monitoring control system correspondingly adjusts the electrolysis parameters in the electrolytic polishing process according to the obtained change condition of the physical quantity of the circuit between the two detection pads.
Specifically, the circuit physical quantity between the two detection pads obtained in real time by the monitoring control system comprises one of voltage, current, resistance and capacitance; the electrolysis parameters in the electrolytic polishing process include at least one of an electrolysis voltage, an electrolysis current, an electrolysis time, and an electrolyte temperature.
And based on the above-described structure of the intermediate plate 2, it is further preferable that, in the electrolytic polishing process, a voltage change value or a current change value or a resistance change value between the two detection pads a21 in the first line layer L1 can be obtained in real time by using the monitoring control system; or, the capacitance change values between the two detection pads respectively located on the first line layer L1 and the nth line layer LN are obtained in real time (i.e., the capacitance change values between one detection pad a21 and one detection pad B24 are obtained).
Still more preferably, the specific structure and working principle of the monitoring control system used in this embodiment 1 are as follows:
referring to fig. 9, the monitoring control system includes a monitoring assembly and a controller, the monitoring assembly includes two probes 30, a current limiting resistor R1 and a voltmeter V, the two probes 30 and the current limiting resistor R1 are connected in series to an external power source, and the two probes 30 are further respectively used for contacting with two detection pads a21 in the first circuit layer L1, namely: the probe 30 is used for applying voltage to the detection pad A, the current limiting resistor R1 is used for limiting the current in a loop and protecting a circuit; the voltmeter V is respectively connected with the two detection pads A21 in the first circuit layer L1, and the voltmeter V is also in communication connection with the controller.
With the above structure of the monitoring control system, the working principle/method of the monitoring control system for monitoring the surface conduction layer of the intermediate plate 2 in the electrolytic polishing process is as follows: the conducting state between the two detection pads A21 is monitored through the voltmeter V, when the carrier copper layer 12 is thinner, the resistance between the two detection pads A21 shows an increasing trend (can be understood according to a resistance formula), and the voltage value measured by the voltmeter V is gradually increased; when the carrier copper layer 12 is completely removed, the resistance between the two detection pads a21 reaches infinity, and the voltage value measured by the voltmeter V tends to the voltage applied by the external power supply, that is, it represents termination of the electrolytic polishing reaction.
Still further preferably, regarding the selection of the two inspection pads a in the first wiring layer L1, it is possible to select at random, but it is generally preferable that the two inspection pads a be arranged in pairs.
In addition, based on the above-mentioned four corners and the middle position in the first circuit layer L1 are respectively provided with a pair of the detection pads a21, and four corners and the middle position in the nth circuit layer LN are respectively provided with a pair of the detection pads B24, in this embodiment 1, the monitoring components in the monitoring control system are also configured into multiple groups (e.g., five groups) so as to match with the layout of the detection pads, so as to improve the monitoring accuracy.
In addition, based on the monitoring mode of the monitoring control system for the surface conductive layer of the middle plate 2 in the electrolytic polishing process, the method for adjusting the electrolytic parameters in the electrolytic polishing process by the monitoring control system comprises the following steps: defining the initial thickness of the carrier copper layer 12 as H; the electrolytic polishing process in S3 is divided into two stages according to the thickness variation of the copper layer 12, which are respectively: a first stage when the thickness of the carrier copper layer 12 is reduced from H to H/5, and a second stage when the thickness of the carrier copper layer 12 is reduced from H/5 to 0 (zero);
wherein in the first stage of the electrolytic polishing process, the electrolytic voltage is 1-3V, the electrolytic current is 20-40 ASF, and the temperature of the electrolyte is 20-30 ℃; in the second stage of the electrolytic polishing process, the electrolytic voltage is 1-3V, the electrolytic current is 5-20 ASF, and the temperature of the electrolyte is 20-30 ℃.
By staging the electropolishing process, finer polishing results can be achieved. It will be appreciated, of course, that in addition to the above-described separation of the electropolishing process into two stages, the electropolishing process may be performed in multiple stages depending on the production requirements, and the invention is not limited.
Description: the electrolytic polishing process belongs to a common processing process in the field of circuit boards, and a cathode of the electrolytic polishing process is generally made of conductive materials resistant to electrolyte corrosion, such as lead, stainless steel and the like; the electrolyte generally contains sulfuric acid and phosphoric acid as basic components.
Example 2
In the embodiment 2, a method for removing the middle-surface conductive layer in the circuit board processing is also provided, and compared with the embodiment 1, the difference in the embodiment 2 is that: in the case of electropolishing, the specific structure and operation principle of the monitoring control system used in this example 2 are different from those of example 1.
Specifically, the specific structure and working principle of the monitoring control system used in this embodiment 2 are as follows:
referring to fig. 10, the monitoring control system includes a monitoring assembly and a controller, the monitoring assembly includes two probes 30, a current limiting resistor R1, an ammeter a and a controller, the two probes 30, the current limiting resistor R1 and the ammeter a are connected in series to an external power source, and the two probes 30 are further respectively used for contacting with two detection pads a21 in the first circuit layer L1, namely: the probe 30 is used for applying voltage to the detection pad A, the current limiting resistor R1 is used for limiting the current in a loop and protecting a circuit; the ammeter A is also in communication connection with the controller.
With the above structure of the monitoring control system, the working principle/method of the monitoring control system for monitoring the surface conduction layer of the intermediate plate 2 in the electrolytic polishing process is as follows: the conducting state between the two detection pads A21 is monitored through the ammeter A, when the carrier copper layer 12 is thinner, the resistance between the two detection pads A21 shows an increasing trend (can be obtained according to a resistance formula), and the current value measured by the ammeter A is gradually reduced; when the carrier copper layer 12 is completely removed, the resistance between the two detection pads a reaches infinity, and the current value measured by the ammeter a tends to be 0, which means that the electrolytic polishing reaction is terminated.
Further preferably, regarding the selection of the two inspection pads a in the first wiring layer L1, it is possible to select at random, but it is generally preferable to dispose the two inspection pads a in pairs.
In addition, based on the above-mentioned four corners and the middle position in the first circuit layer L1 are respectively provided with a pair of the detection pads a21, and four corners and the middle position in the nth circuit layer LN are respectively provided with a pair of the detection pads B24, in this embodiment 2, the monitoring components in the monitoring control system are also configured into multiple groups (e.g., five groups) so as to match with the layout of the detection pads, so as to improve the monitoring accuracy.
Description: in embodiment 2, except for the specific structure and working principle of the monitoring control system, the method for manufacturing the intermediate plate, the method for adjusting the electrolytic parameters in the electrolytic polishing process by the monitoring control system, and the like adopted in embodiment 2 are the same as those in embodiment 1, so that the description thereof will not be repeated here.
Example 3
In addition, embodiment 3 also provides a method for removing the middle-surface conductive layer in the circuit board processing, and compared with embodiment 1, the difference in this embodiment 3 is that: in the case of electropolishing, the specific structure and operation principle of the monitoring control system used in this example 3 are different from those of example 1.
Specifically, the specific structure and working principle of the monitoring control system used in this embodiment 3 are as follows:
referring to fig. 11, the monitoring control system includes a monitoring assembly and a controller, the monitoring assembly includes two probes 30, a detection resistor 31, a voltmeter V and a controller, the two probes 30 are respectively connected to the positive and negative poles of an external power source, and the two probes 30 are respectively used for contacting with the two detection pads a21 in the first circuit layer L1, namely: the probe 30 is used for applying a voltage to the detection pad a; the detection resistors 31 (preferably, a resistor wire structure is adopted) are respectively connected with the two detection pads a21 in the first circuit layer L1, and form a parallel connection relationship with the carrier copper layer 12; the voltmeter V is connected in parallel with the detection resistor 31, and the voltmeter V is also connected in communication with the controller.
With the above structure of the monitoring control system, the working principle/method of the monitoring control system for monitoring the surface conduction layer of the intermediate plate 2 in the electrolytic polishing process is as follows: when the carrier copper layer 12 is not removed, the detection resistor 31 is in a short circuit state, and the resistor is 0; when the carrier copper layer 12 is removed, the detection resistor 31 reaches a set resistance and no change occurs; this represents termination of the electropolishing reaction.
Further preferably, regarding the selection of the two inspection pads a in the first wiring layer L1, it is possible to select at random, but it is generally preferable to dispose the two inspection pads a in pairs.
In addition, based on the above-mentioned four corners and the middle position in the first circuit layer L1 are respectively provided with a pair of the detection pads a21, and four corners and the middle position in the nth circuit layer LN are respectively provided with a pair of the detection pads B24, in this embodiment 3, the monitoring components in the monitoring control system are also configured into multiple groups (e.g., five groups) to match with the layout of the detection pads, so as to improve the monitoring accuracy.
Description: in embodiment 3, except for the specific structure and working principle of the monitoring control system, the method for manufacturing the intermediate plate, the method for adjusting the electrolytic parameters in the electrolytic polishing process by the monitoring control system, and the like adopted in embodiment 3 are the same as those in embodiment 1, so that the description thereof will not be repeated here.
Example 4
In the embodiment 4, a method for removing the middle-surface conductive layer in the circuit board processing is also provided, and compared with the embodiment 1, the difference in the embodiment 4 is that: in the case of electropolishing, the specific structure and operation principle of the monitoring control system used in this example 4 are different from those of example 1.
Specifically, the specific structure and working principle of the monitoring control system used in this embodiment 4 are as follows:
the monitoring control system comprises a monitoring assembly and a controller, the monitoring assembly comprises two probes 30 and a universal meter, the two probes 30 and the universal meter are connected in series to an external power supply, and the two probes 30 are respectively used for contacting with one detection pad A21 and one detection pad B24, namely: the probe 30 is used for applying voltage to the detection pad; the universal meter is used for detecting capacitance values of the detection pad A21 and the detection pad B24, and is also in communication connection with the controller.
With the above structure of the monitoring control system, the working principle/method of the monitoring control system for monitoring the surface conduction layer of the intermediate plate 2 in the electrolytic polishing process is as follows: after the electropolishing of the carrier copper layer 12 is completed, the capacitance value decreases (which can be derived from the capacitance equation), which represents the termination of the electropolishing reaction.
Further preferably, the area of the inspection pad B is larger than the area of the inspection pad a. The purpose of this design is: on the one hand, to prevent the opposite areas of the detection pad a and the detection pad B from being fluctuated due to the influence of the pattern offset, and on the other hand, to realize the capacitance value difference before and after the electropolishing, namely, to monitor the capacitance value difference (after the electropolishing, the opposite areas of the detection pad a and the detection pad B are reduced, and correspondingly, the capacitance value is reduced), so as to output a signal of terminating the reaction.
Further preferably, regarding the selection of the above-described inspection pad a21 and inspection pad B24, it may be selected at random, but it is generally preferable that the inspection pad a21 and the inspection pad B24 are arranged in a vertically opposed/vertically opposed manner.
In addition, based on the above-mentioned four corners and the middle position in the first circuit layer L1 are respectively provided with a pair of the detection pads a21, and four corners and the middle position in the nth circuit layer LN are respectively provided with a pair of the detection pads B24, in this embodiment 4, the monitoring components in the monitoring control system are also configured into multiple groups (e.g. five groups) to match with the layout of the detection pads, so as to improve the monitoring accuracy.
Description: in embodiment 4, except for the specific structure and working principle of the monitoring control system, the method for manufacturing the intermediate plate, the method for adjusting the electrolytic parameters in the electrolytic polishing process by the monitoring control system, and the like adopted in embodiment 4 are the same as those in embodiment 1, and therefore are not described in detail herein.
Example 5
Referring to fig. 12, embodiment 5 provides a circuit board processing method, which mainly includes the following steps:
s1: providing a middle plate 2 with a surface layer conducting layer removed, wherein the middle plate 2 with the surface layer conducting layer removed is manufactured by adopting the surface layer conducting layer removing method in the circuit board processing provided by any one of the embodiment 1 to the embodiment 4;
s2: and carrying out conventional film stripping, welding prevention, surface treatment and finished product testing processes on the intermediate plate 2 with the surface conducting layer removed in sequence to finish the subsequent manufacturing of the required circuit board finished product.
Description: the "film removing" operation is to remove the plating resist photosensitive film covered in the "outer layer line protecting operation" which is a previous step. The "anti-soldering, surface treatment, and finished product testing process" are all processing processes commonly used in the field of circuit board processing, and therefore are not described in detail herein.
Example 6
Embodiment 6 provides a circuit board manufactured by the circuit board processing method provided in embodiment 5.
The specific structure of the circuit board is described in detail in embodiment 1, and thus will not be described in detail herein.
Description: the "first", "second", etc. of the component name prefixes (e.g., the first circuit layer, the second circuit layer, etc.), and the "a", "B" of the component name suffixes (e.g., the inspection pad a, the inspection pad B, etc.) are provided herein for convenience of description only, and are not intended to limit the scope of the present invention as applicable.
In summary, the method for removing the surface conducting layer in the circuit board processing provided by the invention has the following advantages: 1) The surface conduction layer of the intermediate plate is removed through an electrolytic polishing process, and a physical method is used for monitoring the reaction end point in the electrolytic polishing process, so that a monitoring control system can be ensured to timely, accurately and effectively output a signal for stopping the electrolytic reaction, the product is prevented from staying in the liquid medicine for too long or short time, the processing quality of the product is further improved, and the waste of productivity is reduced; in addition, by adopting the electrolytic polishing process, the operation is simple, and the undercut risk brought by the etching process can be well overcome, so that the circuit flatness can be effectively improved. 2) By using the physical method to monitor the reaction end point in the electrolytic polishing process, the monitoring control system can properly adjust the electrolytic parameters in the electrolytic polishing process, thereby obtaining finer polishing effect and better improving the production efficiency. 3) The method for removing the surface conduction layer in the circuit board processing is novel and reasonable, flexible in processing and easy to implement, and can improve the utilization rate of raw materials and reduce the waste of the raw materials.
In the above description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The foregoing description is only of a preferred embodiment of the invention, which can be practiced in many other ways than as described herein, so that the invention is not limited to the specific implementations disclosed above. While the foregoing disclosure has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes and modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. Any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention without departing from the technical solution of the present invention still falls within the scope of the technical solution of the present invention.
Claims (12)
1. A method for removing a surface conduction layer in circuit board processing is characterized by comprising the following steps: the method comprises the following steps:
s1: providing a separable substrate (1), wherein the separable substrate (1) comprises an insulating base layer (10), two ultrathin copper layers (11) respectively arranged on two opposite sides of the insulating base layer (10), and two carrier copper layers (12) respectively arranged on two opposite sides of the ultrathin copper layers (11) in a detachable manner;
S2: after double-sided multilayer circuit manufacturing and board dividing operation are carried out on the separable substrate (1), two middle boards (2) are obtained;
each intermediate plate (2) comprises a carrier copper layer (12) and a plurality of circuit layers which are stacked on the carrier copper layer (12), effective pattern areas in the plurality of circuit layers are mutually communicated, and at least two detection pads are arranged at positions outside the effective pattern areas in the two outermost circuit layers; the carrier copper layer (12) is communicated with the effective pattern area in the adjacent circuit layer and the detection bonding pad, namely the carrier copper layer (12) is used as a surface conduction layer of the middle plate (2);
s3: removing the surface conduction layer of the intermediate plate (2) through an electrolytic polishing process; the method comprises the steps of utilizing a monitoring control system to acquire the change condition of the circuit physical quantity between two detection bonding pads positioned on the same layer in real time in the electrolytic polishing process, or acquiring the change condition of the circuit physical quantity between two detection bonding pads positioned on different layers in real time; and the monitoring control system correspondingly adjusts the electrolysis parameters in the electrolytic polishing process according to the obtained change condition of the physical quantity of the circuit between the two detection pads.
2. The method for removing a surface conductive layer in circuit board processing according to claim 1, wherein: in the step S3, the circuit physical quantity between the two detection pads obtained in real time by the monitoring control system includes one of voltage, current, resistance and capacitance;
the electrolysis parameters in the electrolytic polishing process include at least one of an electrolysis voltage, an electrolysis current, an electrolysis time, and an electrolyte temperature.
3. The method for removing a surface conductive layer in circuit board processing according to claim 2, wherein: in the step S2, the circuit layer in each intermediate plate (2) is N layers, and N is any natural number greater than 2; defining one of the circuit layers adjacent to the carrier copper layer (12) as a first circuit layer, and correspondingly, defining one of the circuit layers furthest from the carrier copper layer (12) as an Nth circuit layer;
the positions outside the effective pattern areas in the first circuit layer and the Nth circuit layer are respectively provided with a plurality of detection pads, the plurality of detection pads in the Nth circuit layer are mutually independent and are not communicated with the effective pattern areas in the detection pads, and the plurality of detection pads in the first circuit layer are mutually independent and are not communicated with the effective pattern areas in the detection pads without considering the carrier copper layer (12);
In this way, in the electrolytic polishing process, the voltage change value or the current change value or the resistance change value between the two detection pads in the first circuit layer is obtained in real time by utilizing the monitoring control system; or acquiring capacitance change values between the two detection pads respectively located on the first circuit layer and the Nth circuit layer in real time.
4. The method for removing a surface conductive layer in circuit board processing according to claim 3, wherein: the monitoring control system comprises a monitoring assembly and a controller, wherein the monitoring assembly comprises two probes (30), a current limiting resistor and a voltmeter, the two probes (30) and the current limiting resistor are connected in series to an external power supply, and the two probes (30) are respectively used for being in contact with two detection pads in the first circuit layer; the voltmeter is respectively connected with the two detection pads in the first circuit layer, and the voltmeter is also in communication connection with the controller.
5. The method for removing a surface conductive layer in circuit board processing according to claim 3, wherein: the monitoring control system comprises a monitoring component and a controller, wherein the monitoring component comprises two probes (30), a current limiting resistor, an ammeter and the controller, the two probes (30), the current limiting resistor and the ammeter are connected in series to an external power supply, the two probes (30) are respectively used for contacting with the two detection pads in the first circuit layer, and the ammeter is in communication connection with the controller.
6. The method for removing a surface conductive layer in circuit board processing according to claim 3, wherein: the monitoring control system comprises a monitoring assembly and a controller, wherein the monitoring assembly comprises two probes (30), a detection resistor (31), a voltmeter and the controller, the two probes (30) are respectively connected to an external power supply, and the two probes (30) are respectively used for being in contact with two detection pads in the first circuit layer; the detection resistors (31) are respectively connected with two detection pads in the first circuit layer and form a parallel connection relationship with the carrier copper layer (12); the voltmeter is connected in parallel with the detection resistor (31), and the voltmeter is also connected in communication with the controller.
7. The method for removing a surface conductive layer in circuit board processing according to claim 3, wherein: defining the detection pad in the first circuit layer as a detection pad A, defining the detection pad in the Nth circuit layer as a detection pad B, and enabling the area of the detection pad B to be larger than that of the detection pad A;
the monitoring control system comprises a monitoring assembly and a controller, wherein the monitoring assembly comprises two probes (30) and a universal meter, the two probes (30) and the universal meter are connected in series to an external power supply, the two probes (30) are respectively used for being in contact with one detection pad A and one detection pad B, the universal meter is used for detecting capacitance values of the detection pad A and the detection pad B, and the universal meter is also in communication connection with the controller.
8. The method for removing a surface layer via layer in circuit board processing according to any one of claims 4 to 7, characterized in that: the plurality of detection pads in the first circuit layer and the plurality of detection pads in the Nth circuit layer are arranged in a one-to-one opposite mode.
9. The method for removing a surface conductive layer in circuit board processing according to claim 3, wherein: limiting holes are formed beside the plurality of detection bonding pads in the first circuit layer.
10. The method for removing a surface conductive layer in circuit board processing according to claim 3, wherein: defining an initial thickness of the carrier copper layer (12) as H; the electrolytic polishing process in the above step S3 is divided into two stages according to the thickness change condition of the carrier copper layer (12), respectively: a first stage when the thickness of the carrier copper layer (12) is reduced from H to H/5, and a second stage when the thickness of the carrier copper layer (12) is reduced from H/5 to 0;
wherein in the first stage of the electrolytic polishing process, the electrolytic voltage is 1-3V, the electrolytic current is 20-40 ASF, and the temperature of the electrolyte is 20-30 ℃;
in the second stage of the electrolytic polishing process, the electrolytic voltage is 1-3V, the electrolytic current is 5-20 ASF, and the temperature of the electrolyte is 20-30 ℃.
11. A circuit board processing method is characterized in that: the method comprises the following steps:
s1: providing a middle plate (2) with a surface layer conducting layer removed, wherein the middle plate (2) with the surface layer conducting layer removed is manufactured by the surface layer conducting layer removing method in the circuit board processing of claim 10;
s2: and (3) sequentially carrying out conventional film removing, welding preventing, surface treatment and finished product testing processes on the intermediate plate (2) with the surface conducting layer removed, so as to finish the subsequent manufacturing of the required circuit board finished product.
12. A circuit board, characterized in that: the circuit board manufactured by the method for manufacturing the circuit board.
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|---|---|---|---|---|
| JP2014193606A (en) * | 2013-03-01 | 2014-10-09 | Jx Nippon Mining & Metals Corp | Carrier-fitted copper foil, copper-clad laminate sheet using the same, printed wiring board, electronic appliance using the same, and method for manufacturing printed wiring board |
| CN104394665A (en) * | 2014-10-15 | 2015-03-04 | 上海美维电子有限公司 | Manufacturing method of ultrathin printed circuit board, and ultrathin printed circuit board |
| CN106211638A (en) * | 2016-07-26 | 2016-12-07 | 上海美维科技有限公司 | A kind of processing method of ultra-thin multilayer printed circuit board |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014193606A (en) * | 2013-03-01 | 2014-10-09 | Jx Nippon Mining & Metals Corp | Carrier-fitted copper foil, copper-clad laminate sheet using the same, printed wiring board, electronic appliance using the same, and method for manufacturing printed wiring board |
| CN104394665A (en) * | 2014-10-15 | 2015-03-04 | 上海美维电子有限公司 | Manufacturing method of ultrathin printed circuit board, and ultrathin printed circuit board |
| CN106211638A (en) * | 2016-07-26 | 2016-12-07 | 上海美维科技有限公司 | A kind of processing method of ultra-thin multilayer printed circuit board |
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