CN117012752A - Capacitor and method of forming the same - Google Patents

Capacitor and method of forming the same Download PDF

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Publication number
CN117012752A
CN117012752A CN202210453826.8A CN202210453826A CN117012752A CN 117012752 A CN117012752 A CN 117012752A CN 202210453826 A CN202210453826 A CN 202210453826A CN 117012752 A CN117012752 A CN 117012752A
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plate
plug
forming
dielectric layer
capacitor
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熊鹏
张宏
刘继全
倪百兵
杨明
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210453826.8A priority Critical patent/CN117012752A/en
Publication of CN117012752A publication Critical patent/CN117012752A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A capacitor and a method of forming the same, wherein the method of forming includes: providing a substrate; forming a lower electrode plate on the substrate, a first dielectric layer on the lower electrode plate, a middle electrode plate on the first dielectric layer, a second dielectric layer on the middle electrode plate and an upper electrode plate on the second dielectric layer; forming a first through hole penetrating the upper polar plate, the second dielectric layer and the middle polar plate, wherein the bottom of the first through hole is higher than or flush with the top surface of the lower polar plate; forming a second through hole penetrating through the upper polar plate, wherein the bottom of the second through hole is higher than or flush with the top surface of the middle polar plate; forming a first plug in the first through hole and on the surface of the upper polar plate, wherein the first plug is electrically connected with the lower polar plate and the upper polar plate respectively; and forming a second plug in the second through hole, wherein the second plug is electrically connected with the middle polar plate. The capacitor and the forming method thereof simplify the wiring mode of the capacitor and reduce the process cost.

Description

Capacitor and method of forming the same
Technical Field
The invention relates to the technical field of semiconductors, in particular to a capacitor and a forming method thereof.
Background
Capacitive elements are often used as electronic passive devices in integrated circuits. Among them, metal-insulator-metal (MIM) capacitors have good frequency characteristics and electrical characteristics, and thus are widely used. In addition, in semiconductor manufacturing, the compatibility of the metal-insulator-metal capacitor manufacturing process and other interconnection processes is high, and the difficulty and complexity of integration with the CMOS front-end process are reduced.
Conventional metal-insulator-metal capacitors include a lower plate metal, a dielectric layer, and an upper plate metal, thereby forming a sandwich structure with the dielectric layer sandwiched between the two layers of metal. However, in practical manufacturing processes, as devices are increasingly scaled, individual capacitors are limited by feature size and their capacitance is very limited.
Currently, capacitors with three electrode plates are formed by continuing to superimpose a second dielectric layer and a third electrode plate metal on the top electrode plate metal of conventional metal-insulator-metal capacitors, thereby increasing the capacitance density of the device.
However, in the related art, wiring of such a capacitor is complicated, and the cost of the manufacturing process is always high.
Disclosure of Invention
The invention solves the technical problem of providing the capacitor and the forming method thereof, simplifying the wiring mode of the capacitor and reducing the process cost.
In order to solve the technical problems, the technical scheme of the invention provides a capacitor, which comprises a substrate; a lower plate on the substrate, a first dielectric layer on the lower plate, a middle plate on the first dielectric layer, a second dielectric layer on the middle plate, and an upper plate on the second dielectric layer; a first plug electrically connecting the lower plate with the upper plate; and a second plug electrically connected with the middle polar plate.
Optionally, the first plug is located on the surface of the upper electrode plate, in the second dielectric layer and in the middle electrode plate; the second plug is positioned in the upper polar plate.
Correspondingly, the technical scheme of the invention also provides a method for forming the capacitor, which comprises the following steps: providing a substrate; forming a lower electrode plate on the substrate, a first dielectric layer on the lower electrode plate, a middle electrode plate on the first dielectric layer, a second dielectric layer on the middle electrode plate and an upper electrode plate on the second dielectric layer; forming a first through hole penetrating the upper electrode plate, the second dielectric layer and the middle electrode plate; forming a second through hole penetrating through the upper polar plate; forming a first plug in the first through hole and on the surface of the upper polar plate, wherein the first plug is electrically connected with the lower polar plate and the upper polar plate respectively; and forming a second plug in the second through hole, wherein the second plug is electrically connected with the middle polar plate.
Optionally, the substrate includes a base, an underlying dielectric layer on the base, and a first electrical interconnect layer within the underlying dielectric layer.
Optionally, the bottom of the first through hole exposes the surface of the first dielectric layer; the second dielectric layer surface is exposed at the bottom of the second through hole.
Optionally, after forming the first through hole and the second through hole, the method for forming the capacitor further includes: etching the first dielectric layer at the bottom of the first through hole until the surface of the lower polar plate is exposed; and etching the second dielectric layer at the bottom of the second through hole until the surface of the middle polar plate is exposed.
Optionally, the method for forming the first through hole includes: forming a first mask layer on the upper polar plate, wherein part of the surface of the upper polar plate is exposed by the first mask layer; and etching the upper electrode plate, the second dielectric layer and the middle electrode plate by taking the first mask layer as a mask.
Optionally, the bottom of the first through hole exposes the surface of the lower polar plate; the bottom of the second through hole exposes the surface of the middle polar plate.
Optionally, the method for forming the second through hole includes: forming a second mask layer positioned in the first through hole and on the upper polar plate, wherein the second mask layer exposes part of the surface of the upper polar plate at two sides of the first through hole; and etching the upper polar plate by taking the second mask layer as a mask.
Optionally, before forming the first plug and the second plug, the method for forming the capacitor further includes: a third dielectric layer is formed on the bottom plate sidewall, the middle plate sidewall, and the top plate sidewall surface.
Optionally, after the first through hole is formed, the upper polar plate is separated into a first sub polar plate and a second sub polar plate, and the middle polar plate is separated into a third sub polar plate and a fourth sub polar plate.
Optionally, the first plug is respectively communicated with the first sub-polar plate, the second sub-polar plate and the lower polar plate.
Optionally, the first plug comprises a first sub-plug and a second sub-plug which are separated, the first sub-plug is respectively communicated with the first sub-polar plate and the lower polar plate, and the second sub-plug is respectively communicated with the second sub-polar plate and the lower polar plate.
Optionally, the second plug includes a third sub-plug and a fourth sub-plug, the third sub-plug is in communication with the third sub-plate, and the fourth sub-plug is in communication with the fourth sub-plate.
Optionally, the forming method of the first plug and the second plug includes: forming an initial plug material layer positioned in the first through hole, the second through hole and the surface of the upper polar plate; patterning the initial plug material layer to form a first plug located in the first via and on the top plate surface and a second plug located in the second via.
Optionally, the method for forming a capacitor further includes: and forming an interlayer dielectric layer surrounding the first plug and the second plug.
Optionally, after forming the first plug and the second plug, the method further includes: and forming a second electric interconnection layer positioned on the first plug and the second plug, wherein the first plug and the second plug are respectively communicated with the second electric interconnection layer.
Optionally, the width of the first through hole ranges from 0.3 micrometers to 0.5 micrometers.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the capacitor, the formed first plug is respectively communicated with the lower polar plate and the upper polar plate, so that the first plug can be simultaneously used as an electric connection line of the upper polar plate and an electric connection line of the lower polar plate, the process for respectively forming the electric connection lines on the upper polar plate and the lower polar plate is saved, and the wiring space is saved. In addition, the capacitor is provided with three layers of polar plates, but the first plug and the second plug can be formed only through two patterning processes, so that the upper polar plate, the middle polar plate and the lower polar plate are all provided with electric connection wires, and the process cost is saved.
Further, after the first through hole is formed, the upper polar plate is separated into a first sub polar plate and a second sub polar plate, and the first plug is respectively communicated with the first sub polar plate, the second sub polar plate and the lower polar plate, so that the first plug is used as an electric connection line of the first sub polar plate, the second sub polar plate and the lower polar plate, wiring space is saved, the structure of the capacitor is more compact, and capacitance density is improved.
In the capacitor provided by the technical scheme of the invention, the first plug is respectively communicated with the lower polar plate and the upper polar plate, so that the first plug can be simultaneously used as an electric connection line of the upper polar plate and an electric connection line of the lower polar plate, the process of respectively forming the electric connection lines on the upper polar plate and the lower polar plate is saved, and the wiring space is saved.
Drawings
Fig. 1 to 5 are schematic structural views of a forming process of a capacitor according to an embodiment of the present invention.
Detailed Description
As described in the background art, in the prior art, a capacitor having three electrode plates needs to be provided with independent electrical wires on the three electrode plates, so as to achieve the performance of high capacitance density of the capacitor. However, such a capacitor is complicated in wiring, occupies a large wiring space, and the cost of the manufacturing process is always high.
In order to solve the technical problems, the technical scheme of the invention provides a method for forming a capacitor, and the first plug is formed to be respectively communicated with a lower polar plate and an upper polar plate, so that the first plug can be simultaneously used as an electric connection line of the upper polar plate and an electric connection line of the lower polar plate, and wiring space is saved. In addition, the first plug communicated with the lower polar plate and the upper polar plate and the second plug communicated with the middle polar plate can be formed through two patterning processes, so that the process cost is saved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 5 are schematic structural views of a forming process of a capacitor according to an embodiment of the present invention.
Referring to fig. 1, a substrate 100 is provided; a lower plate 101 on the substrate 100, a first dielectric layer 104 on the lower plate 101, a middle plate 102 on the first dielectric layer 104, a second dielectric layer 105 on the middle plate 102, and an upper plate 103 on the second dielectric layer 105 are formed.
The material of the substrate 100 includes silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), and the like. Specifically, in this embodiment, the material of the substrate 100 is silicon.
The substrate 100 includes a base (not shown), an underlying dielectric layer (not shown) on the base, and a first electrical interconnect layer (not shown) within the underlying dielectric layer.
The lower plate 101, the first dielectric layer 104, and the middle plate 102 constitute a first capacitance, and the middle plate 102, the second dielectric layer 105, and the upper plate 103 constitute a second capacitance. Therefore, by stacking the lower plate 101, the middle plate 102 and the upper plate 103 on each other, both the upper surface and the lower surface of the middle plate 102 are utilized, and thus, the capacitor has both the first capacitance and the second capacitance within the same working area, thereby significantly increasing the capacitance density of the device.
Specifically, in this embodiment, the forming method of the lower plate 101, the first dielectric layer 104, the middle plate 102, the second dielectric layer 105, and the upper plate 103 includes: depositing a lower plate material layer (not shown) on the substrate 100; patterning the lower plate material layer to form a lower plate 101; depositing a first layer of dielectric material (not shown) on the lower plate 101; patterning the first dielectric material layer to form a first dielectric layer 104; depositing a layer of center plate material (not shown) over the first dielectric layer 104; patterning the middle plate material layer to form a middle plate 102; depositing a second layer of dielectric material (not shown) on the middle plate 102; patterning the second dielectric material layer to form a second dielectric layer 105; depositing an upper plate material layer (not shown) on the second dielectric layer 105; the top plate 103 material layer is patterned to form the top plate 103.
In this embodiment, the materials of the lower plate 101, the middle plate 102, and the upper plate 103 include metals.
In this embodiment, the materials of the first dielectric layer 104 and the second dielectric layer 105 include silicon oxide or silicon nitride.
Referring to fig. 2, a first through hole 110 is formed through the upper plate 103, the second dielectric layer 105 and the middle plate 102, and the bottom of the first through hole 110 is higher than the top surface of the lower plate 101.
The first through hole 110 provides a space for a first plug to be formed later.
The purpose of the first through hole 110 penetrating the upper plate 103, the second dielectric layer 105 and the middle plate 102 is that, after the first dielectric layer 104 at the bottom of the first through hole 110 is removed, the surface of the upper plate 103 and the surface of the lower plate 101 may be simultaneously exposed by the first through hole 110, so that a first plug formed in the first through hole 110 can be simultaneously electrically connected with the upper plate 103 and the lower plate 101.
In this embodiment, the bottom of the first via hole 110 exposes the surface of the first dielectric layer 104.
Specifically, the method for forming the first through hole 110 includes: forming a first mask layer (not shown) on the upper plate 103, the first mask layer exposing a portion of the upper plate 103 surface; and etching the upper electrode plate 103, the second dielectric layer 105 and the middle electrode plate 102 by taking the first mask layer as a mask until the surface of the first dielectric layer 104 is exposed.
In this embodiment, the process of etching the upper plate 103, the second dielectric layer 105 and the middle plate 102 includes a dry etching process.
In this embodiment, the process of etching the upper plate 103, the second dielectric layer 105 and the middle plate 102 includes: etching the upper electrode plate 103 by using the first mask layer as a mask until the surface of the second dielectric layer 105 is exposed; etching the second dielectric layer 105 by using the first mask layer as a mask until the surface of the middle polar plate 102 is exposed; and etching the middle polar plate 102 by using the first mask layer as a mask and adopting a third etching gas until the surface of the first dielectric layer 104 is exposed.
In this embodiment, the upper plate 103 and the middle plate 102 are made of the same material, and the second dielectric layer 105 is made of a material different from that of the upper plate 103 and the middle plate 102. Therefore, in the process of etching the upper plate 103, the second dielectric layer 105 and the middle plate 102, the first etching gas and the third etching gas are the same, and the second etching gas and the first etching gas and the third etching gas are different.
After forming the first through hole 110, the upper plate 103 is separated into a first sub-plate 103a and a second sub-plate 103b, and the middle plate 102 is separated into a third sub-plate 102a and a fourth sub-plate 102b.
In this embodiment, the width of the first through hole 110 ranges from 0.3 micrometers to 0.5 micrometers. The width of the first through hole 110 refers to the distance between the first sub-plate 103a and the second sub-plate 103b in the direction parallel to the surface of the substrate 100 of the first through hole 110.
The distance between the first and second sub-plates 103a, 103b is the same as the distance between the third and fourth sub-plates 102a, 102b.
Therefore, the distance between the first sub-plate 103a and the second sub-plate 103b and the distance between the third sub-plate 102a and the fourth sub-plate 102b are smaller, so that the capacitor has a more compact structure, the capacitance density is improved, and the working area of the device is further saved.
In another embodiment, the first via bottom is flush with the bottom plate top surface, i.e., the first via bottom exposes the bottom plate surface.
The method for forming the first through hole comprises the following steps: forming a first mask layer on the upper polar plate, wherein part of the surface of the upper polar plate is exposed by the first mask layer; and sequentially etching the upper electrode plate, the second dielectric layer, the middle electrode plate and the first dielectric layer by taking the first mask layer as a mask until the surface of the lower electrode plate is exposed.
In another embodiment, the substrate includes a device region and an edge region. The device region is an effective working region of the capacitor; the edge region is located around the device region and provides mechanical support for the device region.
In the process of forming the first through hole, the first mask layer also exposes the surface of the upper polar plate on the edge area, so that the first through hole is formed, and the upper polar plate, the second dielectric layer, the middle polar plate and the first dielectric layer on the edge area are etched and removed by taking the first mask layer as a mask until the surface of the lower polar plate on the edge area is exposed.
Referring to fig. 3, a second through hole 111 is formed through the upper plate 103, and the bottom of the second through hole 111 is higher than the top surface of the middle plate 102.
The second through hole 111 provides a forming space for a second plug to be formed later, and after the second dielectric layer 105 at the bottom of the second through hole 111 is removed later, the second plug formed in the second through hole 111 can be electrically connected with the middle electrode plate 102.
In this embodiment, the bottom of the second through hole 111 exposes the surface of the middle plate 102.
Specifically, the method for forming the second through hole 111 includes: forming a second mask layer (not shown) in the first through hole 110 and on the upper electrode plate 103, wherein the second mask layer exposes part of the surface of the upper electrode plate 103 at two sides of the first through hole 110; and etching the upper electrode plate 103 by taking the second mask layer as a mask until the surface of the second dielectric layer 105 is exposed.
In another embodiment, the second via bottom is flush with the top surface of the center plate, i.e., the second via bottom exposes the center plate surface.
The method for forming the second through hole comprises the following steps: forming a second mask layer positioned in the first through hole and on the upper polar plate, wherein the second mask layer exposes part of the surface of the upper polar plate at two sides of the first through hole; and sequentially etching the upper electrode plate and the surface of the second dielectric layer by taking the second mask layer as a mask until the surface of the middle electrode plate is exposed.
In another embodiment, the substrate includes a device region and an edge region.
And in the process of forming the first through hole, simultaneously removing the upper electrode plate, the second dielectric layer, the middle electrode plate and the first dielectric layer on the edge area until the surface of the lower electrode plate on the edge area is exposed.
In the process of forming the second through hole, the second mask layer also exposes the surface of the lower electrode plate on the edge area, so that the second through hole is formed, and simultaneously, the second mask layer is used as a mask to continuously etch and remove the lower electrode plate on the edge area until the surface of the edge area is exposed.
Referring to fig. 4, a third dielectric layer 112 is formed on the sidewall of the lower plate 101, the sidewall of the middle plate 102, and the sidewall surface of the upper plate 103; etching the first dielectric layer 104 at the bottom of the first through hole 110 until the surface of the lower electrode plate 101 is exposed; the second dielectric layer 105 at the bottom of the second via 111 is etched until the surface of the middle plate 102 is exposed.
The third dielectric layer 112 is used for protecting the surfaces of the upper plate 103, the middle plate 102 and the lower plate 101 from being polluted by other processes, thereby ensuring the working effect of the capacitor.
The forming process of the third dielectric layer 112 includes: depositing an initial dielectric layer (not shown) on the sidewalls and top surfaces of the upper plate 103, middle plate 102, and lower plate 101; the initial dielectric layer on the surface of the upper plate 103, the initial dielectric layer and the first dielectric layer 104 in the first through hole 110, and the initial dielectric layer and the second dielectric layer 105 in the second through hole 111 are etched back and removed, so that the first through hole 110 exposes the surface of the lower plate 101, and the second through hole 111 exposes the surface of the middle plate 102.
In this embodiment, the materials of the first dielectric layer 104, the second dielectric layer 105, and the third dielectric layer 112 are the same.
Therefore, after the initial dielectric layer is formed, the initial dielectric layer on the surface of the upper plate 103, the initial dielectric layer and the first dielectric layer 104 in the first via hole 110, and the initial dielectric layer and the second dielectric layer 105 in the second via hole 111 may be etched at the same time by the same process, thereby making the process steps simpler. Specifically, the etching process includes an anisotropic dry etching process.
Referring to fig. 5, a first plug 120 is formed in the first through hole 110 and on the surface of the upper electrode plate 103, and the first plug 120 is electrically connected to the lower electrode plate 101 and the upper electrode plate 103 respectively; a second plug (not shown) is formed in the second through hole 111, and the second plug is electrically connected to the middle plate 102.
The first plug 120 and the second plug connect the upper electrode plate 103, the middle electrode plate 102, and the lower electrode plate 101 to the second electrical interconnection layer 131 formed later, so that a voltage is applied to the upper electrode plate 103, the middle electrode plate 102, and the lower electrode plate 101 to make the first capacitor formed by the lower electrode plate 101, the first dielectric layer 104, and the middle electrode plate 102, the second dielectric layer 105, and the upper electrode plate 103 function as a second capacitor.
Because the formed first plug 120 is respectively communicated with the lower electrode plate 101 and the upper electrode plate 103, the first plug 120 can be simultaneously used as an electric connection line of the upper electrode plate 103 and an electric connection line of the lower electrode plate 101, so that the process of respectively forming independent electric connection lines on the upper electrode plate 103 and the lower electrode plate 101 is saved, and the wiring space is saved. In addition, the capacitor has three layers of polar plates, but because the capacitor has a wiring structure, the first plug 120 and the second plug 121 can be formed only through two patterning processes as shown in fig. 2 and 3, compared with the situation that the upper polar plate 103, the middle polar plate 102 and the lower polar plate 101 are respectively provided with independent electric connection wires, the forming process of the first plug 120 and the second plug 121 in the embodiment simplifies the patterning times, saves the forming times of a mask layer in the patterning process, and saves the process cost.
In this embodiment, the first plug 120 is respectively connected to the first sub-plate 103a, the second sub-plate 103b and the lower plate 101, so that the first plug 120 is used as an electrical connection line between the first sub-plate 103a, the second sub-plate 103b and the lower plate 101, which further saves the wiring space, and ensures that the distance between the first sub-plate 103a and the second sub-plate 103b is smaller, thereby making the capacitor more compact, improving the capacitance density, saving the working area of the device, and reducing the device structure.
In addition, since the electrical connection lines of the first sub-plate 103a, the second sub-plate 103b and the lower plate 101 are all the first plugs 120, the area of the second electrical interconnection layer 131 formed on the first plugs 120 is further reduced, and the process cost is saved.
In the present embodiment, the distance between the first sub-plate 103a and the second sub-plate 103b is in the range of 0.3 micrometers to 0.5 micrometers.
In another embodiment, the first plug includes a first sub-plug and a second sub-plug, the first sub-plug is respectively communicated with the first sub-pole plate and the lower pole plate, and the second sub-plug is respectively communicated with the second sub-pole plate and the lower pole plate, so that flexibility of wiring is considered under the condition of saving a certain wiring space.
In this embodiment, the second plug includes a third sub-plug 121a and a fourth sub-plug 121b, the third sub-plug 121a is in communication with the third sub-plate 102a, and the fourth sub-plug 121b is in communication with the fourth sub-plate 102b.
Specifically, the method for forming the first plug 120 and the second plug includes: forming an initial plug material layer (not shown) in the first through hole 110, in the second through hole 111 and on the surface of the upper plate 103; the initial plug material layer is patterned to form a first plug 120 within the first via 110 and on the surface of the top plate 103, and a second plug within the second via 111.
After forming the first and second plugs 120 and 120, an interlayer dielectric layer (not shown) is formed to surround the first and second plugs.
In another embodiment, an interlayer dielectric layer positioned on the surfaces of the upper polar plate, the middle polar plate and the lower polar plate can be formed first; then, forming a through hole in the interlayer dielectric layer; a first plug, and a second plug are formed in the through hole.
In this embodiment, a second electrical interconnection layer 131 is formed on the first plug 120, the second plug, and the interlayer dielectric layer, and the first plug 120 and the second plug are respectively in communication with the second electrical interconnection layer 131.
In this embodiment, a portion of the second electrical interconnect layer 131 is also in communication with a first electrical interconnect layer (not shown) within the substrate 100.
Correspondingly, the embodiment of the invention also provides a capacitor formed by adopting the method.
With continued reference to fig. 5, the capacitor includes: a substrate 100; a lower plate 101 on the substrate 100, a first dielectric layer 104 on the lower plate 101, a middle plate 102 on the first dielectric layer 104, a second dielectric layer 105 on the middle plate 102, and an upper plate 103 on the second dielectric layer 105; a first plug 120 electrically connecting the lower plate 101 with the upper plate 103; a second plug (not shown) electrically connected to the center plate 102.
In this embodiment, the first plug 120 is located on the surface of the upper plate 103, in the second dielectric layer 105, and in the middle plate 102; the second plug is located within the upper plate 103.
Because the first plug 120 is respectively connected to the lower plate 101 and the upper plate 103, the first plug 120 can be used as an electrical connection line of the upper plate 103 and an electrical connection line of the lower plate 101 at the same time, thereby saving the process of forming independent electrical connection lines on the upper plate 103 and the lower plate 101 respectively, saving the wiring space and reducing the size of the device.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (18)

1. A capacitor, comprising:
a substrate;
a lower plate on the substrate, a first dielectric layer on the lower plate, a middle plate on the first dielectric layer, a second dielectric layer on the middle plate, and an upper plate on the second dielectric layer;
a first plug electrically connecting the lower plate with the upper plate;
and a second plug electrically connected with the middle polar plate.
2. The capacitor of claim 1 wherein the first plug is located on the top plate surface, in the second dielectric layer, and in the middle plate; the second plug is positioned in the upper polar plate.
3. A method of forming a capacitor, comprising:
providing a substrate;
forming a lower electrode plate on the substrate, a first dielectric layer on the lower electrode plate, a middle electrode plate on the first dielectric layer, a second dielectric layer on the middle electrode plate and an upper electrode plate on the second dielectric layer;
forming a first through hole penetrating the upper electrode plate, the second dielectric layer and the middle electrode plate;
forming a second through hole penetrating through the upper polar plate;
forming a first plug in the first through hole and on the surface of the upper polar plate, wherein the first plug is electrically connected with the lower polar plate and the upper polar plate respectively;
and forming a second plug in the second through hole, wherein the second plug is electrically connected with the middle polar plate.
4. The method of forming a capacitor of claim 3 wherein said substrate comprises a base, an underlying dielectric layer on said base, and a first electrical interconnect layer in said underlying dielectric layer.
5. The method of forming a capacitor of claim 3 wherein a bottom of said first via exposes a surface of said first dielectric layer; the second dielectric layer surface is exposed at the bottom of the second through hole.
6. The method of forming a capacitor of claim 5, further comprising, after forming the first via, the second via: etching the first dielectric layer at the bottom of the first through hole until the surface of the lower polar plate is exposed; and etching the second dielectric layer at the bottom of the second through hole until the surface of the middle polar plate is exposed.
7. The method of forming a capacitor of claim 3, wherein the method of forming the first via comprises: forming a first mask layer on the upper polar plate, wherein part of the surface of the upper polar plate is exposed by the first mask layer; and etching the upper electrode plate, the second dielectric layer and the middle electrode plate by taking the first mask layer as a mask.
8. The method of forming a capacitor of claim 3 wherein a bottom of said first via exposes a surface of said lower plate; the bottom of the second through hole exposes the surface of the middle polar plate.
9. The method of forming a capacitor of claim 3, wherein the method of forming the second via comprises: forming a second mask layer positioned in the first through hole and on the upper polar plate, wherein the second mask layer exposes part of the surface of the upper polar plate at two sides of the first through hole; and etching the upper polar plate by taking the second mask layer as a mask.
10. The method of forming a capacitor of claim 3, further comprising, prior to forming the first plug, the second plug: a third dielectric layer is formed on the bottom plate sidewall, the middle plate sidewall, and the top plate sidewall surface.
11. The method of forming a capacitor of claim 3 wherein after forming said first via, said upper plate is separated into a first sub-plate and a second sub-plate and said middle plate is separated into a third sub-plate and a fourth sub-plate.
12. The method of forming a capacitor of claim 11 wherein said first plug is in communication with a first sub-plate, a second sub-plate and a lower plate, respectively.
13. The method of forming a capacitor of claim 11 wherein said first plug comprises a first discrete sub-plug in communication with said first sub-plate and said lower plate, respectively, and a second discrete sub-plug in communication with said second sub-plate and said lower plate, respectively.
14. The method of forming a capacitor of claim 11 wherein said second plug comprises a third sub-plug in communication with a third sub-plate and a fourth sub-plug in communication with a fourth sub-plate.
15. The method of forming a capacitor of claim 3, wherein the method of forming the first plug and the second plug comprises: forming an initial plug material layer positioned in the first through hole, the second through hole and the surface of the upper polar plate; patterning the initial plug material layer to form a first plug located in the first via and on the top plate surface and a second plug located in the second via.
16. The method of forming a capacitor of claim 3, further comprising: and forming an interlayer dielectric layer surrounding the first plug and the second plug.
17. The method of forming a capacitor of claim 3, further comprising, after forming the first plug and the second plug: and forming a second electric interconnection layer positioned on the first plug and the second plug, wherein the first plug and the second plug are respectively communicated with the second electric interconnection layer.
18. The method of forming a capacitor of claim 3, wherein the first via has a width in the range of 0.3 microns to 0.5 microns.
CN202210453826.8A 2022-04-27 2022-04-27 Capacitor and method of forming the same Pending CN117012752A (en)

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