CN116995102B - 一种低温漂齐纳器件及其制造方法 - Google Patents

一种低温漂齐纳器件及其制造方法 Download PDF

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CN116995102B
CN116995102B CN202311251906.6A CN202311251906A CN116995102B CN 116995102 B CN116995102 B CN 116995102B CN 202311251906 A CN202311251906 A CN 202311251906A CN 116995102 B CN116995102 B CN 116995102B
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杜一颖
崔力铸
邵帅
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Chengdu Yichuang Microelectronics Co ltd
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Abstract

本发明涉及一种低温漂齐纳器件及其制造方法，属于半导体器件技术领域，它包括P型硅片衬底，以及位于P型硅片衬底内部的P型齐纳扩散区、N型深掩埋击穿区、阴极欧姆接触区和阳极P+接触区；阳极P+接触区位于P型硅片衬底的两侧，且不与N型深掩埋击穿区接触，所述阴极欧姆接触区位于两个阳极P+接触区的中间位置，所述N型深掩埋击穿区位于阴极欧姆接触区的下方，所述P型齐纳扩散区位于N型深掩埋击穿区的下方，且与N型深掩埋击穿区相接触形成PN结。本发明将掩埋击穿区和埋层融合成N型深掩埋击穿区，这样N型深掩埋击穿区版图开窗面积比P型齐纳扩散区大，可以极大减小掩埋击穿区注入难度。

Description

一种低温漂齐纳器件及其制造方法
技术领域
本发明涉及半导体器件技术领域，尤其涉及一种低温漂齐纳器件及其制造方法。
背景技术
基准电压源已作为半导体集成电路中不可缺少的基本模块，其广泛用于放大器、模数转换器、数模转换器、射频、传感器和电源管理等芯片中。传统的基准电压源包括齐纳基准、掩埋齐纳基准、XFET 基准和带隙基准。齐纳基准源是利用齐纳二级管反向击穿来实现稳压输出，只需单个器件即可实现，无需电路设计，相比其他基准源更加简单。
温漂指的是稳压源输出电压随温度变化而变化，而低温漂或零温漂是指稳压源输出电压受环境温度影响小或根本不受环境温度影响；随着半导体技术和便携式电子、车载电子产品的发展，对低温漂、高精度的基准电压源的需求大大增加；实际上相比电压源的绝对精度，温度漂移可能是更重要的问题，在可能的情况下，选择基准电压源应该注重温漂系数，以便能在芯片工作温度范围内保持电压基准源的精度。
传统齐纳二极管的击穿发生在硅表面层，由于硅芯片表层与其内部相比有更多的杂质、晶体缺陷和机械应力，容易受到表面氧化层中迁移电荷以及外界环境的影响，所以表层齐纳二极管的噪声较大、长期稳定性差、温漂系数大。为了克服上述缺点，避免表面击穿，于是出现了更具优势的嵌入式掩埋齐纳二极管结构。相比传统表面型齐纳二极管，掩埋齐纳二极管可以使噪声和温漂性能显著提高。但掩埋齐纳二极管需要新增埋层和掩埋击穿区，需要精准控制掩埋击穿区域的注入，工艺难度较大。而且掩埋击穿区仅在齐纳扩散区两侧击穿，中间平行平面结大部分区域没有击穿走电流，对版图面积是一种浪费。
发明内容
本发明的目的在于克服现有技术的缺点，提供了一种低温漂齐纳器件及其制造方法，解决了现有齐纳二极管存在的问题。
本发明的目的通过以下技术方案来实现：一种低温漂齐纳器件，所述器件包括P型硅片衬底，以及位于P型硅片衬底内部的P型齐纳扩散区、N型深掩埋击穿区、阴极欧姆接触区和阳极P+接触区；
所述阳极P+接触区位于P型硅片衬底的两侧，且不与N型深掩埋击穿区接触，所述阴极欧姆接触区位于两个阳极P+接触区的中间位置，所述N型深掩埋击穿区位于阴极欧姆接触区的下方，所述P型齐纳扩散区位于N型深掩埋击穿区的下方，且与N型深掩埋击穿区相接触形成PN结。
所述N型深掩埋击穿区包括一个完全将阴极欧姆接触区包裹在内的整体结构，且N型深掩埋击穿区的横向宽度大于P型齐纳扩散区的横向宽度。
所述N型深掩埋击穿区包括三个分离的子区域，其中两个子区域位于阴极欧姆接触区的两侧且与阴极欧姆接触区接触，最后一个子区域位于阴极欧姆接触区和P型齐纳扩散区之间，且与阴极欧姆接触区和P型齐纳扩散区接触。
其中两个子区域的纵向长度大于阴极欧姆接触区的纵向长度，最后一个子区域的横向宽度大于P型齐纳扩散区的横向宽度且小于阴极欧姆接触区的横向宽度。
所述阴极欧姆接触区的掺杂类型包括N型掺杂或者P型掺杂。
一种低温漂齐纳器件制造方法，所述制造方法包括：
S1、在P型硅片衬底上进行掺杂注入并退火，形成阴极欧姆接触区和阳极P+接触区；
S2、在P型硅片衬底上进行N型深掩埋注入并退火，形成N型深掩埋击穿区，且N型深掩埋击穿区的深度大于阴极欧姆接触区的深度；
S3、在P型硅片衬底上进行P型齐纳注入并退火，形成P型齐纳扩散区，P型齐纳扩散区与N型深掩埋击穿区接触形成PN结，且P型齐纳扩散区的横向宽度小于N型深掩埋击穿区的横向宽度。
所述阴极欧姆接触区的掺杂类型包括N型掺杂或者P型掺杂。
所述阳极P+接触区不与N型深掩埋击穿区接触，所述阴极欧姆接触区与N型深掩埋击穿区接触，且不与P型齐纳扩散区相接触。
本发明具有以下优点：一种低温漂齐纳器件及其制造方法，将掩埋击穿区和埋层融合成N型深掩埋击穿区，这样N型深掩埋击穿区版图开窗面积比P型齐纳扩散区大，可以极大减小掩埋击穿区注入难度；掩埋击穿区和齐纳扩散区所形成的平行平面结均可以产生击穿电流，充分利用版图面积，提高齐纳稳压基准源性能。
附图说明
图1为本发明实施例1的结构示意图；
图2为本发明实施例2的结构示意图；
图中：1-P型硅片衬底，2-阴极欧姆接触区，3-N型深掩埋击穿区，4-P型齐纳扩散区，5-阳极P+接触区。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。因此，以下结合附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的保护范围，而是仅仅表示本申请的选定实施例。基于本申请的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本申请保护的范围。下面结合附图对本发明做进一步的描述。
实施例1，本发明涉及一种低温漂齐纳器件，将掩埋击穿区和埋层融合成N型深掩埋击穿区3，这样N型深掩埋击穿区3版图开窗面积比P型齐纳扩散区4大，可以极大减小掩埋击穿区注入难度；同时也简化了制造流程，从原先需要分别做埋层和掩埋击穿区，变成只需做一次N型深掩埋击穿区。而且N型深掩埋击穿区3和P型齐纳扩散区4所形成平行平面结均可以产生击穿电流，与嵌入式掩埋齐纳二极管相比增大了击穿面积，可以在相同版图面积下获得性能更优的齐纳稳压基准源。
如图1所示，它包括P型硅片衬底1，以及位于P型硅片衬底1内部的P型齐纳扩散区4、N型深掩埋击穿区3、阴极欧姆接触区2和阳极P+接触区5；
其中，阳极P+接触区5位于P型硅片衬底1的两侧，且不与N型深掩埋击穿区3接触，所述阴极欧姆接触区2位于两个阳极P+接触区5的中间位置，所述N型深掩埋击穿区3位于阴极欧姆接触区2的下方，所述P型齐纳扩散区4位于N型深掩埋击穿区3的下方，且与N型深掩埋击穿区3相接触形成PN结。
N型深掩埋击穿区3包括一个完全将阴极欧姆接触区2包裹在内的整体结构，且N型深掩埋击穿区3的横向宽度大于P型齐纳扩散区4的横向宽度。
在本实施例中，在PN结重掺杂条件下，PN结将发生齐纳击穿。齐纳击穿的物理机理是：P 区价带与 N 区导带相距近，N 区导带底部低于 P 区价带顶部，反偏电压可以轻易地使 P 区价带中的电子直接隧穿到 N 区的导带中，形成击穿电流。随着温度升高，电子热运动加剧，较小的反向电压就能使电子穿过势垒，所以温度上升，齐纳击穿电压下降。即：齐纳击穿的击穿稳压值是负温度系数的。
在PN结掺杂浓度较轻的条件下，PN结将发生雪崩击穿。雪崩击穿的物理机理是：在高反偏电压下，高能量的电子撞击其他电子导致电子脱离了共价键束缚，从而使载流子数量成倍增加。随着温度增加使晶格原子振动幅度加大，平均自由程减小，因此需要更高的电场来加速电子，所以雪崩击穿稳压值是正温度系数的。
因此可以通过调节PN结两侧N型、P型的掺杂浓度，让PN结的击穿调节为介于齐纳击穿和雪崩击穿之间，进而实现两种物理机理的温度补偿，降低温漂系数。在本实施例中，可以通过调节P型齐纳扩散区4和N型深掩埋击穿区3的掺杂浓度，使得PN结同时发生齐纳击穿和雪崩击穿，最终实现低温漂或零温漂。
,实施例2，如图2所示，本实施例与实施例1的区别在于N型深掩埋击穿区3，本实施例中N型深掩埋击穿区3包括三个分离的子区域，其中两个子区域位于阴极欧姆接触区2的两侧且与阴极欧姆接触区2接触，最后一个子区域位于阴极欧姆接触区2和P型齐纳扩散区4之间，且与阴极欧姆接触区2和P型齐纳扩散区4接触。
其中两个子区域的纵向长度大于阴极欧姆接触区2的纵向长度，最后一个子区域的横向宽度大于P型齐纳扩散区4的横向宽度且小于阴极欧姆接触区2的横向宽度。
,实施例3，本发明还涉及一种低温漂齐纳器件制造方法，所述制造方法包括：
S1、在P型硅片衬底,1上进行掺杂注入并退火，形成阴极欧姆接触区2和阳极P+接触区5；
S2、在P型硅片衬底1上进行N型深掩埋注入并退火，形成N型深掩埋击穿区3，且N型深掩埋击穿区3的深度大于阴极欧姆接触区2的深度；
S3、在P型硅片衬底1上进行P型齐纳注入并退火，形成P型齐纳扩散区4，P型齐纳扩散区4与N型深掩埋击穿区3接触形成PN结，且P型齐纳扩散区4的横向宽度小于N型深掩埋击穿区3的横向宽度。
其中，阳极P+接触区5不与N型深掩埋击穿区3接触，所述阴极欧姆接触区2与N型深掩埋击穿区3接触，且不与P型齐纳扩散区4相接触。
本发明阴极欧姆接触区2的掺杂类型包括N型掺杂或者P型掺杂。器件中各掺杂类型相应变为相反的掺杂，即P型掺杂变为N型掺杂的同时N型掺杂变为P型掺杂。
以上所述仅是本发明的优选实施方式，应当理解本发明并非局限于本文所披露的形式，不应看作是对其他实施例的排除，而可用于各种其他组合、修改和完善，并能够在本文所述构想范围内，通过上述教导或相关领域的技术或知识进行改动。而本领域人员所进行的改动和变化不脱离本发明的精神和范围，则都应在本发明所附权利要求的保护范围内。

Claims (6)

1.一种低温漂齐纳器件，其特征在于：所述器件包括P型硅片衬底（1），以及位于P型硅片衬底（1）内部的P型齐纳扩散区（4）、N型深掩埋击穿区（3）、阴极欧姆接触区（2）和阳极P+接触区（5）；
所述阳极P+接触区（5）位于P型硅片衬底（1）的两侧，且不与N型深掩埋击穿区（3）接触，所述阴极欧姆接触区（2）位于两个阳极P+接触区（5）的中间位置，所述N型深掩埋击穿区（3）位于阴极欧姆接触区（2）的下方，所述P型齐纳扩散区（4）位于N型深掩埋击穿区（3）的下方，且与N型深掩埋击穿区（3）相接触形成PN结；
所述N型深掩埋击穿区（3）包括三个分离的子区域，其中两个子区域位于阴极欧姆接触区（2）的两侧且与阴极欧姆接触区（2）接触，最后一个子区域位于阴极欧姆接触区（2）和P型齐纳扩散区（4）之间，且与阴极欧姆接触区（2）和P型齐纳扩散区（4）接触。
2.根据权利要求1所述的一种低温漂齐纳器件，其特征在于：其中两个子区域的纵向长度大于阴极欧姆接触区（2）的纵向长度，最后一个子区域的横向宽度大于P型齐纳扩散区（4）的横向宽度且小于阴极欧姆接触区（2）的横向宽度。
3.根据权利要求1所述的一种低温漂齐纳器件，其特征在于：所述阴极欧姆接触区（2）的掺杂类型包括N型掺杂。
4.一种低温漂齐纳器件制造方法，其特征在于：所述制造方法包括：
S1、在P型硅片衬底（1）上进行掺杂注入并退火，形成阴极欧姆接触区（2）和阳极P+接触区（5）；
S2、在P型硅片衬底（1）上进行N型深掩埋注入并退火，形成N型深掩埋击穿区（3），且N型深掩埋击穿区（3）的深度大于阴极欧姆接触区（2）的深度；
S3、在P型硅片衬底（1）上进行P型齐纳注入并退火，形成P型齐纳扩散区（4），P型齐纳扩散区（4）与N型深掩埋击穿区（3）接触形成PN结，且P型齐纳扩散区（4）的横向宽度小于N型深掩埋击穿区（3）的横向宽度；
所述N型深掩埋击穿区（3）包括三个分离的子区域，其中两个子区域位于阴极欧姆接触区（2）的两侧且与阴极欧姆接触区（2）接触，最后一个子区域位于阴极欧姆接触区（2）和P型齐纳扩散区（4）之间，且与阴极欧姆接触区（2）和P型齐纳扩散区（4）接触。
5.根据权利要求4所述的一种低温漂齐纳器件制造方法，其特征在于：所述阴极欧姆接触区（2）的掺杂类型包括N型掺杂。
6.根据权利要求4所述的一种低温漂齐纳器件制造方法，其特征在于：所述阳极P+接触区（5）不与N型深掩埋击穿区（3）接触，所述阴极欧姆接触区（2）与N型深掩埋击穿区（3）接触，且不与P型齐纳扩散区（4）相接触。
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