CN116978930A - Gallium nitride junction barrier Schottky diode with novel junction material and manufacturing method - Google Patents

Gallium nitride junction barrier Schottky diode with novel junction material and manufacturing method Download PDF

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CN116978930A
CN116978930A CN202210422374.7A CN202210422374A CN116978930A CN 116978930 A CN116978930 A CN 116978930A CN 202210422374 A CN202210422374 A CN 202210422374A CN 116978930 A CN116978930 A CN 116978930A
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gallium nitride
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field plate
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郭晋亮
马鹏飞
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Tuoer Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

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Abstract

The application discloses a gallium nitride junction barrier Schottky diode with novel junction materials and a manufacturing method thereof. The gallium nitride junction barrier Schottky diode comprises an ohmic cathode metal layer (4), an N+ gallium nitride substrate layer (1), an N-gallium nitride epitaxial layer (2), a P-type junction layer (3) and a Schottky anode metal layer (5) from bottom to top, wherein a first passivation medium layer (6) is arranged above two ends of the Schottky anode metal layer (5); a first metal field plate layer (7) is arranged above the Schottky anode metal layer (5) and the first passivation dielectric layer (6); a second passivation medium layer (8) is arranged above the two ends of the first metal field plate layer (7); a second metal field plate layer (9) is arranged above the first metal field plate layer (7) and the second passivation medium layer (8). The application increases the reverse breakdown voltage of the gallium nitride junction barrier Schottky diode, reduces the reverse leakage of the gallium nitride junction barrier Schottky diode, and can be used for high-frequency high-power electronic equipment.

Description

Gallium nitride junction barrier Schottky diode with novel junction material and manufacturing method
Technical Field
The application belongs to the technical field of microelectronics, and particularly relates to a gallium nitride junction barrier Schottky diode and a manufacturing method thereof, which can be used for manufacturing various high-power electronic devices.
Background
Gallium nitride power devices are attracting rapid development in the application field of power devices due to the characteristics of high breakdown, high mobility, high frequency, high efficiency and the like. Compared with the traditional material, the Schottky diode prepared from the gallium nitride material has high reliability and stability, so that the device performance of the Schottky diode can be better exerted under severe working conditions such as high power, high temperature and the like. The forward and reverse working principle of the traditional vertical gallium nitride Schottky diode is that the change of barrier height is generated when metal and semiconductor are contacted, but the reverse voltage-withstanding characteristic is not outstanding, so that the actual breakdown voltage has a certain deviation from the theoretical value. To increase its breakdown voltage, reduce reverse leakage effects, junction barrier schottky diode structures are used.
With the development of the integrated circuit industry, the requirements of high-power and high-frequency devices are increasingly demanded at the present stage, and the performance of the power devices directly determines the quality and efficiency of products. Taking a diode as an example, the device is required to have the capability of quick on and off and the excellent performance of pressure resistance and high temperature resistance under the working environment, and the forward and reverse characteristics of the diode are particularly important. In addition, the reduction of reverse electric leakage achieves the aim of saving energy and reducing consumption while improving the efficiency of the product.
The structure of the conventional junction barrier Schottky diode is shown in fig. 1, and comprises an ohmic cathode metal layer 4, an N+ gallium nitride substrate layer 1 and an N-gallium nitride epitaxial layer 2 from bottom to top, wherein a P-type junction layer 3 is arranged in the N-gallium nitride epitaxial layer 2, and a Schottky anode metal layer 5 is arranged on the N-gallium nitride epitaxial layer 2. The current research reports about the gallium nitride junction barrier Schottky diode are relatively few, so the gallium nitride junction barrier Schottky diode has great research value. However, the existing junction barrier Schottky diode structure has no protection of a terminal structure, so that the reverse performance of the device is not outstanding enough. In addition, the P-type junction of the existing structure is made of homogeneous materials, so that the depletion degree is not high when the device works reversely, and the leakage current is larger.
Disclosure of Invention
The application aims to provide a gallium nitride junction barrier Schottky diode with an inclined field plate and a manufacturing method thereof, so as to effectively increase reverse breakdown voltage of the gallium nitride diode, reduce leakage current and improve device performance.
The first aspect of the embodiment of the application provides a gallium nitride junction barrier Schottky diode with a novel junction material, which comprises an ohmic cathode metal layer (4), an N+ gallium nitride substrate layer (1), an N-gallium nitride epitaxial layer (2), a P-type junction layer (3) and a Schottky anode metal layer (5) from bottom to top, wherein a first passivation medium layer (6) is arranged above two opposite ends of the Schottky anode metal layer (5); a first metal field plate layer (7) is arranged above the Schottky anode metal layer (5) and the first passivation dielectric layer (6); a second passivation medium layer (8) is arranged above the two ends of the first metal field plate layer (7); a second metal field plate layer (9) is arranged above the first metal field plate layer (7) and the second passivation medium layer (8).
Further, the thickness of the N-gallium nitride epitaxial layer (2) is 3-10 μm, and the carrier concentration range is 1E15cm -3 ～1E16cm -3 The carrier concentration of the N+ gallium nitride substrate layer (1) is 1E17cm -3 ～1E18cm -3 。
Furthermore, the P-type junction layer (3) is made of P-type cuprous oxide material, and the junction depth is 300-500 nm.
Further, the dielectric materials used for the first passivation dielectric layer (6) and the second passivation dielectric layer (8) are SiO 2 、Al 2 O 3 、Si 3 N 4 The thickness of any one of the first passivation dielectric layer (6) and the second passivation dielectric layer (8) is 50 nm-200 nm.
Further, the first metal field plate layer (7) and the second metal field plate layer (9) are of a double-layer inclined field plate structure, the adopted material is Ti/Au or Au, and the thickness of any layer of the first metal field plate layer (7) and the second metal field plate layer (9) is 50-200 nm.
Further, the ohmic cathode metal layer (1) is formed by adopting one material of Ti, al, ni, au and Pt metal to form a single layer or multiple layers of materials;
the Schottky anode metal layer (5) is formed by adopting one material of Ni, au and W to form a single layer or multiple layers of materials to form multiple layers.
The second aspect of the embodiment of the application provides a manufacturing method of a gallium nitride junction barrier schottky diode with a novel junction material, comprising the following steps:
1) Forming a pattern on the lower surface of the N+ gallium nitride substrate layer (1) by adopting one-time photoetching on an epitaxial wafer sequentially comprising the N+ gallium nitride substrate layer (1) and the N-gallium nitride epitaxial layer (2) from bottom to top, growing ohmic cathode metal in the pattern area by adopting an electron beam evaporation process, and performing thermal annealing treatment to form an ohmic cathode metal layer (4);
2) Forming a pattern on the N-gallium nitride epitaxial layer (2) by adopting secondary photoetching, and then adopting a reactive ion etching process to etch the whole sample downwards to form a plurality of interdigital grooves;
3) A P-type cuprous oxide film grows in the interdigital groove on the N-gallium nitride epitaxial layer (2) by adopting sputtering or other common film preparation processes to form a P-type junction layer (3);
4) Forming a pattern on the N-gallium nitride epitaxial layer (2) by adopting three times of photoetching, growing a Schottky anode metal layer (5) in a pattern area by adopting an electron beam evaporation process, and carrying out thermal annealing treatment;
5) Forming patterns at the two opposite ends of the Schottky anode metal layer (5) by four times of photoetching, and etching the pattern areas below the surface of the N-gallium nitride epitaxial layer (2) by adopting a buffer oxide etching process, wherein the etched wall surface is an inclined wall surface;
6) Depositing a first passivation dielectric layer (6) on the whole sample wafer by adopting a chemical vapor deposition process;
7) Forming a pattern on the first passivation dielectric layer (6) by adopting five times of photoetching, and then adopting a reactive ion etching process to open holes with the depth of 50-200 nm in a pattern area;
8) Adopting an electron beam evaporation process to grow a first metal field plate layer (7) with the thickness of 50-200 nm in a hole on the upper surface of the whole sample wafer;
9) A second passivation dielectric layer (8) is formed on the first metal field plate layer (7) by adopting a plasma enhanced chemical vapor deposition process;
10 Forming a pattern on the second passivation dielectric layer (8) by adopting six times of photoetching, and then adopting an etching process to open holes with the depth of 50-200 nm in the pattern area;
11 And (3) growing a second metal field plate layer (9) with the thickness of 50-200 nm on the upper surface of the whole sample wafer by adopting an electron beam evaporation process to obtain the gallium nitride junction barrier Schottky diode.
Further, the process conditions of the reactive ion etching process in step 2) are as follows:
reaction chamber pressure: 5mtorr of the total number of the cells,
reaction chamber gas: cl 2 With BCl 3 ，
Reaction chamber gas flow rate ratio: cl 2 ：BCl 3 ＝75sccm：30sccm，
An RF radio frequency source: 150W-200W.
Further, the process conditions for the buffer oxide etching in step 5) are as follows:
reaction chamber pressure: 5mtorr of the total number of the cells,
reaction chamber gas: cl 2 With BCl 3 ，
Reaction chamber gas flow rate ratio: cl 2 ：BCl 3 ＝75sccm：30sccm，
An RF radio frequency source: 150W-200W.
Further, the process conditions for enhanced chemical vapor deposition employed in steps 7) and 9) are as follows:
reaction chamber pressure: 2000mtorr of the total number of the pieces of the fiber,
reaction chamber gas: siH (SiH) 4 、N 2 O、N 2 The three kinds of gases are used for generating the air,
reaction chamber gas flow rate ratio: siH (SiH) 4 ：N 2 O：N 2 ＝40sccm：710sccm：180sccm，
Reaction chamber temperature: 320-370 ℃,
an RF radio frequency source: 20W-30W.
Further, the process conditions for electron beam evaporation in steps 8) and 11) are as follows:
working vacuum: 5E-4Pa of the pressure of the liquid,
reaction chamber gas: ti and Au are mixed together,
evaporation rate: the wavelength of the light is 0.1nm/s,
evaporation power: 30W-40W.
Compared with the prior art, the embodiment of the application has the beneficial effects that:
firstly, the P-type junction layer adopts the P-type cuprous oxide material, so that when the device works in the reverse direction, the formed depletion region is wider, the depletion effect is stronger, and the reverse leakage current can be reduced;
second, because the double-layer inclined field plate structure is additionally arranged on the Schottky anode metal, the strong electric field at the edge of the Schottky anode metal of the device is transferred to the metal field plate, the field intensity at the edge of the Schottky anode metal is reduced, the breakdown voltage is further increased, and the device performance is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a conventional GaN junction barrier Schottky diode;
FIG. 2 is a schematic cross-sectional view of a GaN junction barrier Schottky diode having a novel junction material in accordance with the present application;
fig. 3 is a flow chart illustrating the fabrication of the schottky diode of fig. 2 according to the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Fig. 2 is a schematic diagram of a gan junction barrier schottky diode according to the present application, which includes an ohmic cathode metal 4, an n+ gan substrate layer 1, an n-gan epitaxial layer 2, a p-type junction layer 3, an ohmic cathode metal layer 4, a schottky anode metal 5, a first passivation dielectric layer 6, a first metal field plate layer 7, a second passivation dielectric layer 8, and a second metal field plate layer 9.
Wherein: the ohmic cathode metal layer 4 adopts one material of Ti, al, ni, au and Pt metal to form a single layer or multiple materials to form multiple layers; the carrier concentration of the N+ gallium nitride substrate layer 1 is 10E17cm -3 ～10E18cm -3 Which is located on top of the ohmic cathode metal layer 4; the thickness of the N-gallium nitride epitaxial layer 2 is 3-10 mu m, and the carrier concentration is 10E15cm -3 ～10E16cm -3 Which is located on top of the n+ gallium nitride substrate layer 2; the P-type junction layer 3 is integrated in the N-gallium nitride epitaxial layer 2, and the junction depth is 300 nm-500 nm; the Schottky anode metal layer 5 is positioned above the N-gallium nitride epitaxial layer 2, one of W, ni/Au can be adopted for growth, grooves are formed at two ends, and the depth of the grooves is 30-150 nm; the first passivation dielectric layer 6 adopts SiO as the dielectric material 2 、Al 2 O 3 Any one of SiN with the thickness of 50 nm-200 nm is positioned above the Schottky anode metal layer 5; the first metal field plate layer 7 adopts an inclined plane field plate structure with the thickness of 50-200 nm and is positioned in a first passivation mediumAbove the mass layer 6; the second passivation dielectric layer 8 is the same as the first passivation dielectric layer 6 in material and thickness and is positioned above the first metal field plate layer 7; the second metal field plate layer 9 and the first metal field plate layer 7 are made of the same material and have the same thickness, and are located above the second passivation dielectric layer 8.
Referring to fig. 3, the method of fabricating the gallium nitride junction barrier schottky diode according to the present application provides the following three embodiments:
example 1: and manufacturing a Schottky diode with the P-type junction depth of 300nm, the ohmic cathode metal of Ti/Au, the Schottky anode metal of Ni/Au, the SiN of the first passivation dielectric layer and the second passivation dielectric layer, and the thickness of the first metal field plate layer and the second metal field plate layer of 50 nm.
Step 1: epitaxial wafer cleaning is performed as shown in fig. 3 (a).
The epitaxial wafer used in the example comprises an N+ gallium nitride substrate layer and an N-gallium nitride epitaxial layer from bottom to top, wherein the thickness of the N+ gallium nitride substrate layer is 3 mu m, and the thickness of the N-gallium nitride epitaxial layer is 5 mu m;
and (3) respectively ultrasonically cleaning the epitaxial wafer in acetone, ethanol and plasma water for 5min, and finally blow-drying the epitaxial wafer by a nitrogen gun.
Step 2: ohmic cathode metal layer deposition is shown in fig. 3 (b).
Forming a pattern on the lower surface of the N+ gallium nitride substrate layer of the epitaxial wafer by adopting one-time photoetching, then placing the epitaxial wafer into an electron beam evaporation table, and evaporating Ti/Au with the thickness of 20/45nm on the surface of the N+ gallium nitride substrate layer at the speed of 0.1nm/s to serve as ohmic cathode metal;
and removing redundant metal on the surface of the sample wafer by adopting a stripping process, and annealing for 30s at 860 ℃ to form an ohmic cathode metal layer.
Step 3: the P-type junction layer is deposited as shown in fig. 3 (c).
Forming a pattern on the N-gallium nitride epitaxial layer by adopting secondary photoetching, and adopting a reactive ion etching process to perform etching on the N-gallium nitride epitaxial layer under the conditions of 150W power, 5mTorr pressure and gas Cl 2 With BCl 3 Etching the whole sample wafer downwards for 300-500 nm under the condition that the flow rate ratio is 75sccm to 30sccm, wherein a plurality of interdigital grooves can be formed at 300 nm; wherein the reaction chamber pressureStrong: 5 torr, the rf source may be: 150W-200W.
Sputtering a P-type cuprous oxide film with the thickness of 300-500 nm, such as 300nm, in the formed interdigital groove on the upper surface of the etched sample wafer by using a magnetron sputtering process and using high-purity Cu as a target material and Ar as a protective gas, removing redundant metal on the surface of the sample wafer by using a stripping process, sequentially performing ultrasonic cleaning in acetone, ethanol and plasma water for 3min, and finally drying the sample wafer by using a nitrogen gun.
Step 4: schottky anode metal deposition is shown in fig. 3 (d).
Forming a pattern on the N-gallium nitride epitaxial layer by three times of photoetching, putting a sample wafer into an electron beam evaporation table, and evaporating W with the thickness of 120nm on the surface at the speed of 0.1nm/s to serve as Schottky anode metal;
and removing redundant metal on the surface of the whole sample by adopting a stripping process, and annealing for 5min at the temperature of 450 ℃ to form the Schottky anode metal layer.
Step 5: a first passivation dielectric layer is deposited as shown in fig. 3 (e).
And forming patterns on the two opposite ends of the Schottky anode metal layer by four times of photoetching, and etching the pattern areas to the position below the surface of the N-gallium nitride epitaxial layer (2), such as the position 30-150 nm below the surface, by adopting a buffer oxide etching process, wherein the etched wall surface is an inclined wall surface. The buffer oxide etching process is an RF radio frequency source: 150W to 200W is specifically 150W, the pressure (reaction chamber pressure) is 5mTorr, and the gas Cl 2 With BCl 3 The flow rate of (2) was 75sccm: etching the whole sample wafer under the condition of 30sccm, and forming a groove which is deep to 80nm below the surface of the N-gallium nitride epitaxial layer;
placing the sample into a plasma enhanced chemical vapor deposition device, wherein the deposition temperature of the sample is 220 ℃ in a cavity, and SiH is gas in a reaction chamber 4 ：N 2 O：N 2 The flow rate ratio was 40sccm:710sccm: depositing Si with thickness of 100nm under the condition of 180sccm 3 N 4 A first passivation dielectric layer.
Step 6: the first passivation dielectric layer is perforated as shown in fig. 3 (f).
And forming a pattern on the first passivation dielectric layer by adopting five times of photoetching, and then adopting a reactive ion etching process to open holes with the depth of 50-200 nm in the pattern area. The reactive ion etching process conditions are as follows:
reaction chamber pressure: 2000mtorr of the total number of the pieces of the fiber,
reaction chamber gas: siH (SiH) 4 、N 2 O、N 2 The three kinds of gases are used for generating the air,
reaction chamber gas flow rate ratio: siH (SiH) 4 ：N 2 O：N 2 ＝40sccm：710sccm：180sccm，
Reaction chamber temperature: 320-370 ℃,
an RF radio frequency source: 20W-30W.
And (3) sequentially ultrasonically cleaning the etched sample in acetone, ethanol and plasma water for 3min, and blow-drying by a nitrogen gun.
Step 7: a first metal field plate layer is fabricated as shown in fig. 3 (g).
And (3) placing the epitaxial wafer subjected to the steps into an electron beam evaporation table by adopting an electron beam evaporation process, and evaporating Ti/Au metal with the thickness of 25/25nm on the first passivation dielectric layer and the Schottky anode metal layer at the speed of 0.1nm/s to form a first metal field plate layer, namely growing a first metal field plate layer (7) with the thickness of 50-200 nm in holes on the upper surface of the whole sample wafer.
The process conditions for electron beam evaporation may be as follows:
working vacuum: 5E-4Pa of the pressure of the liquid,
reaction chamber gas: ti and Au are mixed together,
evaporation rate: the wavelength of the light is 0.1nm/s,
evaporation power: 30W-40W.
Step 8: a second passivation dielectric layer is fabricated as shown in fig. 3 (h).
Placing the sample into a plasma enhanced chemical vapor deposition device, and depositing Si with thickness of 50-200 nm, specifically 100nm under the following enhanced chemical vapor deposition process conditions 3 N 4 A second passivation dielectric layer, i.e. deposited on the first metal field plate layer (7)(8)。
The process conditions for enhanced chemical vapor deposition are as follows:
reaction chamber pressure: 2000mtorr of the total number of the pieces of the fiber,
reaction chamber gas: siH (SiH) 4 、N 2 O、N 2 The three kinds of gases are used for generating the air,
reaction chamber gas flow rate ratio: siH (SiH) 4 ：N 2 O：N 2 ＝40sccm：710sccm：180sccm，
Reaction chamber temperature: 320-370 ℃,
an RF radio frequency source: 20W-30W.
Or the specific process conditions are as follows:
the temperature of the cavity is 220 ℃, and the gas SiH of the reaction chamber 4 ：N 2 O：N 2 The flow rate ratio was 40sccm:710sccm:180sccm.
Step 9: the second passivation dielectric layer is perforated as shown in fig. 3 (i).
Forming a pattern on the second passivation dielectric layer by adopting a sixth photoetching process, and then adopting a reactive ion etching process to open holes with the depth of 50-200 nm in the pattern area, wherein the process conditions are as follows: at a power of 150W and a pressure of 5mTorr, gas Cl 2 With BCl 3 The flow rate ratio was 75sccm: etching the whole sample downwards under the condition of 30sccm, such as 100nm;
and (3) sequentially ultrasonically cleaning the etched sample in acetone, ethanol and plasma water for 3min, and blow-drying by a nitrogen gun.
Step 10: a second metal field plate layer is fabricated as shown in fig. 3 (j).
And (3) putting the sample wafer subjected to the steps into an electron beam evaporation table by adopting an electron beam evaporation process, evaporating Ti/Au metal with the thickness of 25/25nm on the second passivation medium layer and the Schottky anode metal layer at the speed of 0.1nm/s to form a second metal field plate layer, and completing the manufacturing of the gallium nitride junction barrier Schottky diode with the novel junction material, namely, growing a second metal field plate layer (9) with the thickness of 50-200 nm on the upper surface of the whole sample wafer. The process conditions of electron beam evaporation may also be as follows:
working vacuum: 5E-4Pa of the pressure of the liquid,
reaction chamber gas: ti and Au are mixed together,
evaporation rate: the wavelength of the light is 0.1nm/s,
evaporation power: 30W-40W.
Example 2: the P-type junction depth is 400nm, the ohmic cathode metal is Ti/Al/Ni/Au, the Schottky anode metal is Ni/Au, and the SiO 2 The first and second metal field plate layers are 100nm thick schottky diodes.
Step A: epitaxial wafer cleaning is performed as shown in fig. 3 (a).
Step a of this embodiment is the same as step 1 of embodiment 1.
And (B) step (B): ohmic cathode metal layer deposition is shown in fig. 3 (b).
B1 Patterning the lower surface of the N+ gallium nitride substrate layer of the epitaxial wafer by adopting first photoetching, then placing the epitaxial wafer into an electron beam evaporation table, and evaporating Ti/Al/Ni/Au with the thickness of 20/145/50/45nm on the surface of the N+ gallium nitride substrate layer at the speed of 0.1nm/s to serve as ohmic cathode metal;
b2 Removing redundant metal on the surface of the sample wafer by adopting a stripping process, and annealing for 30s at 860 ℃ to form an ohmic cathode metal layer.
Step C: the P-type junction layer is deposited as shown in fig. 3 (c).
C1 Patterning the N-GaN epitaxial layer by a second photolithography process, and performing reactive ion etching at a power of 150W, a pressure of 5mTorr, and gas Cl 2 With BCl 3 The flow rate ratio was 75sccm: etching the whole sample downwards for 400nm under the condition of 30 sccm;
c2 Depositing a P-type cuprous oxide film with the thickness of 400nm on the upper surface of the etched sample wafer by adopting a chemical vapor deposition process, removing redundant metal on the surface of the sample wafer by adopting a stripping process, sequentially carrying out ultrasonic cleaning on the sample wafer in acetone, ethanol and plasma water for 3min, and finally drying the sample wafer by using a nitrogen gun.
Step D: schottky anode metal deposition is shown in fig. 3 (d).
D1 Forming a pattern on the N-gallium nitride epitaxial layer by adopting third photoetching, then placing the sample wafer into an electron beam evaporation table, and evaporating Ni/Au with the thickness of 60nm/120nm on the surface at the speed of 0.1nm/s to serve as Schottky anode metal;
d2 Removing redundant metal on the surface of the whole sample by adopting a stripping process, and annealing for 5min at 450 ℃ to form the Schottky anode metal layer.
Step E: a first passivation dielectric layer is deposited as shown in fig. 3 (e).
E1 Patterning the Schottky anode metal layer by a fourth photolithography process, and performing reactive ion etching at a power of 150W, a pressure of 5mTorr, and gas Cl 2 With BCl 3 The flow rate of (2) was 75sccm: etching the whole sample wafer under the condition of 30sccm, and forming a groove which is deep to 80nm below the surface of the N-gallium nitride epitaxial layer;
e2 Placing the sample into a plasma enhanced chemical vapor deposition device, and reacting SiH4 and O in a reaction chamber with the cavity temperature of 220 DEG C 2 The gas flow rate ratio of (2) was 40sccm: under the condition of 710sccm, siO with thickness of 200nm is deposited 2 A first passivation dielectric layer.
Step F: the first passivation dielectric layer is perforated as shown in fig. 3 (f).
F1 Patterning the first passivation dielectric layer by fifth lithography, and etching with reactive ion etching at power of 150W, pressure of 5mTorr, and gas Cl 2 With BCl 3 The flow rate ratio was 75sccm: etching the whole sample downwards for 200nm under the condition of 30 sccm;
f2 The etched sample wafer is sequentially cleaned in acetone, ethanol and plasma water for 3min respectively, and is dried by a nitrogen gun.
Step G: a first metal field plate layer is fabricated as shown in fig. 3 (g).
And (3) placing the epitaxial wafer subjected to the steps into an electron beam evaporation table by adopting an electron beam evaporation process, and evaporating Ti/Au metal with the thickness of 50/50nm on the first passivation dielectric layer and the Schottky anode metal layer at the speed of 0.1nm/s to form a first metal field plate layer.
Step H: a second passivation dielectric layer is fabricated as shown in fig. 3 (h).
Placing the sample wafer with the first metal field plate layer into a plasma enhanced chemical vapor deposition device, and at a cavity temperature of 220 ℃, placing a reaction chamber SiH 4 With O 2 The gas flow rate ratio of (2) was 40sccm: under the condition of 710sccm, siO with thickness of 200nm is deposited 2 And a second passivation dielectric layer.
Step I: the second passivation dielectric layer is perforated as shown in fig. 3 (i).
I1 Patterning the second passivation dielectric layer by sixth photolithography, and etching with reactive ion at power of 150W, pressure of 5mTorr, and gas Cl 2 With BCl 3 Etching the whole sample downwards for 200nm under the condition that the flow rate ratio is 75sccm to 30 sccm;
i2 The etched sample wafer is sequentially cleaned in acetone, ethanol and plasma water for 3min respectively, and is dried by a nitrogen gun.
Step J: a second metal field plate layer is fabricated as shown in fig. 3 (j).
And (3) putting the sample wafer subjected to the steps into an electron beam evaporation table by adopting an electron beam evaporation process, and evaporating Ti/Au metal with the thickness of 50/50nm on the second passivation dielectric layer and the Schottky anode metal layer at the speed of 0.1nm/s to form a second metal field plate layer, thereby completing the manufacture of the gallium nitride junction barrier Schottky diode with the novel junction material.
Example 3: the P-type junction depth is 500nm, the ohmic cathode metal is Ti/Al/Au, the Schottky anode metal is W, al 2 O 3 The thickness of the first metal field plate layer and the second metal field plate layer are respectively 200nm for the Schottky diode.
Step one: epitaxial wafer cleaning is performed as shown in fig. 3 (a).
Step one of this embodiment is the same as step 1 of embodiment 1.
Step two: ohmic cathode metal layer deposition is shown in fig. 3 (b).
Firstly, forming a pattern on the lower surface of an N+ gallium nitride substrate layer of an epitaxial wafer by adopting first photoetching, then placing the epitaxial wafer into an electron beam evaporation table, and evaporating Ti/Al/Au with the thickness of 20/145/45nm on the surface of the N+ gallium nitride substrate layer at the speed of 0.1nm/s to serve as ohmic cathode metal;
and then removing redundant metal on the surface of the sample wafer by adopting a stripping process, and annealing for 30s at 860 ℃ to form an ohmic cathode metal layer.
Step three: the P-type junction layer is deposited as shown in fig. 3 (c).
Firstly, forming a pattern on an N-gallium nitride epitaxial layer by adopting a second photoetching process, and adopting a reactive ion etching process to obtain a semiconductor wafer with the power of 150W, the pressure of 5mTorr and the gas Cl 2 With BCl 3 The flow rate ratio was 75sccm: etching the whole sample downwards for 500nm under the condition of 30 sccm;
and then, adopting a thermal evaporation process to evaporate a P-type cuprous oxide film on the upper surface of the etched sample wafer, wherein the thickness of the P-type cuprous oxide film is 500nm, annealing the P-type cuprous oxide film, removing redundant metal on the surface of the sample wafer by adopting a stripping process, sequentially carrying out ultrasonic cleaning on the sample wafer in acetone, ethanol and plasma water for 3min, and finally drying the sample wafer by using a nitrogen gun.
Step four: schottky anode metal deposition is shown in fig. 3 (d).
Firstly, forming a pattern on an N-gallium nitride epitaxial layer by adopting third photoetching, putting a sample wafer into an electron beam evaporation table, and evaporating W with the thickness of 150nm on the surface at the speed of 0.1nm/s to serve as Schottky anode metal;
and then removing redundant metal on the surface of the whole sample by adopting a stripping process, and annealing for 5min at the temperature of 450 ℃ to form the Schottky anode metal layer.
Step five: the first passivation dielectric layer is deposited as shown in fig. 3 (e).
Firstly, forming a pattern on a Schottky anode metal layer by adopting fourth photoetching, and then adopting a reactive ion etching process to obtain a semiconductor device with the power of 150W, the pressure of 5mTorr and the gas Cl 2 With BCl 3 The flow rate of (2) was 75sccm: etching the whole sample wafer under the condition of 30sccm, and forming a groove which is deep to 80nm below the surface of the N-gallium nitride epitaxial layer;
then, the sample wafer is put into a plasma enhanced chemical vapor deposition device, and the temperature of the cavity is 220 ℃,reaction chamber gas flow rate Ar: n (N) 2 O: the TMA ratio was 700sccm:800sccm: depositing Al with thickness of 150nm on the whole sample at 100sccm 2 O 3 A first passivation dielectric layer.
Step six: the first passivation dielectric layer is perforated as shown in fig. 3 (f).
Firstly, forming a pattern on a first passivation dielectric layer by adopting fifth photoetching, and then adopting a reactive ion etching process to perform etching on the first passivation dielectric layer under the conditions of 150W power, 5mTorr pressure and gas Cl 2 With BCl 3 The flow rate ratio was 75sccm: etching the whole sample downwards for 150nm under the condition of 30 sccm;
and then, sequentially ultrasonically cleaning the etched sample in acetone, ethanol and plasma water for 3min, and blow-drying by a nitrogen gun.
Step seven: a first metal field plate layer is fabricated as shown in fig. 3 (g).
And (3) placing the epitaxial wafer subjected to the steps into an electron beam evaporation table by adopting an electron beam evaporation process, and evaporating Ti/Au metal with the thickness of 100/100nm on the first passivation dielectric layer and the Schottky anode metal layer at the speed of 0.1nm/s to form a first metal field plate layer.
Step eight: a second passivation dielectric layer is fabricated as shown in fig. 3 (h).
Putting the sample wafer manufactured by the first metal field plate layer into plasma enhanced chemical vapor deposition equipment, wherein the temperature of a cavity is 220 ℃, and the gas flow rate Ar of a reaction chamber is: n (N) 2 O: the TMA ratio was 700sccm:800sccm: depositing Al with thickness of 150nm on the whole sample at 100sccm 2 O 3 And a second passivation dielectric layer.
Step nine: the second passivation dielectric layer is perforated as shown in fig. 3 (i).
Firstly, forming a pattern on a second passivation dielectric layer by adopting a sixth photoetching process, and then adopting a reactive ion etching process to form a passivation dielectric layer under the conditions of 150W power, 5mTorr pressure and gas Cl 2 With BCl 3 The flow rate ratio was 75sccm: etching the whole sample downwards for 150nm under the condition of 30 sccm;
and then, sequentially ultrasonically cleaning the etched sample in acetone, ethanol and plasma water for 3min, and blow-drying by a nitrogen gun.
Step ten: a second metal field plate layer is fabricated as shown in fig. 3 (j).
And (3) placing the sample wafer subjected to the steps into an electron beam evaporation table by adopting an electron beam evaporation process, and evaporating Ti/Au metal with the thickness of 100/100nm on the second passivation dielectric layer and the Schottky anode metal layer at the speed of 0.1nm/s to form a second metal field plate layer so as to finish the manufacturing of the gallium nitride junction barrier Schottky diode.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (10)

1. The utility model provides a gallium nitride junction barrier schottky diode with novel junction material, its includes ohmic cathode metal layer (4), N+ gallium nitride substrate layer (1), N-gallium nitride epitaxial layer (2), P type tie layer (3) and schottky anode metal layer (5) from bottom to top, its characterized in that: a first passivation dielectric layer (6) is arranged above the two opposite ends of the Schottky anode metal layer (5); a first metal field plate layer (7) is arranged above the Schottky anode metal layer (5) and the first passivation dielectric layer (6); a second passivation dielectric layer (8) is arranged above the two opposite ends of the first metal field plate layer (7); a second metal field plate layer (9) is arranged above the first metal field plate layer (7) and the second passivation medium layer (8).
2. The gallium nitride junction barrier schottky diode of claim 1, wherein:
the thickness of the N-gallium nitride epitaxial layer (2) is 3-10 mu m, and the concentration range of carriers is 1E15cm -3 ～1E16cm -3 The carrier concentration of the N+ gallium nitride substrate layer (1) is 1E17cm -3 ～1E18cm -3 。
3. Gallium nitride junction barrier schottky diode according to claim 1, characterized in that the material of the P-type junction layer (3) is P-type cuprous oxide material and the junction depth is 300-500 nm.
4. The gallium nitride junction barrier schottky diode of claim 1, wherein:
the first passivation dielectric layer (6) and the second passivation dielectric layer(8) The dielectric material is SiO 2 、Al 2 O 3 、Si 3 N 4 The thickness of any one of the first passivation dielectric layer (6) and the second passivation dielectric layer (8) is 50-200 nm; and/or
The first metal field plate layer (7) and the second metal field plate layer (9) are of double-layer inclined field plate structures, the adopted materials are Ti/Au or Au, and the thickness of any layer of the first metal field plate layer (7) and the second metal field plate layer (9) is 50-200 nm.
5. The gallium nitride junction barrier schottky diode of claim 1, wherein:
the ohmic cathode metal layer (1) is formed by adopting one material of Ti, al, ni, au and Pt metal to form a single layer or multiple materials to form multiple layers; and/or
The Schottky anode metal layer (5) is formed by adopting one material of Ni, au and W to form a single layer or multiple layers of materials to form multiple layers.
6. The manufacturing method of the gallium nitride junction barrier Schottky diode with the novel junction material is characterized by comprising the following steps of:
1) Forming a pattern on the lower surface of the N+ gallium nitride substrate layer (1) by adopting one-time photoetching on an epitaxial wafer sequentially comprising the N+ gallium nitride substrate layer (1) and the N-gallium nitride epitaxial layer (2) from bottom to top, growing ohmic cathode metal in the pattern area by adopting an electron beam evaporation process, and performing thermal annealing treatment to form an ohmic cathode metal layer (4);
2) Forming a pattern on the N-gallium nitride epitaxial layer (2) by adopting secondary photoetching, and then adopting a reactive ion etching process to etch the whole sample downwards to form a plurality of interdigital grooves;
3) A P-type cuprous oxide film grows in the interdigital groove on the N-gallium nitride epitaxial layer (2) by adopting sputtering or other common film preparation processes to form a P-type junction layer (3);
4) Forming a pattern on the N-gallium nitride epitaxial layer (2) by adopting three times of photoetching, growing a Schottky anode metal layer (5) in a pattern area by adopting an electron beam evaporation process, and carrying out thermal annealing treatment;
5) Forming patterns at the two opposite ends of the Schottky anode metal layer (5) by four times of photoetching, and etching the pattern areas below the surface of the N-gallium nitride epitaxial layer (2) by adopting a buffer oxide etching process, wherein the etched wall surface is an inclined wall surface;
6) Depositing a first passivation dielectric layer (6) on the whole sample wafer by adopting a chemical vapor deposition process;
7) Forming a pattern on the first passivation dielectric layer (6) by adopting five times of photoetching, and then adopting a reactive ion etching process to open holes with the depth of 50-200 nm in a pattern area;
8) Adopting an electron beam evaporation process to grow a first metal field plate layer (7) with the thickness of 50-200 nm in a hole on the upper surface of the whole sample wafer;
9) A second passivation dielectric layer (8) is formed on the first metal field plate layer (7) by adopting a plasma enhanced chemical vapor deposition process;
10 Forming a pattern on the second passivation dielectric layer (8) by adopting six times of photoetching, and then adopting an etching process to open holes with the depth of 50-200 nm in the pattern area;
11 And (3) growing a second metal field plate layer (9) with the thickness of 50-200 nm on the upper surface of the whole sample wafer by adopting an electron beam evaporation process to obtain the gallium nitride junction barrier Schottky diode.
7. The method of manufacturing according to claim 6, wherein: the process conditions of the reactive ion etching process in the step 2) are as follows:
reaction chamber pressure: 5mtorr of the total number of the cells,
reaction chamber gas: cl 2 With BCl 3 ，
Reaction chamber gas flow rate ratio: cl 2 ：BCl 3 ＝75sccm：30sccm，
An RF radio frequency source: 150W-200W.
8. The method of manufacturing according to claim 6, wherein: the process conditions for the buffer oxide etching adopted in the step 5) are as follows:
reaction chamber pressure: 5mtorr of the total number of the cells,
reaction chamber gas: cl 2 With BCl 3 ，
Reaction chamber gas flow rate ratio: cl 2 ：BCl 3 ＝75sccm：30sccm，
An RF radio frequency source: 150W-200W.
9. The method of manufacturing according to claim 6, wherein: the process conditions for enhanced chemical vapor deposition in steps 7) and () areas follows:
reaction chamber pressure: 2000mtorr of the total number of the pieces of the fiber,
reaction chamber gas: siH (SiH) 4 、N 2 O、N 2 The three kinds of gases are used for generating the air,
reaction chamber gas flow rate ratio: siH (SiH) 4 ：N 2 O：N 2 ＝40sccm：710sccm：180sccm，
Reaction chamber temperature: 320-370 ℃,
an RF radio frequency source: 20W-30W.
10. The method of manufacturing according to claim 6, wherein: the process conditions for electron beam evaporation in steps 8) and 11) are as follows:
working vacuum: 5E-4Pa of the pressure of the liquid,
reaction chamber gas: ti and Au are mixed together,
evaporation rate: the wavelength of the light is 0.1nm/s,
evaporation power: 30W-40W.
CN202210422374.7A 2022-04-21 2022-04-21 Gallium nitride junction barrier Schottky diode with novel junction material and manufacturing method Pending CN116978930A (en)

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