CN116959996A - Packaging substrate with double-sided conductive bumps and manufacturing method thereof - Google Patents
Packaging substrate with double-sided conductive bumps and manufacturing method thereof Download PDFInfo
- Publication number
- CN116959996A CN116959996A CN202210378965.9A CN202210378965A CN116959996A CN 116959996 A CN116959996 A CN 116959996A CN 202210378965 A CN202210378965 A CN 202210378965A CN 116959996 A CN116959996 A CN 116959996A
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- circuit
- solder paste
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- 239000000758 substrate Substances 0.000 title claims abstract description 79
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 175
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 49
- 239000011241 protective layer Substances 0.000 claims abstract description 27
- 239000010408 film Substances 0.000 claims abstract description 25
- 238000005476 soldering Methods 0.000 claims abstract description 25
- 239000013039 cover film Substances 0.000 claims abstract description 17
- 238000002844 melting Methods 0.000 claims abstract description 11
- 230000008018 melting Effects 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 238000001816 cooling Methods 0.000 claims abstract description 3
- 229910000679 solder Inorganic materials 0.000 claims description 61
- 230000001681 protective effect Effects 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 9
- 238000007650 screen-printing Methods 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 description 6
- 238000007639 printing Methods 0.000 description 4
- 239000004698 Polyethylene Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The application provides a packaging substrate with double-sided conductive bumps and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate layer, at least one circuit layer and at least one protective layer are stacked on two opposite surfaces of the substrate layer, a first through hole is formed in each protective layer, and each circuit layer is exposed to the first through hole; setting a photoresist layer on the protective layer; exposing and developing the photoresist layer to obtain a patterned photoresist layer, wherein a second through hole is formed in the patterned photoresist layer, and the first through hole is communicated with the second through hole; filling soldering paste in the first through hole and the second through hole; forming a cover film on the patterned photoresist layer, wherein the cover film contacts the soldering paste; heating and melting soldering paste, and cooling to form a conductive bump, wherein the conductive bump is electrically connected with the circuit layer; and removing the covering film and the patterned photoresist layer to obtain the packaging substrate with the double-sided conductive bumps. The manufacturing method can improve the yield of the packaging substrate.
Description
Technical Field
The application relates to a packaging substrate with double-sided conductive bumps and a manufacturing method thereof.
Background
In the process of packaging a chip on a substrate, a plurality of connection pads on the chip are required to be electrically connected to a plurality of conductive bumps on the substrate. With the high integration of IC chips, further miniaturization of the diameter and pitch of the conductive bumps on the package substrate are demanded. The prior art generally first performs solder paste printing on a substrate, then forms solder balls by reflow, and then presses the solder balls flat to form solder bumps. However, the solder balls formed after reflow (reflow soldering) tend to be uneven in height during solder paste printing, which results in uneven heights and diameters of solder bumps after flattening, low yield, and affects subsequent chip packaging.
In addition, when the double-sided conductive bump is manufactured on the substrate, in order to avoid the adhesion of solder paste, the prior art generally adopts a mode of twice printing and twice reflow soldering. The surface of the conductive bump is often rough and deteriorated after secondary reflow due to the increase of tin printing times, the quality of the conductive bump is reduced, the yield is affected, and the production efficiency is low.
Disclosure of Invention
In view of the foregoing, there is a need for a package substrate with double-sided conductive bumps and a method for fabricating the same.
The application provides a manufacturing method of a packaging substrate with double-sided conductive bumps, which comprises the following steps: providing a substrate, wherein the substrate comprises a substrate layer, at least one circuit layer and at least one protective layer are overlapped on two opposite surfaces of the substrate layer, a first through hole is formed in each protective layer, and each circuit layer is exposed to the first through hole;
setting a photoresist layer on the protective layer;
exposing and developing the photoresist layer to obtain a patterned photoresist layer, wherein a second through hole is formed in the patterned photoresist layer, and the first through hole is communicated with the second through hole;
filling soldering paste in the first through hole and the second through hole;
forming a cover film on the patterned photoresist layer, wherein the cover film contacts the soldering paste;
heating and melting the soldering paste, and cooling the soldering paste after heating and melting to form a conductive bump, wherein the conductive bump is electrically connected with the circuit layer; and
and removing the covering film and the patterned photoresist layer to obtain the packaging substrate with the double-sided conductive bumps.
In some embodiments, a surface of the conductive bump remote from the wiring layer is planar.
In some embodiments, before the step of disposing a photoresist layer on the protective layer, the manufacturing method further includes:
arranging a protective film on the circuit layer exposed to the first through hole, wherein the protective film is an organic solder mask; the step of "heat-melting the solder paste" further includes:
and removing the protective film.
In some embodiments, the first through hole has an inner diameter that is smaller than an inner diameter of the second through hole.
In some embodiments, the solder paste is a lead-free solder paste, and the step of "heat-melting the solder paste" includes:
and melting the lead-free solder paste by adopting a reflow soldering mode.
In some embodiments, the step of filling the first and second vias with solder paste includes:
and filling solder paste in the first through hole and the second through hole in a screen printing mode, wherein one side of the solder paste, which is away from the circuit layer, is flush with one side of the patterned photoresist layer, which is away from the substrate layer.
In some embodiments, the number of the substrate layers in the substrate is one, the number of the circuit layers and the number of the protection layers are two, the two circuit layers are arranged at intervals, the two circuit layers are located on the same substrate layer, and after the cover film and the patterned photoresist layer are removed, the manufacturing method further includes:
and cutting the substrate layer to obtain two packaging substrates with the double-sided conductive bumps.
The application also provides a packaging substrate with double-sided conductive bumps, comprising:
the substrate comprises a substrate layer, wherein at least one circuit layer and at least one protective layer are stacked on two opposite surfaces of the substrate layer, a first through hole is formed in each protective layer, and each circuit layer is exposed to the first through hole;
the conductive bumps are arranged on two opposite sides of the substrate, one part of each conductive bump is positioned in the first through hole, the other part of each conductive bump is positioned outside the first through hole, the conductive bumps are electrically connected with the circuit layer, and each conductive bump is far away from the surface flush of the circuit layer.
In some embodiments, the conductive bump located within the first via has a cross-sectional width that is less than a cross-sectional width of the conductive bump located outside the first via.
In some embodiments, the conductive bump is made of lead-free solder paste.
According to the application, the cover film is arranged on the soldering paste to form the lamination, and then the reflow soldering is carried out to form the conductive bump, so that the flowing space and the height of the soldering paste in the reflow soldering process can be effectively controlled to be flush, the height and the diameter of the conductive bump are controlled, the uniformity and the yield of the conductive bump are improved, and the yield of the packaging substrate is further improved.
In addition, the conductive bumps are formed by filling the solder paste on the two opposite side surfaces of the substrate, so that the high-density requirement of the conductive bumps is met, and the production efficiency can be effectively improved while the quality of the conductive bumps is ensured.
Drawings
Fig. 1 is a cross-sectional view of a substrate according to an embodiment of the present application.
Fig. 2 is a cross-sectional view of the bonding pad shown in fig. 1 after a protective film is formed thereon.
Fig. 3 is a cross-sectional view after forming a photoresist layer on the protective layer shown in fig. 2.
Fig. 4 is a cross-sectional view of the photoresist layer shown in fig. 3 after exposure and development.
Fig. 5 is a cross-sectional view of the through hole shown in fig. 4 after filling solder paste therein.
Fig. 6 is a cross-sectional view of the patterned photoresist layer shown in fig. 5 after a cap film is formed thereon.
Fig. 7 is a cross-sectional view of the solder paste shown in fig. 6 after reflow soldering.
Fig. 8 is a cross-sectional view of the cap film and patterned photoresist layer of fig. 7 after removal.
Fig. 9 is a cross-sectional view of the package substrate obtained by cutting the base material layer shown in fig. 8.
Description of the main reference signs
Packaging substrate 100
Substrate 10
Substrate layer 101
First surface 1011
Second surface 1012
First circuit layer 102
First bond pad 1021
First protective layer 103
First via 1031
Second circuit layer 104
Second pad 1041
Second protective layer 105
Second through hole 1051
First protective film 20
Second protective film 22
First photoresist layer 30
Second photoresist layer 32
First patterned photoresist layer 34
Third through hole 341
Second patterned photoresist layer 36
Fourth through hole 361
First solder paste 40
Second solder paste 42
First cover film 50
Second cover film 52
First conductive bump 60
Second conductive bump 62
The application will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
Referring to fig. 1 to 9, an embodiment of the application provides a method for manufacturing a package substrate 100 with double-sided conductive bumps, which includes the following steps:
step S1: referring to fig. 1, a substrate 10 is provided, the substrate 10 includes at least one substrate layer 101, and the substrate layer 101 includes a first surface 1011 and a second surface 1012 opposite to the first surface 1011. At least one first circuit layer 102 and at least one first protection layer 103 are sequentially stacked on the first surface 1011 of the substrate layer 101, and at least one second circuit layer 104 and at least one second protection layer 105 are sequentially stacked on the second surface 1012 of the substrate layer 101.
The substrate 10 may be a flexible circuit board, a rigid circuit board, or a rigid-flex board. The material of the base material layer 101 may be one of Polyimide (PI), glass fiber epoxy adhesive (FR 4), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethylene (PE), and the like.
At least one first through hole 1031 is disposed in each of the first protection layers 103, and each of the first through holes 1031 penetrates through the first protection layer 103. Each of the first circuit layers 102 is exposed in the first via 1031 to form a first pad 1021. Similarly, at least one second through hole 1051 is disposed in each of the second passivation layers 105, and each of the second through holes 1051 penetrates through the second passivation layer 105. Each of the second circuit layers 104 is exposed in the second via 1051 to form a second pad 1041. The first protection layer 103 and the second protection layer 105 are used to protect the first circuit layer 102 and the second circuit layer 104, respectively. In this embodiment, the first protective layer 103 and the second protective layer 105 may be solder masks. Specifically, the material of the solder mask layer may be solder mask ink, such as green oil.
In this embodiment, the number of the base material layers 101 on the substrate 10 is one, the number of the first circuit layers 102 and the first protection layers 103 on the first surface 1011 is two, and the two first circuit layers 102 are disposed at intervals. The number of the second circuit layers 104 and the second protection layers 105 on the second surface 1012 is two, and the two second circuit layers 104 are spaced apart. The two first circuit layers 102 and the two second circuit layers 104 are disposed on the same substrate layer 101. The first circuit layer 102 and the second circuit layer 104 are symmetrically arranged, and the first protection layer 103 and the second protection layer 105 are symmetrically arranged.
Step S2: referring to fig. 2, a first protective film 20 is formed on each of the first pads 1021, and a second protective film 22 is formed on each of the second pads 1041.
Wherein the first protection film 20 is located in the first through hole 1031, and the second protection film 22 is located in the second through hole 1051. In this embodiment, the first and second protective films 20 and 22 may be organic protective solder films (OSP films) for preventing oxidation of the first and second pads 1021 and 1041.
Step S3: referring to fig. 3, a first photoresist layer 30 is formed on the first passivation layer 103, and a second photoresist layer 32 is formed on the second passivation layer 105.
As shown in fig. 3, in the present embodiment, the first photoresist layer 30 is formed on both the first protection layers 103, and the second photoresist layer 32 is formed on both the second protection layers 105.
The first photoresist layer 30 and the second photoresist layer 32 are heat-resistant photoresist, and may be a photosensitive film or a photosensitive ink.
Step S4: referring to fig. 4, the first photoresist layer 30 and the second photoresist layer 32 are exposed and developed to obtain a first patterned photoresist layer 34 and a second patterned photoresist layer 36.
Wherein a third via hole 341 is formed in the first patterned photoresist layer 34, and the third via hole 341 is communicated with the first via hole 1031. A fourth through hole 361 is formed in the second patterned photoresist layer 36, and the fourth through hole 361 communicates with the second through hole 1051.
In this embodiment, the inner diameter of the first through hole 1031 is smaller than the inner diameter of the third through hole 341. I.e. the projection of the first via 1031 on the first wiring layer 102 falls within the projection range of the third via 341 on the first wiring layer 102. Likewise, the second through hole 1051 has an inner diameter smaller than that of the fourth through hole 361. I.e. the projection of the second via 1051 on the second wiring layer 104 falls within the projection range of the fourth via 361 on the second wiring layer 104.
Step S5: referring to fig. 5, the first solder paste 40 is filled in the first and third through holes 1031 and 341, and the second solder paste 42 is filled in the second and fourth through holes 1051 and 361.
Specifically, screen printing is performed on the first surface 1011 and the second surface 1012 of the substrate layer 101 simultaneously by using a screen printing method. The first solder paste 40 and the second solder paste 42 are made of the same material, specifically, lead-free solder paste.
In this embodiment, the surface of the first solder paste 40 away from the first circuit layer 102 is substantially flush with the surface of the first patterned photoresist layer 34 away from the first protective layer 103, so that the height of each of the first solder paste 40 is substantially uniform. The surface of the second solder paste 42 away from the second circuit layer 104 is substantially flush with the surface of the second patterned photoresist layer 36 away from the second protective layer 105, and the height of each of the second solder paste 42 is substantially uniform.
Step S6: referring to fig. 6, a first cover film 50 is formed on the first patterned photoresist layer 34, and the first cover film 50 is pressed against the first solder paste 40; a second cover film 52 is formed over the second patterned photoresist layer 36, the second cover film 52 pressing the second solder paste 42.
Step S7: referring to fig. 7, the first solder paste 40 and the second solder paste 42 are melted by heating and cooled to form a first conductive bump 60 and a second conductive bump 62.
Specifically, the first solder paste 40 and the second solder paste 42 are melted by reflow. During the reflow process, a portion of the flux in the first and second solder pastes 40 and 42 may clear the first and second protective films 20 and 22. The first solder paste 40 and the second solder paste 42 shrink and tend to be spherical. And because of the shielding of the first and second cover films 50 and 52, the flow space of the first and second solder pastes 40 and 42 is limited, and the height and diameter can be kept uniform after molding, so that the yield of the first and second conductive bumps 60 and 62 can be improved.
The first conductive bump 60 is electrically connected to the first circuit layer 102, and the second conductive bump 62 is electrically connected to the second circuit layer 104.
Step S8: referring to fig. 8, the first and second cover films 50 and 52, and the first and second patterned photoresist layers 34 and 36 are removed.
Step S9: referring to fig. 9, the substrate layer 101 is cut to obtain two package substrates 100.
Wherein, the two package substrates 100 each have a double-sided conductive bump, i.e. two opposite sides of each package substrate 100 have a first conductive bump 60 and a second conductive bump 62, respectively.
The application forms the first soldering paste 40 and the second soldering paste 42 on the opposite sides of the substrate 10 simultaneously by double-sided screen printing, and then performs reflow soldering to form the first conductive bump 60 and the second conductive bump 62, which is beneficial to the high-density requirement of the packaging substrate on the conductive bump, and can effectively improve the production efficiency while ensuring the quality of the conductive bump.
In addition, by disposing the first cover film 50 on the first solder paste 40, disposing the second cover film 52 on the second solder paste 42, and then performing reflow soldering to form the first conductive bump 60 and the second conductive bump 62, the heights of the first conductive bump 60 and the second conductive bump 62 are flush, and the flowing space of the first solder paste 40 and the second solder paste 42 in the reflow soldering process can be effectively controlled, so that the diameters of the first conductive bump 60 and the second conductive bump 62 are controlled to be consistent, the uniformity and the yield of the first conductive bump 60 and the second conductive bump 62 are improved, and the yield of the package substrate 100 is further improved.
Referring to fig. 9, an embodiment of the present application further provides a package substrate 100 having double-sided conductive bumps, wherein the package substrate 100 includes a substrate 10, a first conductive bump 60 and a second conductive bump 62.
The substrate 10 includes a base material layer 101, a first wiring layer 102, a first protection layer 103, a second wiring layer 104, and a second protection layer 105. The substrate layer 101 includes a first surface 1011 and a second surface 1012 disposed opposite the first surface 1011. The first circuit layer 102 and the first protection layer 103 are sequentially stacked on the first surface 1011, and the second circuit layer 104 and the second protection layer 105 are sequentially stacked on the second surface 1012.
At least one first through hole 1031 is disposed in the first protection layer 103, and each first through hole 1031 penetrates through the first protection layer 103. The first circuit layers 102 are exposed in the first through holes 1031 to form first pads 1021. Similarly, at least one second through hole 1051 is disposed in each of the second passivation layers 105, and each of the second through holes 1051 penetrates through the second passivation layer 105. Each of the second circuit layers 104 is exposed in the second via 1051 to form a second pad 1041. The first protection layer 103 and the second protection layer 105 are used to protect the first circuit layer 102 and the second circuit layer 104, respectively. In this embodiment, the first protective layer 103 and the second protective layer 105 may be solder masks.
A portion of the first conductive bump 60 is located in the first via 1031, and another portion is located outside the first via 1031. Wherein the size (i.e., maximum outer diameter) of the first conductive bump 60 located inside the first via 1031 is smaller than the size (i.e., maximum outer diameter) of the first conductive bump 60 located outside the first via 1031. I.e. the projection of the first conductive bump 60 located inside the first via 1031 onto the first wiring layer 102 falls within the projection range of the first conductive bump 60 located outside the first via 1031 onto the first wiring layer 102. The surface of the first conductive bump 60 away from the first pad 1021 is a plane. The first conductive bump 60 is electrically connected to the first circuit layer 102.
A portion of the second conductive bump 62 is located in the second through hole 1051, and another portion is located outside the second through hole 1051. Wherein the second conductive bump 62 (i.e., the maximum outer diameter) located inside the second via 1051 is smaller than the second conductive bump 62 (i.e., the maximum outer diameter) located outside the second via 1051. I.e. the projection of the second conductive bump 62 located inside the second through hole 1051 onto the second wiring layer 104 falls within the projection range of the second conductive bump 62 located outside the second through hole 1051 onto the second wiring layer 104. The surface of the second conductive bump 62 away from the second pad 1041 is a plane. The second conductive bump 62 is electrically connected to the second circuit layer 104.
Wherein the first conductive bump 60 and the second conductive bump 62 are lead-free solder paste.
The present application is not limited to the above-mentioned embodiments, but is capable of other and obvious modifications and equivalents of the above-mentioned embodiments, which will be apparent to those skilled in the art from consideration of the present application without departing from the scope of the present application.
Claims (9)
1. The manufacturing method of the packaging substrate with the double-sided conductive bumps is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a substrate layer, at least one circuit layer and at least one protective layer are overlapped on two opposite surfaces of the substrate layer, a first through hole is formed in each protective layer, and each circuit layer is exposed to the first through hole;
setting a photoresist layer on the protective layer;
exposing and developing the photoresist layer to obtain a patterned photoresist layer, wherein a second through hole is formed in the patterned photoresist layer, and the first through hole is communicated with the second through hole;
filling soldering paste in the first through hole and the second through hole;
forming a cover film on the patterned photoresist layer, wherein the cover film contacts the soldering paste;
heating and melting the soldering paste, and cooling the soldering paste after heating and melting to form a conductive bump, wherein the conductive bump is electrically connected with the circuit layer; and
and removing the covering film and the patterned photoresist layer to obtain the packaging substrate with the double-sided conductive bumps.
2. The method of claim 1, wherein a surface of the conductive bump facing away from the circuit layer is planar.
3. The method of claim 1, wherein prior to disposing a photoresist layer on the protective layer, the method further comprises:
arranging a protective film on the circuit layer exposed to the first through hole, wherein the protective film is an organic solder mask; the step of "heat-melting the solder paste" further includes:
and removing the protective film.
4. The method of manufacturing of claim 1, wherein an inner diameter of the first through hole is smaller than an inner diameter of the second through hole.
5. The method of claim 1, wherein the solder paste is a lead-free solder paste, and the step of "heat-melting the solder paste" comprises:
and melting the lead-free solder paste by adopting a reflow soldering mode.
6. The method of manufacturing according to claim 1, wherein the step of filling the first and second through holes with solder paste includes:
and filling solder paste in the first through hole and the second through hole in a screen printing mode, wherein one side of the solder paste, which is away from the circuit layer, is flush with one side of the patterned photoresist layer, which is away from the substrate layer.
7. The method of claim 1, wherein the number of substrate layers in the substrate is one, the number of circuit layers and the number of protective layers are two, the two circuit layers are disposed at intervals, and the two circuit layers are disposed on the same substrate layer, and after removing the cover film and the protective layers, the method further comprises:
and cutting the substrate layer to obtain two packaging substrates with the double-sided conductive bumps.
8. A package substrate with double sided conductive bumps, comprising:
the substrate comprises a base material layer, at least one circuit layer and at least one protective layer, wherein at least one circuit layer and at least one protective layer are overlapped on two opposite surfaces of the base material layer, a first through hole is formed in each protective layer, and each circuit layer is exposed to the first through hole;
the conductive bumps are arranged on two opposite sides of the substrate, one part of each conductive bump is positioned in the first through hole, the other part of each conductive bump is positioned outside the first through hole, the conductive bumps are electrically connected with the circuit layer, and each conductive bump is far away from the surface flush of the circuit layer.
9. The package substrate with double-sided conductive bumps according to claim 8, wherein a cross-sectional width of the conductive bumps located within the first via is smaller than a cross-sectional width of the conductive bumps located outside the first via.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210378965.9A CN116959996A (en) | 2022-04-12 | 2022-04-12 | Packaging substrate with double-sided conductive bumps and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210378965.9A CN116959996A (en) | 2022-04-12 | 2022-04-12 | Packaging substrate with double-sided conductive bumps and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116959996A true CN116959996A (en) | 2023-10-27 |
Family
ID=88441312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210378965.9A Pending CN116959996A (en) | 2022-04-12 | 2022-04-12 | Packaging substrate with double-sided conductive bumps and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116959996A (en) |
-
2022
- 2022-04-12 CN CN202210378965.9A patent/CN116959996A/en active Pending
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