KR20100120574A - Manufacturing method of flip chip-micro bump in semiconductor package - Google Patents

Abstract

PURPOSE: A method for manufacturing a flip chip micro bump is provided to reduce manufacturing costs and improve productivity by forming a micro bump using a dry film resist without a metal mask. CONSTITUTION: A complex resist layer(Q) is formed on the upper side of a core layer(110) with a circuit pattern(111). The complex resist layer is formed by laminating a solder resist layer(120) and a dry film resist layer(130). The complex resist layer is exposed by using an exposure mask and is developed. A bump hole region is formed on the core layer. A solder resist(140) is coated on the bump hole region. The solder resist is reflowed.

Description

Manufacturing method of Flip chip-micro bump in Semiconductor package

The present invention relates to a method of manufacturing a semiconductor package for overcoming the problem of a solder on pad (SOP) method in a flip chip mounting method of a printed circuit board, and specifically, implements a process of removing a metal mask. The present invention relates to a method for manufacturing solder bumps that can implement fine pitch bumps using dry film resist (DFR).

As semiconductor chips become smaller, more versatile, higher in performance, and larger in capacity, packaging technology is becoming increasingly important as a key technology that ultimately determines the electrical performance, reliability, productivity and miniaturization of electronic devices. . Packaging technology refers to a series of processes that ultimately productize individual chips made in a wafer process. Recently, in order to further increase the mounting efficiency per unit volume, a ball grid array (BGA), a chip size package (CSP) that is about the same size as a chip size, and another chip stacked on the chip are stacked or have different functions. Technologies such as a multi chip module (MCM), in which several semiconductor chips are arranged in a single package, have emerged.

In particular, in recent years, packaging technology for protecting semiconductor devices from the external environment has been required in accordance with the trend of miniaturization and thinning of electronic devices, and high speed, high operation, high density mounting, and the like are required. Flip chip mounting technology for directly bonding a chip to a substrate is emerging. In other words, Flip Chip Bonding (FCB) technology, which is a technology of bonding individual semiconductor chips cut from a wafer to a printed circuit board (PCB) as it is, instead of packaging the wafer, is used as a chip size. As it can be mounted, it is attracting attention as a representative method of CSP (chip size package).

When mounting by the flip chip bonding method, an underfill layer is formed of a liquid resin material to secure a fixing force according to the bump height attached to the pad of the semiconductor chip, and the bonding performance is improved, and the chip To improve the damage and heat transfer capacity. The mounting method by flip chip bonding has excellent electrical characteristics because the connection distance between the semiconductor chip and the connection pad is very short, and the bonding is easy due to the self-alignment characteristic of the solder ball, and the size, weight and There is an I / O terminal on the bottom of the chip, which has the advantage that the signal transmission speed is about 20 times faster than the conventional wire type package.

1A to 1C, a package manufacturing process according to a solder on pad (SOP) process for mounting a chip through soldering on a pad by a conventional packaging technology will be described. Figure 1a is a process flow diagram of the above-described conventional SOP process, a detailed process conceptual diagram according to it is shown in Figure 1b, Figure 1c is an enlarged conceptual diagram for explaining the problem of the manufacturing process step.

The overall process flow is first loaded with the substrate. The substrate has a structure in which the circuit pattern 30 is formed on the insulating layer 10 and the solder resist layer 20 is formed on the remaining portions except the circuit pattern to be used as the bonding pads. Thereafter, a metal mask 50 having a hole formed at a position corresponding to the circuit pattern is raised, and the solder paste 60 is printed on the upper surface of the metal mask with a squeegee 40 so that the solder paste 60 is formed inside the hole. Allow filling (S step 1 to step S 2).

Thereafter, a process of separating the metal mask 50 is performed (step S3).

Then, the solder paste 60 is reflowed to form spherical solder bumps 60a and 60b on the circuit pattern 30 as shown in step S4 of FIG. 1B.

Of course, after the solder bump (coining), attach the chip, and through a separate reflow process to complete the semiconductor package (S 5 ~ S 8 step).

The conventional solder bump manufacturing method removes the metal mask 50 after printing the solder paste, and forms a solder bump on the circuit pattern through a reflow process. When the metal mask 50 is removed, the solder is removed. Due to the friction of the metal mask surface and the solder paste due to the viscosity of the paste 60, the amount of solder paste leaving the hole formed in the metal mask remains irregular, which makes it difficult to print uniform solder paste. When the application amount of the solder paste is not uniform, the size of the solder bumps may be smaller than the desired size or may not be formed at all, resulting in a problem that the reliability of the substrate is greatly reduced.

 In particular, in the above-described conventional SOP process, when the bump pitch becomes fine in the manufacturing step (S 2) of printing the solder paste on the metal mask, a problem that cannot be applied occurs.

Specifically, referring to FIG. 1C, as the bump pitch becomes finer and narrower, the thickness and the material of the metal mask and the material of the solder paste serve as important variables. That is, as shown, when the metal mask 50 is formed on the upper surface of the solder resist 20, the solder paste 60 is applied, and the process of separating the metal mask in the step S 3 described above After the separation of the metal mask, the solder volume printing occurs in a minute area, and the solder paste 60 collapses after the mask separation, and the particles 61 constituting the solder paste accumulate on the gap surface between the solder paste patterns. In addition, the bump bridge (B) that is connected to the neighboring solder paste is generated, which acts as a fatal problem to increase the defective rate of the product.

This becomes more severe when a bump pitch of 140 μm or less is implemented, and a SOP method using a metal mask is a big problem in an environment to realize a fine pitch. In addition, the narrower the pitch, the higher the cost of the solder paste, which requires the processing cost of the metal mask and the finer particles, also serves as a fatal disadvantage of this method.

The present invention has been made to solve the above-described problem, an object of the present invention is to form a solder bump to attach the die chip in the semiconductor package substrate, but without using a metal mask bump using dry film resist (DFR) It is possible to form, to provide a bump manufacturing method that can simplify the manufacturing process, maximize mass production, and minimize manufacturing costs.

The manufacturing process according to the present invention for solving the above problems is a step of forming a complex resist layer and a bump hole region in the core layer on which the circuit pattern is formed; Applying a solder resist to the bump hole area; Reflowing the solder resist; Characterized in that comprises a flip chip micro bump manufacturing method comprising a.

In particular, the first step described above, a) laminating a solder resist and a dry film resist (DFR) on the core layer to form a composite resist layer; b) exposing and developing the composite resist layer at the same time.

In addition, the first step as a process different from the above-described examples, c) patterning the bump hole region by forming a solder resist layer on the core layer; d) forming a dry film resist (DFR) layer in the solder resist region; e) patterning the dry film resist (DFR) layer to have a pattern corresponding to the bump hole region; It can be formed by consisting of.

In the above-described manufacturing process, after the three steps, the method may further include four steps of peeling the dry film resist (DFR) layer, and further, a step of stamping the bumps formed in the bump hole region is further performed. It may include.

The dry film resist (DFR) layer used in the above-described manufacturing process is preferably composed of polyester. That is, it is preferable to include a DFR made of a material having high heat resistance, acid resistance, and chemical resistance, so that the property does not change in the reflow process so that a stable process may be performed.

In addition, the above steps a) and d) may be formed on one side or both sides of the core layer on which the solder resist layer is formed.

In addition, the core layer used in the first step may be formed by laminating and patterning a dry film on the copper foil composite to form a circuit pattern through exposure.

According to the present invention, while forming a solder bump to attach the die chip on the semiconductor package substrate, it is possible to form a bump using a dry film resist (DFR) without using a metal mask, simplifying the manufacturing process, maximizing mass production And there is an effect that can minimize the manufacturing cost.

In particular, it is possible to realize a fine bump of 130㎛ pitch or less, to achieve a high density of semiconductor package components, and SOP (solder in) for quality issues and stable assembly due to interconnection (interconnect) pad) can also be implemented.

Hereinafter, with reference to the accompanying drawings will be described a specific configuration and operation according to the present invention. In the description with reference to the accompanying drawings, the same components are given the same reference numerals regardless of the reference numerals, and duplicate description thereof will be omitted. In addition, the substrate described below is a concept including all of the substrate for transmitting the electrical signal between electronic components. For example, the substrate according to the present invention may be a flip chip such as a rigid substrate, a flex substrate, an LCTT substrate, a single-sided / multi-faceted / multilayer substrate, a semiconductor mounting substrate (BGA, FBGA, TBGA, CSP), or the like. In the following, the semiconductor package substrate for flip chip connection will be described as an example, and the present invention can be variously applied to various types of circuit patterns formed in the substrate. Applicable to both Solder Mask Defined (NSD) type and Non-Solder Mask Defined (NSND) type.

Figures 2a and 2b show a flow chart and preferred process diagram showing a preferred embodiment according to the present invention.

The present invention basically includes a step of forming a composite resist layer on the core layer having a circuit pattern and forming a bump hole region, a step of applying a solder resist to the bump hole region, and a three step of reflowing the solder resist. It is made to include.

Specifically, the solder resist SR 120 is applied to the upper surface of the core layer 110 in which the circuit pattern 111 is formed on the outer layer (P 1 step).

Thereafter, a dry film resist (DFR) layer is formed on the solder resist 120 layer (P 2). In this case, the dry film resist (DFR) layer may be laminated in a film shape. In addition, the dry film resist (DFR) layer 130 may be formed on one or both surfaces of the solder resist 120 layer. Hereinafter, a structure in which the solder resist 120 layer and the dry film resist 130 layer are stacked is defined as a composite resist layer Q. In particular, the thickness or height of the dry film resist layer may be variously adjusted according to the height of the solder bumps.

Subsequently, a process of simultaneously exposing and developing the composite resist layer Q using the exposure mask M is performed (steps P3 to P4). The exposure and development perform patterning of the bump hole region R, which is a region where bumps are to be formed.

Thereafter, the solder paste 140 is applied to the bump hole region R (step P5), reflowed (step P6), and then the dry film resist 130 layer is peeled off. (P step 7). After peeling the dry film resist 130, a deflux process may be performed. Of course, the deflux process may be performed simultaneously with the peeling process.

After peeling of the P 7 step may be optionally added coining (coining).

A process different from the above-described embodiment will be described with reference to FIG. 2C.

Other embodiments have the same basic process sequence as the above-described embodiment, but differences occur in the process of forming the bump hole regions, which will be described below.

First, in step P 1, a solder resist 120 layer is formed on the core layer 110 on which the circuit pattern 111 is formed.

Subsequently, the bump hole region R is patterned (exposure and develop) using the solder resist 120 layer using an exposure mask M (steps P11 to P22).

Thereafter, a dry film resist 130 layer is formed on the solder resist 120 layer on which the bump hole region is formed. The manufacturing method may be implemented in various ways, and preferably may be implemented by laminating the DFR in the form of a film (P 13).

Thereafter, the exposure mask M is used to form holes having a pattern corresponding to the bump hole region R through exposure and development processes (P 14 to P 4).

Since the process after step P 4 is the same as the above-described embodiment will be omitted.

3 is a conceptual diagram illustrating a process of forming a core layer with a circuit pattern in the above-described process.

In the core layer on which the circuit pattern according to the present invention is formed, the hole H is formed in the insulating material 110 on which the copper foil 111 is formed by drilling, and the inside of the hole is plated with a metal such as Cu to form a via. (U1 ~ U3). Thereafter, a dry film resist DFR is coated on the copper foil 111, and a circuit pattern is formed through exposure and development through an exposure mask M (U4 to U5).

The dry film resist according to the present invention is preferably composed of polyester. That is, it is preferable to include a DFR made of a material having high heat resistance, acid resistance, and chemical resistance, so that the property does not change in the reflow process so that a stable process may be performed. Specifically, it will be more preferable to use DFR having heat resistance, acid resistance, and chemical resistance so that the properties thereof do not change even at high heat and acidity so that the properties can be maintained in the reflow process performed at 300 ° C. or lower.

As an example, the dry film resist (DFR) according to the present invention may be formed of a three-layer structure formed by sandwiching a photosensitive resin processed on a film between a base film having a thickness of 20 to 25 μm and a protective film. In particular, the DFR according to the present invention may be a material having a strong heat resistance, acid resistance, chemical resistance, in particular the base film may be a polyester film.

Moreover, DFR which is excellent in releasability and surface property by making the surface of a polyester film have the coating layer (the largest protrusion height of 0.1-2.0 micrometers in the surface of a coating layer) containing the aggregate component and crosslinking agent originating component which contain fluorine in a molecule | numerator Protective film may be applied. As the fluorine-containing aggregate component used in the coating agent, a fluoro olefin copolymer resin may be used. Moreover, in order to give a fixed protrusion height to a polyester film, microparticles | fine-particles (organic crosslinked polymer particle, amorphous silica particle from a characteristic such as transparency) can be added to a film or a coat layer.

In the manufacturing process according to the present invention it is possible to form a solder bump in a single process without using an expensive metal mask using a dry film (Dry flim). In particular, the advantage of shortening the circuit process by removing the metal mask in the process using a heat-resistant dry film, printing the solder paste, and proceeding the exposure and development process at the same time after laminating the dry film. In addition, since the metal mask is not used as described above, there is no fear that bump bridges are formed between the bumps when forming the existing fine pitch, so that SOPs having a fine pitch of 130 μm or less may be formed. By eliminating the increase in the cost of reducing the size of the solder paste, the solder paste having various sizes of particles can be applied to the process, thereby providing a product having quality and reliability.

In the foregoing detailed description of the present invention, specific examples have been described. However, various modifications are possible within the scope of the present invention. The technical idea of the present invention should not be limited to the embodiments of the present invention but should be determined by the equivalents of the claims and the claims.

1A to 1C are conceptual views illustrating a package manufacturing process and problems according to a SOP (Solder on Pad) process using a conventional packaging technology.

Figures 2a to 2c shows a flow chart and process diagram of the micro bumps according to the present invention.

3 is a process diagram illustrating a manufacturing process of the core layer according to the present invention.

Claims (8)

Forming a complex resist layer on the core layer on which the circuit pattern is formed and forming a bump hole region; Applying a solder resist to the bump hole area; Reflowing the solder resist; Flip chip micro bump manufacturing method comprising a. The method according to claim 1, The first step, a) forming a composite resist layer by laminating solder resist and dry film resist (DFR) on the core layer; b) simultaneously exposing and developing the composite resist layer; Flip chip micro bump manufacturing method characterized in that. The method according to claim 1, The first step, c) patterning the bump hole region by forming a solder resist layer on the core layer; d) forming a dry film resist (DFR) layer in the solder resist region; e) patterning the dry film resist (DFR) layer to have a pattern corresponding to the bump hole region; Flip chip micro bump manufacturing method characterized in that consisting of. The method according to claim 2 or 3, After step 3, The method of claim 1, further comprising the step of peeling the dry film resist (DFR) layer. The method according to claim 4, After step 4, The method of claim 1, further comprising the step of stamping the bump formed in the bump hole region. The method according to claim 4, The dry film resist (DFR) layer is a flip chip micro bump manufacturing method characterized in that it comprises a polyester. The method according to claim 4, Step a) and d), And forming the solder resist layer on one or both surfaces of the core layer on which the solder resist layer is formed. The method according to claim 1, The first step, Laminating and patterning the dry film on the copper foil composite, A method of manufacturing a flip chip micro bump, characterized in that it is a step formed by forming a circuit pattern through exposure development.

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