CN116234183A - Circuit board with conductive bump and manufacturing method thereof - Google Patents
Circuit board with conductive bump and manufacturing method thereof Download PDFInfo
- Publication number
- CN116234183A CN116234183A CN202111460780.4A CN202111460780A CN116234183A CN 116234183 A CN116234183 A CN 116234183A CN 202111460780 A CN202111460780 A CN 202111460780A CN 116234183 A CN116234183 A CN 116234183A
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- Prior art keywords
- conductive
- layer
- circuit
- hole
- circuit board
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Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 118
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 45
- 239000011241 protective layer Substances 0.000 claims abstract description 28
- 239000010408 film Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000013039 cover film Substances 0.000 claims abstract description 13
- 238000003466 welding Methods 0.000 claims abstract description 13
- 238000005476 soldering Methods 0.000 claims abstract description 8
- 229910000679 solder Inorganic materials 0.000 claims description 16
- 230000001681 protective effect Effects 0.000 claims description 10
- 238000007650 screen-printing Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- -1 polyethylene terephthalate Polymers 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 6
- 239000004721 Polyphenylene oxide Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 6
- 239000011112 polyethylene naphthalate Substances 0.000 description 6
- 229920000139 polyethylene terephthalate Polymers 0.000 description 6
- 239000005020 polyethylene terephthalate Substances 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 229920006380 polyphenylene oxide Polymers 0.000 description 6
- 239000011800 void material Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The application provides a manufacturing method of a circuit board with conductive bumps, which is characterized by comprising the following steps of: providing a circuit substrate, wherein the circuit substrate comprises a base layer, a conductive circuit layer and a protective layer which are sequentially stacked, a first through hole is formed in the protective layer, and the conductive circuit layer is exposed to the first through hole to form a welding pad; forming a photoresist layer on the protective layer; exposing and developing the photoresist layer to obtain a patterned photoresist layer, wherein a second through hole is formed in the patterned photoresist layer; filling a conductive paste in the first and second through holes; forming a cover film on the patterned photoresist layer; performing reflow soldering on the conductive paste to form conductive bumps; and removing the covering film and the patterned photoresist layer, thereby obtaining the circuit board. The circuit board yield can be improved. The application also provides a circuit board with the conductive bump manufactured by the method.
Description
Technical Field
The present disclosure relates to circuit boards, and particularly to a circuit board with conductive bumps and a method for manufacturing the circuit board.
Background
In the process of manufacturing circuit boards, it is sometimes necessary to print a conductive paste (e.g., solder paste) on a pad using a steel plate and flatten the paste for subsequent packaging. However, due to the fact that the solder paste has certain fluidity, the amount of tin under the solder paste is uneven during printing, copper leakage occurs after flattening due to the difference of the heights of the solder paste after reflow soldering, and the solder paste has the problems of big balls, small balls and no plane, so that the yield of the circuit board is reduced.
Disclosure of Invention
In view of this, the present application provides a circuit board with conductive bumps with higher yield.
An embodiment of the present application provides a method for manufacturing a circuit board with conductive bumps, including the following steps:
providing a circuit substrate, wherein the circuit substrate comprises a base layer, at least one conductive circuit layer and at least one protective layer which are sequentially stacked, each protective layer is provided with a first through hole, and each conductive circuit layer is exposed to the first through hole to form a welding pad;
forming a photoresist layer on the protective layer;
exposing and developing the photoresist layer to obtain a patterned photoresist layer, wherein a second through hole is formed in the patterned photoresist layer and is communicated with the first through hole;
filling a conductive paste in the first and second through holes;
forming a cover film on the patterned photoresist layer, and pressing the cover film on the conductive paste;
performing reflow soldering on the conductive paste to form a conductive bump, and electrically connecting the conductive bump with the welding pad; and
and removing the covering film and the patterned photoresist layer to obtain the circuit board, wherein the surface of the conductive bump, which is far away from the welding pad, is a plane.
Another embodiment of the present application provides a circuit board with conductive bumps, including:
the circuit substrate comprises a base layer, a conductive circuit layer and a protective layer which are sequentially stacked, wherein a first through hole is formed in the protective layer, and the conductive circuit layer is exposed to the first through hole to form a welding pad; and
and one part of the conductive bump is positioned in the first through hole, the other part of the conductive bump is positioned outside the first through hole, the conductive bump is electrically connected with the welding pad, and the surface of the conductive bump far away from the welding pad is a plane.
The photoresist layer is formed on the protective layer, the photoresist layer is exposed and developed to form the patterned photoresist layer, and then the conductive paste is filled in the first through hole and the second through hole in the patterned photoresist layer to replace a steel plate. Meanwhile, the covering film can effectively control the flow of the conductive paste in the reflow soldering process, so that the height and the diameter of the conductive convex blocks are controlled, the uniformity and the yield of the conductive convex blocks are improved, the yield of the circuit board is improved, and meanwhile the follow-up packaging of the circuit board is facilitated.
Drawings
Fig. 1 is a cross-sectional view of a circuit substrate according to an embodiment of the present application.
Fig. 2 is a cross-sectional view of the bonding pad shown in fig. 1 after an organic protective film is formed thereon.
Fig. 3 is a cross-sectional view after forming a photoresist layer on the protective layer shown in fig. 2.
Fig. 4 is a cross-sectional view of the photoresist layer shown in fig. 3 after exposure.
Fig. 5 is a cross-sectional view of the first and second through holes shown in fig. 4 after filling the conductive paste therein.
Fig. 6 is a cross-sectional view of the patterned photoresist layer shown in fig. 5 after a cap film is formed thereon.
Fig. 7 is a cross-sectional view of the conductive paste shown in fig. 6 after reflow soldering.
Fig. 8 is a cross-sectional view of the cap film and patterned photoresist layer of fig. 7 after removal.
Fig. 9 is a cross-sectional view of the wiring board obtained by cutting the base layer shown in fig. 8.
Description of the main reference signs
First via 1031
Organic protective film 20
Patterned photoresist layer 31
Second through hole 311
The following detailed description will further illustrate the application in conjunction with the above-described figures.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
In order to further describe the technical means and effects adopted by the present application to achieve the predetermined purpose, the following detailed description is made in connection with the accompanying drawings and preferred embodiments.
An embodiment of the present application provides a method for manufacturing a circuit board with conductive bumps, including the following steps:
in step S11, referring to fig. 1, a circuit substrate 10 is provided.
In one embodiment, the circuit substrate 10 includes a base layer 101, at least one conductive circuit layer 102, and at least one protective layer 103 stacked in sequence.
In other embodiments, the inside of the base layer 101 may further be provided with a plurality of conductive circuit layers (not shown).
The material of the base layer 101 may be one selected from epoxy resin (PP), BT resin, polyphenylene oxide (Polyphenylene Oxide, PPO), polyimide (PI), polyethylene terephthalate (Polyethylene Terephthalate, PET), and polyethylene naphthalate (Polyethylene Naphthalate, PEN). In this embodiment, the material of the base layer 101 is polyimide.
In this embodiment, at least one void (not shown) is disposed in each conductive trace layer 102, and the passivation layer 103 is also filled in the void.
At least one first through hole 1031 is disposed in each of the protection layers 103, and each of the first through holes 1031 penetrates through the protection layer 103. Wherein each of the conductive trace layers 102 is exposed to the first via 1031 to form a pad 1021. The protection layer 103 is used for protecting the conductive line layer 102. In this embodiment, the protection layer 103 may be a solder mask. Specifically, the material of the solder mask layer may be ink.
In this embodiment, the number of the base layers 101 in each circuit substrate 10 is one, and the number of the conductive circuit layers 102 and the number of the protective layers 103 in each circuit substrate 10 are two. Specifically, the two conductive circuit layers 102 are disposed at intervals, the two conductive circuit layers 102 are located on the same base layer 101, the two protective layers 103 are respectively located on the two conductive circuit layers 102, and the two protective layers 103 are disposed at intervals.
In step S12, referring to fig. 2, an organic protective film 20 is formed on each of the pads 1021.
Wherein the organic protective film 20 is further located in the first via 1031. In this embodiment, the organic protective film 20 may be an organic protective solder film (OSP film). The organic protective film 20 is used to prevent oxidation of the pad 1021.
In step S13, referring to fig. 3, a photoresist layer 30 is formed on the passivation layer 103.
As shown in fig. 3, the photoresist layer 30 is formed on both the protective layers 103.
Wherein the photoresist layer 30 is a heat-resistant photoresist. In one embodiment, the photoresist layer 30 may be a photosensitive film or a photosensitive ink.
In step S14, referring to fig. 4, the photoresist layer 30 is exposed and developed to obtain a patterned photoresist layer 31.
Wherein, a second through hole 311 is disposed in the patterned photoresist layer 31, and the second through hole 311 is communicated with the first through hole 1031.
In this embodiment, the inner diameter of the first through hole 1031 is smaller than the inner diameter of the second through hole 311. I.e. the projection of the first via 1031 onto the conductive line layer 102 falls within the projection range of the second via 311 onto the conductive line layer 102.
In step S15, referring to fig. 5, the conductive paste 40 is filled in the first via 1031 and the second via 311.
Specifically, the conductive paste 40 is filled in the first and second through holes 1031 and 311 by screen printing.
The conductive paste 40 may be lead-free solder paste, copper paste, or the like. In this embodiment, the conductive paste 40 is a lead-free solder paste.
In this embodiment, the surface of the conductive paste 40 away from the conductive trace layer 102 is substantially flush with the surface of the patterned photoresist layer 31 away from the conductive trace layer 102.
In step S16, referring to fig. 6, a cover film 50 is formed on the patterned photoresist layer 31, and the cover film 50 is pressed against the conductive paste 40.
It is understood that the cover film 50 is in contact with the conductive paste 40.
In step S17, referring to fig. 7, the conductive paste 40 is reflowed to form conductive bumps 60.
Specifically, during the reflow process, a part of the flux in the conductive paste 40 may remove the organic protective film 20, and the solvent and a part of the flux in the conductive paste 40 may volatilize, and at the same time, the cohesion of the conductive paste 40 increases to shrink the conductive paste 40 and approach a sphere shape.
It can be appreciated that, due to the blocking of the cover film 50, the conductive paste 40 can flow only in the first via 1031 and the second via 311 after being heated during the reflow process, so that the yield of the conductive bump 60 can be improved.
The conductive bump 60 is electrically connected to the pad 1021, so that the conductive bump 60 is electrically connected to the conductive circuit layer 102.
In step S18, referring to fig. 8, the cover film 50 and the patterned photoresist layer 31 are removed.
As shown in fig. 8, the surface of the conductive bump 60 away from the pad 1021 is a plane.
In step S19, referring to fig. 9, the base layer 101 is cut to obtain two circuit boards 100.
Wherein, two conductive circuit layers 102 are respectively located in two circuit boards 100. I.e. each of the circuit boards 100 comprises one of the conductive trace layers 102.
Referring to fig. 9, an embodiment of the present application further provides a circuit board 100 with conductive bumps, where the circuit board 100 includes a circuit substrate 10 and the conductive bumps 60.
In one embodiment, the circuit substrate 10 includes a base layer 101, a conductive circuit layer 102, and a protective layer 103 stacked in sequence.
In other embodiments, the inside of the base layer 101 may further be provided with a plurality of conductive circuit layers (not shown). The material of the base layer 101 may be one selected from epoxy resin (PP), BT resin, polyphenylene oxide (Polyphenylene Oxide, PPO), polyimide (PI), polyethylene terephthalate (Polyethylene Terephthalate, PET), and polyethylene naphthalate (Polyethylene Naphthalate, PEN). In this embodiment, the material of the base layer 101 is polyimide.
In this embodiment, at least one void (not shown) is disposed in the conductive circuit layer 102, and the protection layer 103 is also filled in the void.
At least one first through hole 1031 is disposed in the protection layer 103, and the first through holes 1031 penetrate through the protection layer 103. Wherein the conductive line layer 102 is exposed to the first via 1031 to form a pad 1021. The protection layer 103 is used for protecting the conductive line layer 102. In this embodiment, the protection layer 103 may be a solder mask. Specifically, the material of the solder mask layer may be ink.
One part of the conductive bump 60 is located in the first via 1031, and the other part is located outside the first via 1031. Wherein the conductive bump 60 located inside the first via 1031 has a smaller size (i.e., maximum outer diameter) than the conductive bump 60 located outside the first via 1031. I.e. the projection of the conductive bump 60 located within the first via 1031 onto the conductive trace layer 102 falls within the projection of the conductive bump 60 located outside the first via 1031 onto the conductive trace layer 102. Wherein the surface of the conductive bump 60 away from the pad 1021 is a plane.
The conductive bump 60 is electrically connected to the pad 1021, so that the conductive bump 60 is electrically connected to the conductive circuit layer 102.
The conductive bump 60 may be lead-free solder paste, copper paste, or the like. In this embodiment, the conductive bump 60 is a lead-free solder paste.
The photoresist layer 30 is formed on the protective layer 103, and the photoresist layer 30 is exposed and developed to form the patterned photoresist layer 31, and then the conductive paste 40 is filled in the first through holes 1031 and the second through holes 311 in the patterned photoresist layer 31 instead of the steel plate. Meanwhile, the cover film 50 in the present application can effectively control the flow of the conductive paste 40 in the reflow soldering process, so as to control the height and diameter of the conductive bump 60, improve the uniformity and yield of the conductive bump, and further improve the yield of the circuit board 100, and is also beneficial to the subsequent packaging of the circuit board 100.
In addition, the conductive paste 40 is filled in a screen printing mode, and high-precision alignment is not needed in the screen printing mode, so that the uniformity of filling of the conductive paste 40 is improved, and meanwhile, the filling efficiency can be improved.
The above description is only one preferred embodiment of the present application, but is not limited to this embodiment during actual application.
Claims (10)
1. The manufacturing method of the circuit board with the conductive bumps is characterized by comprising the following steps of:
providing a circuit substrate, wherein the circuit substrate comprises a base layer, at least one conductive circuit layer and at least one protective layer which are sequentially stacked, each protective layer is provided with a first through hole, and each conductive circuit layer is exposed to the first through hole to form a welding pad;
forming a photoresist layer on the protective layer;
exposing and developing the photoresist layer to obtain a patterned photoresist layer, wherein a second through hole is formed in the patterned photoresist layer and is communicated with the first through hole;
filling a conductive paste in the first and second through holes;
forming a cover film on the patterned photoresist layer, and pressing the cover film on the conductive paste;
performing reflow soldering on the conductive paste to form a conductive bump, and electrically connecting the conductive bump with the welding pad; and
and removing the covering film and the patterned photoresist layer to obtain the circuit board, wherein the surface of the conductive bump, which is far away from the welding pad, is a plane.
2. The method of manufacturing a circuit board according to claim 1, wherein the conductive paste is filled in the first through hole and the second through hole by screen printing.
3. The method of manufacturing a circuit board according to claim 1, wherein before forming the photoresist layer on the protective layer, the method further comprises:
forming an organic protective film on the bonding pad;
in the process of reflow soldering the conductive paste, the manufacturing method further comprises the following steps:
and removing the organic protective film.
4. The method of manufacturing a circuit board according to claim 1, wherein an inner diameter of the first through hole is smaller than an inner diameter of the second through hole.
5. The method of claim 1, wherein the photoresist layer is a photosensitive film or a photosensitive ink.
6. The method of claim 1, wherein the conductive paste is a lead-free solder paste.
7. The method of manufacturing a circuit board according to claim 1, wherein the number of the base layers in each circuit substrate is one, the number of the conductive circuit layers and the number of the protective layers in each circuit substrate are two, the two conductive circuit layers are disposed at intervals, the two conductive circuit layers are disposed on the same base layer, the two protective layers are disposed on the two conductive circuit layers, respectively, and the two protective layers are disposed at intervals, and after removing the cover film and the protective layer, the method further comprises:
cutting the base layer to obtain two circuit boards;
the two conductive circuit layers are respectively located in the two circuit boards.
8. A circuit board with conductive bumps, comprising:
the circuit substrate comprises a base layer, a conductive circuit layer and a protective layer which are sequentially stacked, wherein a first through hole is formed in the protective layer, and the conductive circuit layer is exposed to the first through hole to form a welding pad; and
and one part of the conductive bump is positioned in the first through hole, the other part of the conductive bump is positioned outside the first through hole, the conductive bump is electrically connected with the welding pad, and the surface of the conductive bump far away from the welding pad is a plane.
9. The circuit board of claim 8, wherein the conductive bumps located within the first vias have a smaller size than the conductive bumps located outside the first vias.
10. The circuit board of claim 8, wherein the conductive bump is made of lead-free solder paste.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111460780.4A CN116234183A (en) | 2021-12-02 | 2021-12-02 | Circuit board with conductive bump and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111460780.4A CN116234183A (en) | 2021-12-02 | 2021-12-02 | Circuit board with conductive bump and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116234183A true CN116234183A (en) | 2023-06-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111460780.4A Pending CN116234183A (en) | 2021-12-02 | 2021-12-02 | Circuit board with conductive bump and manufacturing method thereof |
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| Country | Link |
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| CN (1) | CN116234183A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11112133A (en) * | 1997-10-03 | 1999-04-23 | Nippon Avionics Co Ltd | Method for planarizing solder bump |
| US6432807B1 (en) * | 1999-06-10 | 2002-08-13 | Nec Corporation | Method of forming solder bumps on a semiconductor device using bump transfer plate |
| JP2004006926A (en) * | 1996-03-29 | 2004-01-08 | Ngk Spark Plug Co Ltd | Wiring board with solder bump, its manufacturing method, and flattening jig |
| US20060202331A1 (en) * | 2005-03-09 | 2006-09-14 | Wen-Hung Hu | Conductive bump structure of circuit board and method for fabricating the same |
| CN101226908A (en) * | 2007-01-16 | 2008-07-23 | 百慕达南茂科技股份有限公司 | Projection structure with ring-shaped support and manufacturing method thereof |
| KR20110015904A (en) * | 2009-08-10 | 2011-02-17 | 삼성전기주식회사 | Method for manufacturing of solder bump |
| JP2016051747A (en) * | 2014-08-29 | 2016-04-11 | 京セラサーキットソリューションズ株式会社 | Wiring board |
-
2021
- 2021-12-02 CN CN202111460780.4A patent/CN116234183A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004006926A (en) * | 1996-03-29 | 2004-01-08 | Ngk Spark Plug Co Ltd | Wiring board with solder bump, its manufacturing method, and flattening jig |
| JPH11112133A (en) * | 1997-10-03 | 1999-04-23 | Nippon Avionics Co Ltd | Method for planarizing solder bump |
| US6432807B1 (en) * | 1999-06-10 | 2002-08-13 | Nec Corporation | Method of forming solder bumps on a semiconductor device using bump transfer plate |
| US20060202331A1 (en) * | 2005-03-09 | 2006-09-14 | Wen-Hung Hu | Conductive bump structure of circuit board and method for fabricating the same |
| CN101226908A (en) * | 2007-01-16 | 2008-07-23 | 百慕达南茂科技股份有限公司 | Projection structure with ring-shaped support and manufacturing method thereof |
| KR20110015904A (en) * | 2009-08-10 | 2011-02-17 | 삼성전기주식회사 | Method for manufacturing of solder bump |
| JP2016051747A (en) * | 2014-08-29 | 2016-04-11 | 京セラサーキットソリューションズ株式会社 | Wiring board |
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