TWI581383B - Semiconductor chip package having double sided ball planting and the method for fabricating the same - Google Patents

Description

Double-sided ball-forming semiconductor chip package structure and manufacturing method thereof

The present invention relates to a semiconductor package structure, and more particularly to a semiconductor wafer package structure for double-sided ball implantation and a method of fabricating the same, which can be applied to a package package structure of a package-on-package (POP).

The semiconductor package stack structure (POP) combines the top and bottom semiconductor package structures in a top-bottom stack and reflow soldering. The bottom package structure of the package stack and the top package structure each seal the appropriate wafer, which may or may not be the same. Individual seals that are typically different wafers to form a system package. The electrical connection between the bottom package structure and the top package structure is in addition to the use of the bottom solder ball to the top package structure, and a plurality of through mold vias (TMV) are used, which are through the bottom package structure. Molding the gel. The method of forming the through-holes includes laser drilling after the formation of the molding compound of the bottom package structure to expose the ball pads or the intermediate solder balls embedded in the molding compound. Whether or not the intermediate solder balls are pre-planted prior to molding, the high energy of the laser drilling can cause damage to the surface of the ball mat or the intermediate solder balls.

In addition, the conventional ball grid array package structure is fabricated on the substrate strip When the single-sided ball is placed on the mother board, the thickness and structural strength of the mother board are insufficient to support the double-sided ball planting, and the problem of falling the ball is easy to occur.

In order to solve the above problems, the main object of the present invention is to provide a semiconductor wafer package structure for double-sided ball implantation and a manufacturing method thereof for reducing the risk of falling ball during the process of joining double-sided solder balls, and avoiding the conventional mold sealing. Damage to the metal surface during hole fabrication.

A second object of the present invention is to provide a semiconductor wafer package structure and a manufacturing method thereof for double-sided ball implantation, which can reduce the packaging process of bonding double-sided solder balls to achieve the effect of reducing packaging cost.

A further object of the present invention is to provide a semiconductor wafer package structure for double-sided ball implantation and a method of fabricating the same to achieve the effect of heat dissipation gain at the bottom of the package stack structure.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a semiconductor wafer package structure for double-sided ball implantation, comprising a substrate, a plurality of first solder balls, a wafer, a mold sealing body, a plurality of second solder balls, and a plurality of third solder balls. The substrate has an upper surface and a lower surface. The upper surface is provided with a plurality of first pads and a plurality of peripheral ball pads, and the lower surface is provided with a plurality of first ball pads and a plurality of second ball pads. The substrate has a plurality of first vias and a plurality of second vias, the first vias connecting the first pads and the first ball pads, and the second vias are connected to the Some peripheral ball pads and the second ball pads. The first solder balls are bonded to the peripheral balls pad. The chip is disposed on the upper surface of the substrate and covers the first pads. The mold encapsulation system is formed on the upper surface of the substrate to seal the wafer, and the mold encapsulation system partially seals the first solder balls. The thickness of the mold encapsulant is greater than the set height of the wafer but less than The height of the first solder balls to reveal the curved surfaces of the first solder balls. The second solder balls are bonded to the first ball pads. The third solder balls are bonded to the second ball pads. The present invention further discloses a method of fabricating the semiconductor wafer package structure of the double-sided ball.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing semiconductor chip package structure, the plurality of bumps may be further disposed on the active surface of the wafer and bonded to the first pads, so that the wafer is flip-chip bonded to the substrate. Upper surface.

In the foregoing semiconductor wafer package structure, an underfill may be further formed between the wafer and the substrate to cover the bumps.

In the foregoing semiconductor chip package structure, a back surface of the wafer may be attached to the upper surface of the substrate by a die bonding layer and cover the first pads, and the upper surface of the substrate may be further provided with a plurality of The second pads are located between the first pads and the peripheral ball pads, and the plurality of bonding wires can connect the plurality of pads of the chip to the second pads.

In the foregoing semiconductor chip package configuration, the minimum gap from the first solder balls to one of the adjacent sides of the wafer may be no more than the average gap of the first solder balls.

By the above technical means, the invention can achieve the risk of falling ball during the process of joining the double-sided solder balls, and the laser drilling process can be eliminated, so as to avoid surface damage of the soldering surface of the package stack, thereby reducing the package. Process and have the advantage of reducing packaging costs. . In a specific application, the top side ball placement and wafer placement of the bottom package structure of the package stack may be performed first, and the wafer connection may be flip-chip (FC) bonding or wire bonding ( Wire bonding, WB), using a stamper press die with a film on the top mold, the top side solder balls are partially trapped in the film during the mold injection. After the injection molding is completed, the solder ball portion covered in the film is exposed to be soldered for the solder ball of the top package structure of the package stack, thereby achieving the three-dimensional package stack.

100‧‧‧Semiconductor chip package construction

110‧‧‧Substrate

111‧‧‧Upper surface

112‧‧‧ lower surface

113‧‧‧First mat

114‧‧‧around ball pad

115‧‧‧First ball mat

116‧‧‧second ball mat

117‧‧‧First via

118‧‧‧Second via

120‧‧‧First solder ball

121‧‧‧ curved surface

130‧‧‧ wafer

131‧‧‧Active surface

132‧‧‧Back

140‧‧‧Mold sealant

140A‧‧·Mold sealant precursor

150‧‧‧second solder ball

160‧‧‧ third solder ball

170‧‧‧Bumps

171‧‧‧ solder

180‧‧‧ underfill

200‧‧‧Semiconductor chip package construction

233‧‧‧ solder pads

219‧‧‧second mat

270‧‧‧welding line

280‧‧‧Mack layer

310‧‧‧Upper mold

311‧‧‧Dissecting film

1 is a cross-sectional view showing a semiconductor wafer package structure of a double-sided ball in accordance with a first embodiment of the present invention.

2A to 2F are schematic cross-sectional views showing the main steps of the manufacturing method of the semiconductor wafer package structure according to the first embodiment of the present invention.

3A to 3C are cross-sectional views showing the components of the semiconductor chip package structure in the secondary steps of the formation process of a mold encapsulant in accordance with the first embodiment of the present invention.

Figure 4 is a cross-sectional view showing another semiconductor wafer package structure for double-sided ball implantation in accordance with a second embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

In accordance with a first embodiment of the present invention, a double-sided ball-on semiconductor wafer package structure 100 is illustrated in cross-section in FIG. The semiconductor chip package structure 100 includes a substrate 110, a plurality of first solder balls 120, a wafer 130, a molding compound 140, a plurality of second solder balls 150, and a plurality of third solder balls 160.

Referring to FIG. 1 , the substrate 110 has an upper surface 111 and a lower surface 112. The upper surface 111 is provided with a plurality of first pads 113 and a plurality of peripheral ball pads 114. The lower surface 112 is provided with a plurality of The first ball pad 115 and the plurality of second ball pads 116. Typically, the substrate 110 can be a miniature printed circuit board. The substrate 110 has a plurality of first vias 117 and a plurality of second vias 118. The first vias 117 are connected to the first pads 113 and the first ball pads 115. The two through holes 118 are connected to the peripheral ball pads 114 and the second ball pads 116. In this embodiment, the first pads 113 can be flip-chip bonded signal transmission pads, and the first vias 117 and the second vias 118 can be signal transmissions. The plated through holes are provided with metal structures in the holes and are respectively located at the center and the periphery of the substrate 110. With the combination described above, the structural strength and heat dissipation of the substrate 110 can be enhanced.

The first solder balls 120 are bonded to the peripheral ball pads 114. The first solder balls 120 are used to bond the same or different top package configurations when the package is stacked. The materials of the first solder balls 120 may be made of a solder metal material such as tin-lead or tin-silver-copper. In a preferred feature, the minimum gap between the first solder balls 120 and one of the adjacent sides of the wafer 130 may be no more than the average gap of the first solder balls 120, and may be omitted for forming the mold gap. In the laser drilling process of the hole, the wafer 130 and the first solder balls 120 do not touch and interfere with each other.

The wafer 130 is disposed on the upper surface 111 of the substrate 110 and covers the first pads 113. The wafer 130 can be a semiconductor wafer having an integrated circuit. In this embodiment, the semiconductor chip package structure 100 can further include a plurality of bumps 170, which can be fixed on one active surface 131 of the wafer 130 and bonded to the first pads 113 to make the wafer. The flip-chip is bonded to the upper surface 111 of the substrate 110. The back surface 132 of the wafer 130 is relatively away from the substrate 110. Therefore, the bumps 170 can be electrically connected to the wafer 130 and the first interfaces. Pad 113. The bumps 170 may be columnar bumps such as copper pillars, and each bump 170 is soldered to the corresponding first pad 113 by a solder 171.

The molding compound 140 is formed on the upper surface 111 of the substrate 110 to seal the wafer 130. The molding compound 140 can be a thermosetting composite colloid formed by molding. In addition, the molding compound 140 partially seals the first solder balls. 120. The thickness of the molding compound 140 is greater than the height of the wafer 130 but less than the height of the first solder balls 120 to expose the curved surfaces 121 of the first solder balls 120. The curved surface 121 is less than fifty percent of the surface area of the first solder balls 120 and does not need to be ground flat to maintain the spherical shape of the first solder balls 120. In this embodiment, the curved surfaces 121 of the first solder balls 120 can serve as solder-free solder joints for the upper bonding of the POP package stack.

The second solder balls 150 are bonded to the first ball pads 115. The third solder balls 160 are bonded to the second ball pads 116. The materials of the second solder balls 150 and the third solder balls 160 may be the same as the materials of the first solder balls 120. The second solder balls 150 and the third solder balls 160 are electrically connected to each other.

In order to reduce the flip chip bonding height of the wafer 130 as much as possible, so that the first solder balls 120 protrude slightly from the mold sealing body 140, the gap between the wafer 130 and the substrate 110 will be disadvantageous to the molding compound 140. Filled. The semiconductor chip package structure 100 can further include an underfill layer 180 between the wafer 130 and the substrate 110 to cover the bumps 170, so that the wafer 130 can be further fixed on the substrate. 110, the bumps 170 may not interfere with each other.

Therefore, the present invention can achieve a reduction in the risk of falling the ball during the process of joining the double-sided solder balls, and can also eliminate the laser drilling process to avoid surface damage of the package stack soldering surface.

The manufacturing method of the semiconductor wafer package structure 100 for the above-described double-sided ball implantation is further described as follows. FIGS. 2A to 2F are schematic cross-sectional views showing the main steps of the manufacturing process of the semiconductor wafer package structure 100.

First, referring to FIG. 2A, a substrate 110 having an upper surface 111 and a lower surface 112 is provided. In this step, the substrate 110 is in a mother board type. The upper surface 111 is provided with a plurality of first pads 113 and a plurality of peripheral ball pads 114. The lower surface 112 is provided with a plurality of first ball pads 115 and a plurality of second ball pads 116, and the substrate 110 is another The plurality of first vias 117 and the plurality of second vias 118 are connected to the first pads 113 and the first ball pads 115. The second vias 118 are connected to the first pads 113. The peripheral ball pads 114 and the second ball pads 116 are connected. Then, referring to FIG. 2B , a plurality of first solder balls 120 are disposed on the upper surface 111 of the substrate 110 , and the first solder balls 120 are bonded to the peripheral ball pads 114 .

Then, referring to FIG. 2C, a wafer 130 is disposed on the upper surface 111 of the substrate 110, and the wafer 130 covers the first pads 113. In this embodiment, a plurality of bumps 170 are fixed on one active surface 131 of the wafer 130 and bonded to the first pads 113 such that the wafer 130 is flip-chip bonded to the upper surface of the substrate 110. 111, each bump 170 is soldered to the corresponding first pad 113 by a solder 171. Thereafter, please refer to FIG. 2D, and more specifically, an underfill 180 is formed between the wafer 130 and the substrate 110 to cover the bumps 170.

Then, referring to FIG. 2E, a molding compound 140 is formed on the upper surface 111 of the substrate 110 to seal the wafer 130. The molding compound 140 partially seals the first solder balls 120. The thickness of the sealing body 140 is greater than the height of the wafer 130 but less than the height of the first solder balls 120 to expose the curved surfaces 121 of the first solder balls 120. The above steps of forming the molding compound 140 are as follows. The process steps described in detail in Figures 3A through 3C are described in detail later.

Then, referring to FIG. 2F, a plurality of second solder balls 150 and a plurality of third solder balls 160 are disposed on the lower surface 112 of the substrate 110, and the second solder balls 150 are coupled to the first balls. Pads 115, the third solder balls 160 are coupled to the second ball pads 116. Finally, a singulation step is performed to form a plurality of semiconductor wafer package structures 100 as shown in FIG.

3A to 3C are schematic cross-sectional views showing elements of the secondary steps of the formation process of the mold encapsulant 140 in the method of fabricating the semiconductor wafer package structure 100.

First, referring to FIG. 3A, a mold clamping operation is performed to place an upper mold 310 above the substrate 110. A surface of the upper mold 310 is attached with a release film 311 to the substrate. The gap of 110 is greater than the height of the wafer 130 but less than the height of the first solder balls 120. The first solder balls 120 are partially trapped in the release film 311.

Thereafter, referring to FIG. 3B, a glue injection operation is performed to cause the mold sealant precursor 140A to be infused into the gap. More specifically, the “gap” refers to the gap between the upper surface 111 of the substrate 110 and the release film 311 after the mold clamping, and the glue injection space excludes the wafer 130, the underfill 180, and the first A solder ball 120 occupies space.

Thereafter, referring to FIG. 3C, a gel curing operation is performed to cure the molding compound precursor 140A to the molding compound 140, and the molding compound 140 is separated from the upper mold 310 and the release film. 311. More specifically, removing the upper mold After the mold 310 and the release film 311, the mold seal 140 seals the wafer 130 and the mold seal 140 partially seals the first solder balls 120 to expose the arcs of the first solder balls 120. Face 121.

According to a second embodiment of the present invention, another double-sided ball-on semiconductor chip package structure 200 is illustrated in a cross-sectional view of FIG. 4, wherein the components of the same name and function corresponding to the first embodiment are first specific. The component numbers of the embodiments are shown, and the details of the details are not described again. The semiconductor chip package structure 200 includes a substrate 110, a plurality of first solder balls 120, a wafer 130, a molding compound 140, a plurality of second solder balls 150, and a plurality of third solder balls 160.

Referring to FIG. 4, the substrate 110 has an upper surface 111 and a lower surface 112. The upper surface 111 is provided with a plurality of first pads 113 and a plurality of peripheral ball pads 114. The lower surface 112 is provided with a plurality of The first ball pad 115 and the plurality of second ball pads 116 further comprise a plurality of first through holes 117 and a plurality of second conductive holes 118, and the first conductive holes 117 are connected to the first The pad 113 and the first ball pads 115 are connected to the peripheral ball pads 114 and the second ball pads 116. In the embodiment, the first pads 113 are thermally conductive pads, and the first vias 117 are thermally conductive holes. The upper surface 111 of the substrate 110 can be further provided with a plurality of second pads 219, which can be located between the first pads 113 and the peripheral ball pads 114 as signal transmission pads.

The first solder balls 120 are bonded to the peripheral ball pads 114. The wafer 130 is disposed on the upper surface 111 of the substrate 110 and covers the first pads 113. In this embodiment, one back surface 132 of the wafer 130 can utilize a die bond layer. 280 is attached to the upper surface 111 of the substrate 110 and covers the first pads 113. The plurality of bonding wires 270 can connect the plurality of pads 233 of the wafer 130 on the active surface thereof to the second pads. 219. More specifically, the bonding wires 270 can be formed by wire bonding (WB) to electrically connect the pads 233 of the die 130 to the second pads 219.

The molding compound 140 is formed on the upper surface 111 of the substrate 110 to seal the wafer 130 and the bonding wires 270. In addition, the molding compound 140 partially seals the first solder balls 120. The thickness of the molding compound 140 is greater than the height of the wafer 130 but less than the height of the first solder balls 120 to reveal the The arc faces 121 of the first solder balls 120. The second solder balls 150 are bonded to the first ball pads 115. The third solder balls 160 are bonded to the second ball pads 116.

Therefore, the present invention can achieve a reduction in the risk of falling the ball during the process of joining the double-sided solder balls, and can also eliminate the laser drilling process to avoid surface damage of the package stack soldering surface.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus equivalent changes made in the claims of the present invention are still within the scope of the present invention.

100‧‧‧Semiconductor chip package construction

110‧‧‧Substrate

111‧‧‧Upper surface

112‧‧‧ lower surface

113‧‧‧First mat

114‧‧‧around ball pad

115‧‧‧First ball mat

116‧‧‧second ball mat

117‧‧‧First via

118‧‧‧Second via

120‧‧‧First solder ball

121‧‧‧ curved surface

130‧‧‧ wafer

131‧‧‧Active surface

132‧‧‧Back

140‧‧‧Mold sealant

150‧‧‧second solder ball

160‧‧‧ third solder ball

170‧‧‧Bumps

171‧‧‧ solder

180‧‧‧ underfill

Claims (8)

A semiconductor wafer package structure for double-sided ball implantation, comprising: a substrate having an upper surface and a lower surface, wherein the upper surface is provided with a plurality of first pads and a plurality of peripheral ball pads, wherein the lower surface is provided with a plurality of first ball pads and a plurality of second ball pads, the substrate further comprising a plurality of first via holes and a plurality of second via holes, wherein the first via holes are connected to the first pads and the plurality of first pads a first ball pad, the second conductive holes are connected to the peripheral ball pads and the second ball pads; a plurality of first solder balls are bonded to the peripheral ball pads; a wafer is disposed on the substrate The upper surface covers the first pads; a molding compound is formed on the upper surface of the substrate to seal the wafer, and the molding system partially seals the first solder balls. The molding compound has a vertical thickness on the upper surface of the substrate, a vertical distance from the back surface of the wafer to the upper surface of the substrate is less than the vertical thickness, and the height of each of the first solder balls is greater than the vertical Thickness and the vertical distance to reveal the A first solder balls arc; a second plurality of solder balls based on the plurality of first engaging ball pads; and a plurality of third ball, based on the plurality of second engaging ball pads. The semiconductor chip package structure of the double-sided ball implant according to claim 1, further comprising a plurality of bumps fixed on an active surface of the wafer and bonded to the first pads, so that the A wafer is flip-chip bonded to the upper surface of the substrate. A semiconductor wafer package structure for double-sided ball implantation as described in claim 2 And an underfill film is formed between the wafer and the substrate to cover the bumps. The semiconductor wafer package structure of the double-sided ball-planting method of claim 1, wherein a back surface of the wafer is attached to the upper surface of the substrate by a die-bonding layer and covers the first pads. The upper surface of the substrate is further provided with a plurality of second pads disposed between the first pads and the peripheral ball pads, and the plurality of bonding wires are connected to the plurality of pads of the wafer to the Some second pads. The double-sided ball-molding semiconductor chip package structure according to any one of claims 1 to 4, wherein a distance from the first solder balls to a side of the adjacent side of the wafer is not more than the first The average gap of a solder ball. A method for manufacturing a semiconductor wafer package structure for double-sided ball implantation, comprising: providing a substrate having an upper surface and a lower surface, wherein the upper surface is provided with a plurality of first pads and a plurality of peripheral ball pads, The lower surface is provided with a plurality of first ball pads and a plurality of second ball pads. The substrate has a plurality of first conductive vias and a plurality of second conductive vias, and the first conductive vias are connected to the first conductive vias. a pad and the first ball pads, the second via holes connecting the peripheral ball pads and the second ball pads; and providing a wafer on the upper surface of the substrate, the wafer covering the a first pad; a plurality of first solder balls are disposed on the upper surface of the substrate, the first solder balls are bonded to the peripheral ball pads; and a molding compound is formed on the upper surface of the substrate, To seal the wafer, the mold encapsulation system partially seals the first solder balls, and the thickness of the mold sealant And the height of the first solder balls is greater than the height of the first solder balls to expose the arc surface of the first solder balls, wherein the step of forming the mold colloid comprises: performing a mold clamping operation, An upper mold is disposed above the substrate, and a surface of the upper mold is attached with a release film, and a gap between the release film and the substrate is greater than a height of the wafer but less than a height of the first solder balls. The first solder balls are partially embedded in the release film; a glue injection operation is performed to inject the mold body into the gap; and a glue curing operation is performed to make the mold The sealant is pre-cured to the mold sealant, and the mold sealant is separated from the upper mold and the release film; and a plurality of second solder balls and a plurality of third solder balls are disposed on the lower surface of the substrate The second solder balls are bonded to the first ball pads, and the third solder balls are bonded to the second ball pads. The method of manufacturing a semiconductor wafer package structure of a double-sided ball according to claim 6, wherein in the step of disposing the wafer, a plurality of bumps are fixed on one active surface of the wafer and bonded to The first pads are flip-chip bonded to the upper surface of the substrate. The method for manufacturing a semiconductor wafer package structure of a double-sided ball according to claim 7, further comprising: forming an underfill between the wafer and the substrate to cover the bumps.