CN116936365A - 一种氧化物半导体tft器件的制造方法 - Google Patents

一种氧化物半导体tft器件的制造方法 Download PDF

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CN116936365A
CN116936365A CN202310857133.XA CN202310857133A CN116936365A CN 116936365 A CN116936365 A CN 116936365A CN 202310857133 A CN202310857133 A CN 202310857133A CN 116936365 A CN116936365 A CN 116936365A
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陈伟
陈鑫
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CPT Technology Group Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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Abstract

一种氧化物半导体TFT器件的制造方法,包括:在玻璃基板上采用PVD方式沉积一层第一金属层,即栅极金属层;在栅极金属层上采用CVD方式沉积一层第一绝缘层,即栅极绝缘层;在栅极绝缘层上采用PVD方式沉积一层有源层,在有源层的边缘沟道位置形成两个GND状态的第二金属层;在有源层上方采用PVD方式沉积一层第二金属层,并进行相应的图案化处理,形成源极和漏极。本发明通过在有源层的边缘沟道位置增加两个GND状态的第二金属层,可改善TFT边缘沟道的形成,避免Hump效应,从而提升器件稳定性。

Description

一种氧化物半导体TFT器件的制造方法
技术领域
本发明属于液晶显示面板的TFT(阵列基板)的制造技术领域,具体是指一种氧化物半导体TFT器件的制造方法。
背景技术
现有应用于液晶显示面板中的TFT主要由栅极金属层、栅极绝缘层、有源层和源漏极金属层四个部分组成,TFT好比一个开关,作用是让特定的信号写入特定的画素电极并且维持信号保持不变。从结构上来看,TFT器件可分为ESL结构和BCE结构,差别在于ESL结构多了一层ES层,以现有主流的IGZO-TFT为例,ES层的作用是防止源漏极蚀刻对有源层(IGZO)的影响,但不可避免,多一道ES制程,不仅增加了光罩数量,而且增加了一道阵列系列制程,成膜/曝光/显影/蚀刻/剥膜。为此,通过一系列的制程优化及器件开发,生产上主要还是会选择结构更为紧凑的BCE结构,如图1至图3所示。
然而,IGZO-TFT同常规有源层a-Si TFT、LTPS-TFT一样,常态下,其TFT器件的电性虽然很稳定,但是经过高温正向或负向偏移测试后,其TFT器件的I-V曲线极易出现hump(驼峰)效应,不仅影响到面板显示曲内单颗像素的显示驱动,而且损害到GOA电路正常级传驱动,使面板无法正常驱动,画面显示异常。
Hump效应业内通常称为驼峰效应,TFT在正常驱动下,源漏极间会形成有效的TFT沟道,称为主要TFT,而Hump效应的存在,表明有源层的边缘也形成等效寄生晶体管结构,称为边缘TFT。此时漏极电流可分解为主要TFT电流和边缘TFT电流:Id=Id(main)+Id(edge)。通常来说,边缘TFT占总体电流比例不高了,可忽略不计,但是一旦形成,已经影响到了TFT的正常驱动,出现漏电流现象。
如图4所示,TFT正常驱动下,当栅极施以正电压时,栅压在栅绝缘层中产生电场,电场方向由栅极指向半导体表面,并在表面处产生感应电荷。当达到强反型时(即达到开启电压时),源、漏间加上电压就会有载流子通过沟道。当源漏电压很小时,导电沟道近似为一恒定电阻,漏电流随源漏电压增加而线性增大。当源漏电压很大时,它会对栅电压产生影响,使得栅绝缘层中电场由源端到漏端逐渐减弱,半导体表面反型层中电子由源端到漏端逐渐减小,沟道电阻随着源漏电压增大而增加。漏电流增加变得缓慢,对应线性区向饱和区过渡。源漏极间会形成稳定的载流子沟道,为主要TFT。现有的IGZO为N型半导体,故其形成沟道载流子以电子为主。而同样边缘TFT载流子的存在,边缘TFT极易形成边缘TFT。
发明内容
本发明所要解决的技术问题在于提供一种氧化物半导体TFT器件的制造方法。
本发明是这样实现的:
一种氧化物半导体TFT器件的制造方法,包括如下步骤:
在玻璃基板上采用PVD方式沉积一层第一金属层,即栅极金属层;
在栅极金属层上采用CVD方式沉积一层第一绝缘层,即栅极绝缘层;
在栅极绝缘层上采用PVD方式沉积一层有源层,在有源层的边缘沟道位置形成两个GND状态的第二金属层;
在有源层上方采用PVD方式沉积一层第二金属层,并进行相应的图案化处理,形成源极和漏极。
进一步地,所述栅极金属层,为Mo/Al/Mo。
进一步地,所述栅极绝缘层,为SiOx。
进一步地,所述有源层,为IGZO。
进一步地,所述源极和漏极,为Mo/Al/Mo。
本发明的优点在于:本发明通过在有源层的边缘沟道位置增加两个GND状态的第二金属层,可改善TFT边缘沟道的形成,避免Hump效应,从而提升器件稳定性。
附图说明
下面参照附图结合实施例对本发明作进一步的描述。
图1是现有技术TFT器件的结构示意图。
图2是图1的A-A'剖视图。
图3是图1的B-B'剖视图。
图4是现有技术TFT驱动状态下模拟沟道载流子电荷传输示意图。
图5是本发明的TFT器件的结构示意图。
图6是图5的A-A'剖视图。
图7是图5的B-B'剖视图。
图8是本发明TFT驱动状态下模拟沟道载流子电荷传输示意图。
附图标记:100-主TFT沟道载流子,200-边缘TFT载流子,1-玻璃基板,2-栅极金属层,3-栅极绝缘层,4-有源层,5-源极,6-漏极,7-GND状态的第二金属层。
具体实施方式
如图5至图7所示,一种氧化物半导体TFT器件的制造方法,包括如下步骤:
在玻璃基板1上采用PVD方式沉积一层第一金属层,即栅极金属层2,可选Mo/Al/Mo;
在栅极金属层2上采用CVD方式沉积一层第一绝缘层,即栅极绝缘层3,可选SiOx;
在栅极绝缘层3上采用PVD方式沉积一层有源层4,可选IGZO,在有源层4的边缘沟道位置形成两个GND状态的第二金属层7;
在有源层4上方采用PVD方式沉积一层第二金属层,并进行相应的图案化处理,形成源极5和漏极6(选Mo/Al/Mo)。
饱和区TFT电流驱动公式:Id=(W/2L)Cμ(Vg-Vth)2
其中,d:饱和区漏极电流,W:沟道宽度,L:沟道长度,C:单位面积栅氧化层电容,μ:有源层电子迁移率,Vg:栅极电压,Vth:阈值电压。
饱和区TFT电流驱动公式说明主和边缘TFT的Id大小主要受沟道的W、L影响,本发明通过在有源层的边缘沟道位置增加两个GND状态的第二金属层,可改善TFT边缘沟道的形成(如图8所示),避免Hump效应,从而提升器件稳定性。
上述实施例和图式并非限定本发明的形态和式样,任何所属技术领域的普通技术人员对其所做的适当变化或修饰,皆应视为不脱离本发明的专利范畴。

Claims (5)

1.一种氧化物半导体TFT器件的制造方法,其特征在于:包括如下步骤:
在玻璃基板上采用PVD方式沉积一层第一金属层,即栅极金属层;
在栅极金属层上采用CVD方式沉积一层第一绝缘层,即栅极绝缘层;
在栅极绝缘层上采用PVD方式沉积一层有源层,在有源层的边缘沟道位置形成两个GND状态的第二金属层;
在有源层上方采用PVD方式沉积一层第二金属层,并进行相应的图案化处理,形成源极和漏极。
2.如权利要求1所述的一种氧化物半导体TFT器件的制造方法,其特征在于:所述栅极金属层,为Mo/Al/Mo。
3.如权利要求1所述的一种氧化物半导体TFT器件的制造方法,其特征在于:所述栅极绝缘层,为SiOx。
4.如权利要求1所述的一种氧化物半导体TFT器件的制造方法,其特征在于:所述有源层,为IGZO。
5.如权利要求1所述的一种氧化物半导体TFT器件的制造方法,其特征在于:所述源极和漏极,为Mo/Al/Mo。
CN202310857133.XA 2023-07-13 2023-07-13 一种氧化物半导体tft器件的制造方法 Pending CN116936365A (zh)

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