CN116917889A - 一种寄生电阻电容参数提取方法及装置 - Google Patents
一种寄生电阻电容参数提取方法及装置 Download PDFInfo
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- CN116917889A CN116917889A CN202180094788.5A CN202180094788A CN116917889A CN 116917889 A CN116917889 A CN 116917889A CN 202180094788 A CN202180094788 A CN 202180094788A CN 116917889 A CN116917889 A CN 116917889A
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- 230000003071 parasitic effect Effects 0.000 title claims abstract description 128
- 238000000605 extraction Methods 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 claims description 88
- 238000004590 computer program Methods 0.000 claims description 27
- 238000003860 storage Methods 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 4
- 238000013461 design Methods 0.000 abstract description 28
- 230000006870 function Effects 0.000 description 25
- 230000008569 process Effects 0.000 description 22
- 238000004088 simulation Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- 238000012545 processing Methods 0.000 description 10
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 238000004891 communication Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000002070 nanowire Substances 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 239000011295 pitch Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000002135 nanosheet Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 101100007418 Caenorhabditis elegans cox-5A gene Proteins 0.000 description 1
- 239000004429 Calibre Substances 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000000802 evaporation-induced self-assembly Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012804 iterative process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002060 nanoflake Substances 0.000 description 1
- 239000002064 nanoplatelet Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 235000013599 spices Nutrition 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
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- Databases & Information Systems (AREA)
- Mathematical Physics (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2021/083019 WO2022198571A1 (fr) | 2021-03-25 | 2021-03-25 | Procédé et dispositif d'extraction de paramètres de résistance et de capacité parasites |
Publications (1)
Publication Number | Publication Date |
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CN116917889A true CN116917889A (zh) | 2023-10-20 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN202180094788.5A Pending CN116917889A (zh) | 2021-03-25 | 2021-03-25 | 一种寄生电阻电容参数提取方法及装置 |
Country Status (2)
Country | Link |
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CN (1) | CN116917889A (fr) |
WO (1) | WO2022198571A1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116187269B (zh) * | 2023-03-02 | 2024-06-21 | 深圳华大九天科技有限公司 | 一种多导体系统的寄生电容参数提取方法、装置及存储介质 |
CN116881515B (zh) * | 2023-09-07 | 2023-12-19 | 杭州行芯科技有限公司 | 对不同算法求解的电容结果进行比较的方法及电子设备 |
CN117371387B (zh) * | 2023-12-08 | 2024-02-13 | 浙江集迈科微电子有限公司 | 集成电路器件版图参数化构建方法装置、存储介质和终端 |
CN117454808B (zh) * | 2023-12-25 | 2024-05-28 | 杭州行芯科技有限公司 | 一种寄生电容信息的获取方法、装置及电子设备 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004240801A (ja) * | 2003-02-07 | 2004-08-26 | Renesas Technology Corp | 半導体集積回路の寄生容量抽出装置及び寄生容量抽出方法 |
CN101211376A (zh) * | 2006-12-26 | 2008-07-02 | 北京中电华大电子设计有限责任公司 | 一种寄生参数提取工具专用的版图数据格式 |
CN102222131A (zh) * | 2011-05-16 | 2011-10-19 | 华东师范大学 | 后道互连延迟模型的提取及验证方法 |
KR20170133750A (ko) * | 2016-05-26 | 2017-12-06 | 삼성전자주식회사 | 집적 회로의 설계를 위한 컴퓨터 구현 방법 |
CN108959666B (zh) * | 2017-05-17 | 2021-10-22 | 中国科学院微电子研究所 | 集成电路设计方法及装置、芯片版图分解和着色方法及装置 |
CN108399299A (zh) * | 2018-03-02 | 2018-08-14 | 京东方科技集团股份有限公司 | 一种集成电路物理版图生成方法及装置 |
CN112131830B (zh) * | 2020-09-25 | 2021-06-15 | 成都海光微电子技术有限公司 | 一种寄生参数验证方法、装置、电子设备和存储介质 |
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2021
- 2021-03-25 WO PCT/CN2021/083019 patent/WO2022198571A1/fr active Application Filing
- 2021-03-25 CN CN202180094788.5A patent/CN116917889A/zh active Pending
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WO2022198571A1 (fr) | 2022-09-29 |
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