CN116896516A - Time synchronization precision testing system and method based on pulse per second method - Google Patents
Time synchronization precision testing system and method based on pulse per second method Download PDFInfo
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Abstract
The application relates to a time synchronization precision test system and a method based on a pulse per second method, wherein the system comprises a hardware module and a software module arranged in a computer, the hardware module is connected with a pulse per second signal of a tested piece through an acquisition interface, and information interaction is realized between the hardware module and the computer through an Ethernet; the hardware module provides a sufficient number of acquisition channels and is responsible for capturing the second pulse signals, and the second pulse edge-changing timestamp information is transmitted in real time through the Ethernet; the software module runs on the computer, receives the data sent by the hardware module by using the computer card, executes a special algorithm to process the data and calculate the clock synchronization precision of each slave channel, monitors the test process and the test data in real time through the man-machine interaction interface, and finally generates a test report and a data record file. The system supports multichannel pulse per second signal acquisition, and can efficiently and conveniently realize the test of the clock synchronization precision of the vehicle-mounted network.
Description
Technical Field
The application relates to the technical fields of clock synchronization technology and time synchronization precision test of a vehicle-mounted Ethernet controller, in particular to a time synchronization precision test system and method based on a second pulse method.
Background
The automobile industry develops to the intelligent and networking direction, and the realization of applications such as intelligent automobile sensor data fusion, driving data cloud end uploading, remote monitoring and diagnosis and the like depends on high-precision time synchronization of the whole automobile network system to a certain extent. In order to guarantee the high precision requirement of network time synchronization, accurate test of time synchronization performance and stability is required.
In the prior art, the simplest and most commonly used black box testing method is a 1PPS testing method, namely, capturing integer pulse per second signals output by a tested node in a time synchronization system based on synchronization time, and measuring the time synchronization precision of the tested slave node relative to a master clock node by comparing the phase difference of the rising edges of the pulse per second.
According to the 1PPS test method aiming at the time synchronization system, an oscilloscope is often used as a test tool, the second pulse signals output by the nodes participating in synchronization are collected, the rising edge phase difference of the slave node and the master node is compared by reading the rising edge occurrence time of the tested node, and therefore the time synchronization precision is calculated. But using an oscilloscope as the test device has the following drawbacks:
1. the number of the tested nodes of the time synchronization system can reach 20+, the physical channels of the oscilloscopes are generally 4, and a few expensive oscilloscopes can reach 8 channels, but the requirements of the vehicle-mounted network system level test can not be met.
2. In order to realize high-precision test, the time scale of the oscilloscope is generally microsecond or even nanosecond, but due to the limitation of storage depth of the oscilloscope, the oscilloscope can hardly realize long-time high-frequency signal acquisition and data storage, and cannot realize stability test of synchronous precision.
The phase difference of the rising edge of the tested node is calculated by requiring a tester to manually move the cursors and read the time difference between the cursors of each channel, and repeated measurement and statistics are required to be carried out by the tester to obtain a more accurate result, so that the manual participation is high, and the automatic test cannot be realized. A few advanced oscilloscopes have automatic signal triggering and measuring functions, but are expensive.
Disclosure of Invention
Aiming at the defects existing in the prior art, the application aims to provide a time synchronization precision test system and a time synchronization precision test method based on a pulse per second method, which support network clock synchronization precision test based on a 1PPS method and can realize node level and system level test. The system also has the functions of high-resolution sampling of multichannel second pulse signals, real-time calculation and display of synchronous precision, data statistics and storage and the like, thereby realizing automatic test of clock synchronous precision.
The above object of the present application is achieved by the following technical solutions:
the time synchronization precision testing system based on the pulse per second method comprises a hardware module and a software module arranged in a computer, wherein the hardware module is connected with a pulse per second signal of a tested piece through an acquisition interface, and information interaction is realized between the hardware module and the computer through an Ethernet;
the hardware module provides a sufficient number of acquisition channels and is responsible for capturing a second pulse signal, and the second pulse time-varying timestamp information is transmitted in real time through the Ethernet;
the software module runs on the computer, receives the data sent by the hardware module by using the computer card, executes a special algorithm to process the data and calculate the clock synchronization precision of each slave channel, monitors the test process and the test data in real time through the man-machine interaction interface, and finally generates a test report and a data record file.
The present application may be further configured in a preferred example to: the hardware module is internally provided with a high-performance processing chip and a high-resolution clock module, and time stamps of rising edges and falling edges of pulse signals of all channels are obtained.
The present application may be further configured in a preferred example to: the hardware module comprises a power supply module, a communication module, a field programmable gate array unit, a storage unit, an acquisition processing module and an acquisition state LED;
the field programmable gate array unit is respectively connected with the power supply module, the communication module, the storage unit, the acquisition processing module and the acquisition state LED, the power supply module is connected with the storage unit, and an acquisition interface is arranged on the acquisition processing module.
The present application may be further configured in a preferred example to: in the hardware module in question,
the power module comprises: the power supply system is used for adapting to a 12v/24v power supply system of an automobile, converting external 9-32v direct current power supply into 3.3v and 5v hardware module internal circuit required voltage, and supplying power to other modules;
the communication module: the system consists of an RJ45 interface, an Ethernet physical layer chip and related circuits, realizes Ethernet communication with a computer card, and is used for sending pulse per second edge time stamp data and receiving control data from a software module;
the field programmable gate array unit: the core processor chip of the hardware module realizes high-speed concurrent acquisition of the multi-channel pulse signals by utilizing the advantages of high sampling rate and concurrent processing of the field programmable gate array unit, sampling logic operated in the field programmable gate array unit is provided with a frame convenient to expand, and 1-n paths of pulse signal processing can be supported under the condition of enough logic resources;
the storage unit: the peripheral memory chip is a main processor and comprises double-rate synchronous dynamic random memory, a flash memory and an embedded multimedia card, and is mainly used for storing and running a system and a program;
the acquisition processing module is used for: the high-speed connector and the processing circuit are connected with the second pulse signal through the acquisition interface and are used for pulse signal level conversion, impedance matching and overcurrent protection; the processing circuit uses a high-performance chip to reduce the influence of signal delay as much as possible;
the acquisition state LED: and each channel of pulse signal acquisition state indicator lamp displays the acquisition state.
The present application may be further configured in a preferred example to: the sampling logic of the field programmable gate array unit operates in the field programmable gate array of the hardware module, and is provided with an expandable frame which can expand the pulse signal acquisition channel according to the requirement;
the field programmable logic gate array unit comprises a clock module, a plurality of PPS detection modules, a plurality of first-in first-out queue modules, a data processing and equipment control module, an Ethernet communication module and an LED control module;
the data processing and equipment control module is respectively connected with the Ethernet communication module, the LED control module, the clock module, the PPS detection modules and the first-in first-out queue modules, each first-in first-out queue module is respectively connected with one PPS detection module, and each PPS detection module is respectively connected with the clock module.
The present application may be further configured in a preferred example to: in the field programmable gate array unit,
the clock module: the clock module is used for providing a hardware sampling clock, realizing a high-frequency clock signal (more than or equal to 250 MHz) based on a phase-locked loop technology and taking the high-frequency clock signal as a timing reference of the clock module; the clock timer is 8 bytes (4 bytes second timer, 4 bytes nanosecond timer), when the nanosecond timer exceeds 1e9, the second timer is added with 1, and the nanosecond timer starts counting from zero;
the PPS detection module is used for: the method is responsible for detecting rising edges and falling edges of second pulse signals, recording edge change moments, writing edge change time stamps into a first-in first-out queue module, and instantiating one detection module to expand one pulse acquisition channel, wherein each acquisition channel corresponds to one detection module, and the channels are mutually independent to realize parallel sampling;
the first-in first-out queue module: each channel corresponds to one first-in first-out queue module and buffers the time stamp data;
the data processing and equipment control module: the time stamp data read from the first-in first-out queue module corresponding to each channel is packed and transmitted to the Ethernet communication module; analyzing a control data packet from the Ethernet communication module to control other modules;
the Ethernet communication module: the method comprises the steps of responsible for encapsulation and decapsulation of an Ethernet frame, encapsulating a time stamp data packet of a pulse signal in the Ethernet frame and sending out the time stamp data packet; unpacking the received Ethernet control data;
the LED control module comprises: and controlling the on-off state of the light emitting diode in the acquisition state.
The present application may be further configured in a preferred example to: the software module comprises a device discovery module, a communication module, a data processing module, a business logic module, an application programming interface and a user interface;
the software module runs in a computer and is responsible for processing the edge time stamp data of each channel in real time, calculating clock synchronization precision and realizing data storage and report generation.
The present application may be further configured in a preferred example to: in the case of the software module in question,
the device discovery module: a hardware module for discovering in a network;
the communication module: the method is responsible for serialization and deserialization of application data, and communication with a hardware module is realized based on a system TCP/IP protocol stack;
the data processing module: is responsible for buffering and storing data from the hardware module;
the business logic module: the processing module is a core processing module of the software module and is responsible for analyzing and processing data, such as judging whether a pulse signal is effective or not and whether a slave channel signal is relevant or not, and further calculating the time synchronization precision of each slave channel;
the application programming interface: the programming interface is used for a user interface or a third party to call and supports a plurality of programming languages of C#, C++, java;
the user interface: and the system is responsible for man-machine interaction and realizes the functions of equipment configuration, file operation and data graphic display.
The present application may be further configured in a preferred example to: the special algorithm for calculating the synchronization precision of the software module comprises the following steps:
step 1: after the test is started, the service logic module circularly receives the data from the data processing module, and the data of each channel is processed independently;
step 2: each channel firstly determines a first effective signal, judges that logic is three continuous received signals, and considers that the first PPS signal is effective PPS if the difference between rising edge time and high level duration time of the three continuous received signals are within a set range;
step 3: the validity judgment is needed to be carried out every time the PPS signal is received, the judgment logic is that the difference between the rising edge time of the current PPS signal and the rising edge time of the valid PPS signal is within the set range, and if the current signal is invalid, the exception processing is carried out;
step 4: if the test channel is a main channel, buffering effective signal data, otherwise, performing related judgment of a secondary channel signal, wherein the main channel is a reference channel for calculating the synchronous precision, namely the difference between the rising edges of the secondary channel and the main channel is the synchronous precision of the secondary channel, and only one channel is allowed to be selected as the main channel;
step 5: performing time synchronization precision calculation from channel signal correlation judgment success, buffering calculation results and original data, and performing exception processing if signal correlation judgment fails;
step 6: and before the measurement is not finished, the data processing flow is circularly executed.
In this embodiment, the special algorithm is a PPS signal data processing algorithm, so as to implement PPS signal validity judgment, signal correlation interpretation from a channel, and signal exception processing, thereby ensuring that synchronization accuracy calculation is effectively completed.
A method of testing a time synchronization accuracy testing system based on a pulse-per-second method according to any of claims 1-9, comprising the steps of:
step S1: the hardware module acquisition interface is connected with all the measured node second pulse signals;
step S2: the hardware module is connected with the computer through the Ethernet;
step S3: the hardware module is connected with a power supply through a power interface to start power supply;
step S4: the method comprises the steps of running a software module on a computer, and firstly configuring a hardware module;
step S5: starting a test, wherein a hardware module starts to acquire a pulse signal output by a tested node, and transmits acquired time stamp data to a software module;
step S6: the software module analyzes and processes the data in real time, and automatically generates a test report after the test is finished.
In summary, the present application includes at least one of the following beneficial technical effects:
the application discloses a time synchronization precision testing system and a time synchronization precision testing method based on a pulse per second method, which support multichannel pulse per second signal acquisition and can efficiently and conveniently realize the test of the clock synchronization precision of a vehicle-mounted network. The beneficial effects are as follows:
1. the high-performance processing chip and the processing circuit support the high-resolution acquisition of more channel second pulse signals, realize nanosecond test precision and meet the synchronous high-precision test requirement of the whole vehicle clock;
2. recording test data by using a computer storage space, supporting continuous long-time test, and realizing clock synchronization precision stability test;
3. the development of a special algorithm completes data processing and automatic calculation of synchronous precision, supports automatic test, has high test efficiency, and can avoid test errors caused by artificial factors; compared with an expensive oscilloscope purchased, the special testing device for the clock synchronization precision can reduce the testing cost.
Drawings
Fig. 1 is a block diagram of the overall system architecture of the present application.
Fig. 2 is a block diagram of a hardware module according to the present application.
Fig. 3 is a block diagram of PFGA sampling logic of the present application.
Fig. 4 is a block diagram of the software module structure of the present application.
Fig. 5 is a business logic flow diagram of a specific algorithm of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application; it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments, and that all other embodiments obtained by persons of ordinary skill in the art without making creative efforts based on the embodiments in the present application are within the protection scope of the present application.
In the description of the present application, it should be noted that the positional or positional relationship indicated by the terms such as "upper", "lower", "inner", "outer", "top/bottom", etc. are based on the positional or positional relationship shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the term "connected" should be construed broadly and may be a fixed connection, a removable connection, or an integral connection; the signal connection and the electric connection can be adopted; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
Embodiment one:
referring to fig. 1, the time synchronization precision testing system based on the pulse per second method disclosed by the application comprises a hardware module and a software module arranged in a computer, wherein the hardware module is connected with a pulse per second signal of a tested piece through an acquisition interface, and information interaction is realized between the hardware module and the computer through an Ethernet;
the hardware module provides a sufficient number of acquisition channels and is responsible for capturing the pulse-per-second signals; a high-performance processing chip and a high-resolution clock module are arranged in the hardware module, and time stamps of rising edges and falling edges of pulse signals of all channels are obtained; transmitting the second pulse time-varying timestamp information in real time through the Ethernet;
the software module runs on the computer, receives the data sent by the hardware module by using the computer card, executes a special algorithm to process the data and calculate the clock synchronization precision of each slave channel, monitors the test process and the test data in real time through the man-machine interaction interface, and finally generates a test report and a data record file.
Referring to fig. 2, the hardware module includes a power module, a communication module, a field programmable gate array unit, a storage unit, an acquisition processing module, and an acquisition status LED; the field programmable gate array unit is respectively connected with the power module, the communication module, the storage unit, the acquisition processing module and the acquisition state LED, the power module is connected with the storage unit, and the acquisition processing module is provided with an acquisition interface.
In the hardware module(s) of the present application,
and a power supply module: the power supply system is used for adapting to a 12v/24v power supply system of an automobile, converting external 9-32v direct current power supply into 3.3v and 5v hardware module internal circuit required voltage, and supplying power to other modules;
and a communication module: the system consists of an RJ45 interface, an Ethernet physical layer chip and related circuits, realizes Ethernet communication with a computer card, and is used for sending pulse per second edge time stamp data and receiving control data from a software module;
a field programmable gate array unit (FPGA): the device is a core processor chip of a hardware module, realizes high-speed concurrent acquisition of multichannel pulse signals by utilizing the advantages of high sampling rate, concurrent processing and the like of an FPGA, has a frame convenient to expand by sampling logic operated in the FPGA, and can support 1-n paths of pulse signal processing under the condition of enough logic resources;
and a storage unit: the peripheral memory chip is a main processor and comprises double rate synchronous dynamic random access memory (DDR SDRAM), flash memory (Flash) and an embedded multimedia card (eMMC), and is mainly used for storing and running a system and a program;
and the acquisition and processing module is used for: the high-speed connector and the processing circuit are connected with the second pulse signal through the acquisition interface and are used for pulse signal level conversion, impedance matching and overcurrent protection; the processing circuit uses a high-performance chip to reduce the influence of signal delay as much as possible;
collecting state LEDs: and each channel of pulse signal acquisition state indicator lamp displays the acquisition state.
Referring to fig. 3, the sampling logic of the field programmable gate array unit operates in the field programmable gate array of the hardware module, and is provided with an expandable frame, so that the pulse signal acquisition channel can be expanded as required; the field programmable gate array unit comprises a clock module, a plurality of PPS detection modules, a plurality of first-in first-out queue modules, a data processing and equipment control module, an Ethernet communication module and an LED control module.
The data processing and equipment control module is respectively connected with the Ethernet communication module, the LED control module, the clock module, the PPS detection modules and the first-in first-out queue modules, each first-in first-out queue module is respectively connected with one PPS detection module, and each PPS detection module is respectively connected with the clock module.
In a field programmable gate array unit,
and (3) a clock module: the clock module is used for providing a hardware sampling clock, realizing a high-frequency clock signal (more than or equal to 250 MHz) based on a phase-locked loop technology and taking the high-frequency clock signal as a timing reference of the clock module; the clock timer is 8 bytes (4 bytes second timer, 4 bytes nanosecond timer), when the nanosecond timer exceeds 1e9, the second timer is added with 1, and the nanosecond timer starts counting from zero;
PPS detection module: the method is responsible for detecting rising edges and falling edges of second pulse signals, recording edge transition moments, writing edge transition time stamps into a first-in first-out queue module (FIFO), and instantiating one detection module to expand one pulse acquisition channel, wherein each acquisition channel corresponds to one detection module, and the channels are mutually independent to realize parallel sampling;
a first-in-first-out queue module (FIFO): each channel corresponds to a first-in first-out queue module (FIFO) for buffering time stamp data;
and the data processing and equipment control module is used for: the method comprises the steps of packaging time stamp data read from a first-in-first-out queue module (FIFO) corresponding to each channel and transmitting the time stamp data to an Ethernet communication module; analyzing a control data packet from the Ethernet communication module to control other modules;
an Ethernet communication module: the method comprises the steps of responsible for encapsulation and decapsulation of an Ethernet frame, encapsulating a time stamp data packet of a pulse signal in the Ethernet frame and sending out the time stamp data packet; unpacking the received Ethernet control data;
and the LED control module is used for: and controlling the on-off state of the light emitting diode in the acquisition state.
Referring to fig. 4, the software modules include a device discovery module, a communication module, a data processing module, a business logic module, an application programming interface, a user interface; the software module runs in the computer, is responsible for processing the edge time stamp data of each channel in real time, calculating the clock synchronization precision, and realizing data storage and report generation.
In the software module(s) of the present application,
and a device discovery module: a hardware module for discovering in a network;
and a communication module: the method is responsible for serialization and deserialization of application data, and communication with a hardware module is realized based on a system TCP/IP protocol stack;
and a data processing module: is responsible for buffering and storing data from the hardware module;
service logic module: the processing module is a core processing module of the software module and is responsible for analyzing and processing data, such as judging whether a pulse signal is effective or not and whether a slave channel signal is relevant or not, and further calculating the time synchronization precision of each slave channel;
application programming interface: the programming interface is used for a user interface or a third party to call and supports a plurality of programming languages of C#, C++, java;
user interface: and the functions of equipment configuration, file operation, data image-text display and the like are realized.
Referring to fig. 5, the software module synchronization accuracy calculation flow includes the following steps:
step 1: after the test is started, the service logic module circularly receives the data from the data processing module, and the data of each channel is processed independently;
step 2: each channel firstly determines a first effective signal, judges that logic is three continuous received signals, and considers that the first PPS signal is effective PPS if the difference between rising edge time and high level duration time of the three continuous received signals are within a set range;
step 3: the validity judgment is needed to be carried out every time the PPS signal is received, the judgment logic is that the difference between the rising edge time of the current PPS signal and the rising edge time of the valid PPS signal is within the set range, and if the current signal is invalid, the exception processing is carried out;
step 4: if the test channel is a main channel, buffering effective signal data, otherwise, performing related judgment of a secondary channel signal, wherein the main channel is a reference channel for calculating the synchronous precision, namely the difference between the rising edges of the secondary channel and the main channel is the synchronous precision of the secondary channel, and only one channel is allowed to be selected as the main channel;
step 5: performing time synchronization precision calculation from channel signal correlation judgment success, buffering calculation results and original data, and performing exception processing if signal correlation judgment fails;
step 6: and before the measurement is not finished, the data processing flow is circularly executed.
Embodiment two:
the application also discloses a test method of the time synchronization precision test system based on the pulse per second method, which comprises the following steps:
step S1: the hardware module acquisition interface is connected with all the measured node second pulse signals;
step S2: the hardware module is connected with the computer through the Ethernet;
step S3: the hardware module is connected with a power supply through a power interface to start power supply;
step S4: the method comprises the steps of running a software module on a computer, and firstly configuring a hardware module;
step S5: starting a test, wherein a hardware module starts to acquire a pulse signal output by a tested node, and transmits acquired time stamp data to a software module;
step S6: the software module analyzes and processes the data in real time, and automatically generates a test report after the test is finished.
The implementation principle of the application is as follows: the application discloses a time synchronization precision testing system and a time synchronization precision testing method based on a pulse per second method, which support multichannel pulse per second signal acquisition and can efficiently and conveniently realize the test of the clock synchronization precision of a vehicle-mounted network. The system supports network clock synchronization precision test based on a 1PPS method, and can realize node level and system level test. The system also has the functions of high-resolution sampling of multichannel second pulse signals, real-time calculation and display of synchronous precision, data statistics and storage and the like, thereby realizing automatic test of clock synchronous precision.
The embodiments of the present application are all preferred embodiments of the present application, and are not intended to limit the scope of the present application in this way, therefore: all equivalent changes in structure, shape and principle of the application should be covered in the scope of protection of the application.
Claims (10)
1. The time synchronization precision testing system based on the pulse per second method is characterized by comprising a hardware module and a software module arranged in a computer, wherein the hardware module is connected with a pulse per second signal of a tested piece through an acquisition interface, and information interaction is realized between the hardware module and the computer through an Ethernet;
the hardware module provides a sufficient number of acquisition channels and is responsible for capturing a second pulse signal, and the second pulse time-varying timestamp information is transmitted in real time through the Ethernet;
the software module runs on the computer, receives the data sent by the hardware module by using the computer card, executes a special algorithm to process the data and calculate the clock synchronization precision of each slave channel, monitors the test process and the test data in real time through the man-machine interaction interface, and finally generates a test report and a data record file.
2. The time synchronization precision testing system based on the pulse per second method according to claim 1, wherein a high-performance processing chip and a high-resolution clock module are arranged in the hardware module, and time stamps of rising edges and falling edges of pulse signals of all channels are obtained.
3. The time synchronization accuracy testing system based on the pulse per second method according to any one of claims 1-2, wherein the hardware module comprises a power module, a communication module, a field programmable gate array unit, a storage unit, an acquisition processing module and an acquisition status LED;
the field programmable gate array unit is respectively connected with the power supply module, the communication module, the storage unit, the acquisition processing module and the acquisition state LED, the power supply module is connected with the storage unit, and an acquisition interface is arranged on the acquisition processing module.
4. A time synchronization accuracy test system based on a pulse per second method according to claim 3, wherein, in said hardware module,
the power module comprises: the power supply system is used for adapting to a 12v/24v power supply system of an automobile, converting external 9-32v direct current power supply into 3.3v and 5v hardware module internal circuit required voltage, and supplying power to other modules;
the communication module: the system consists of an RJ45 interface, an Ethernet physical layer chip and related circuits, realizes Ethernet communication with a computer card, and is used for sending pulse per second edge time stamp data and receiving control data from a software module;
the field programmable gate array unit: the core processor chip of the hardware module realizes high-speed concurrent acquisition of the multi-channel pulse signals by utilizing the advantages of high sampling rate and concurrent processing of the field programmable gate array unit, sampling logic operated in the field programmable gate array unit is provided with a frame convenient to expand, and 1-n paths of pulse signal processing can be supported under the condition of enough logic resources;
the storage unit: the peripheral memory chip is a main processor and comprises double-rate synchronous dynamic random memory, a flash memory and an embedded multimedia card, and is mainly used for storing and running a system and a program;
the acquisition processing module is used for: the high-speed connector and the processing circuit are connected with the second pulse signal through the acquisition interface and are used for pulse signal level conversion, impedance matching and overcurrent protection; the processing circuit uses a high-performance chip to reduce the influence of signal delay as much as possible;
the acquisition state LED: and each channel of pulse signal acquisition state indicator lamp displays the acquisition state.
5. The time synchronization precision test system based on the pulse per second method according to claim 3, wherein the sampling logic of the field programmable gate array unit operates in a field programmable gate array of a hardware module, and is provided with an expandable frame, so that a pulse signal acquisition channel can be expanded as required;
the field programmable logic gate array unit comprises a clock module, a plurality of PPS detection modules, a plurality of first-in first-out queue modules, a data processing and equipment control module, an Ethernet communication module and an LED control module;
the data processing and equipment control module is respectively connected with the Ethernet communication module, the LED control module, the clock module, the PPS detection modules and the first-in first-out queue modules, each first-in first-out queue module is respectively connected with one PPS detection module, and each PPS detection module is respectively connected with the clock module.
6. The system for testing the time synchronization accuracy based on the pulse per second method according to claim 5, wherein in the field programmable gate array unit,
the clock module: the clock module is used for providing a hardware sampling clock, realizing a high-frequency clock signal (more than or equal to 250 MHz) based on a phase-locked loop technology and taking the high-frequency clock signal as a timing reference of the clock module; the clock timer is 8 bytes (4 bytes second timer, 4 bytes nanosecond timer), when the nanosecond timer exceeds 1e9, the second timer is added with 1, and the nanosecond timer starts counting from zero;
the PPS detection module is used for: the method is responsible for detecting rising edges and falling edges of second pulse signals, recording edge change moments, writing edge change time stamps into a first-in first-out queue module, and instantiating one detection module to expand one pulse acquisition channel, wherein each acquisition channel corresponds to one detection module, and the channels are mutually independent to realize parallel sampling;
the first-in first-out queue module: each channel corresponds to one first-in first-out queue module and buffers the time stamp data;
the data processing and equipment control module: the time stamp data read from the first-in first-out queue module corresponding to each channel is packed and transmitted to the Ethernet communication module; analyzing a control data packet from the Ethernet communication module to control other modules;
the Ethernet communication module: the method comprises the steps of responsible for encapsulation and decapsulation of an Ethernet frame, encapsulating a time stamp data packet of a pulse signal in the Ethernet frame and sending out the time stamp data packet; unpacking the received Ethernet control data;
the LED control module comprises: and controlling the on-off state of the light emitting diode in the acquisition state.
7. The time synchronization accuracy testing system based on the pulse per second method according to claim 1, wherein the software modules comprise a device discovery module, a communication module, a data processing module, a business logic module, an application programming interface, and a user interface;
the software module runs in a computer and is responsible for processing the edge time stamp data of each channel in real time, calculating clock synchronization precision and realizing data storage and report generation.
8. A time synchronization accuracy testing system according to claim 7, wherein, in said software module,
the device discovery module: a hardware module for discovering in a network;
the communication module: the method is responsible for serialization and deserialization of application data, and communication with a hardware module is realized based on a system TCP/IP protocol stack;
the data processing module: is responsible for buffering and storing data from the hardware module;
the business logic module: the processing module is a core processing module of the software module and is responsible for analyzing and processing data, such as judging whether a pulse signal is effective or not and whether a slave channel signal is relevant or not, and further calculating the time synchronization precision of each slave channel;
the application programming interface: the programming interface is used for a user interface or a third party to call and supports a plurality of programming languages of C#, C++, java;
the user interface: and the system is responsible for man-machine interaction and realizes the functions of equipment configuration, file operation and data graphic display.
9. A time synchronization accuracy testing system based on the pulse per second method according to any of claims 7 or 8, wherein said software module synchronization accuracy calculation specific algorithm comprises the steps of:
step 1: after the test is started, the service logic module circularly receives the data from the data processing module, and the data of each channel is processed independently;
step 2: each channel firstly determines a first effective signal, judges that logic is three continuous received signals, and considers that the first PPS signal is effective PPS if the difference between rising edge time and high level duration time of the three continuous received signals are within a set range;
step 3: the validity judgment is needed to be carried out every time the PPS signal is received, the judgment logic is that the difference between the rising edge time of the current PPS signal and the rising edge time of the valid PPS signal is within the set range, and if the current signal is invalid, the exception processing is carried out;
step 4: if the test channel is a main channel, buffering effective signal data, otherwise, performing related judgment of a secondary channel signal, wherein the main channel is a reference channel for calculating the synchronous precision, namely the difference between the rising edges of the secondary channel and the main channel is the synchronous precision of the secondary channel, and only one channel is allowed to be selected as the main channel;
step 5: performing time synchronization precision calculation from channel signal correlation judgment success, buffering calculation results and original data, and performing exception processing if signal correlation judgment fails;
step 6: and before the measurement is not finished, the data processing flow is circularly executed.
10. A method for testing a time synchronization accuracy testing system based on a pulse per second method according to any one of claims 1-9, comprising the steps of:
step S1: the hardware module acquisition interface is connected with all the measured node second pulse signals;
step S2: the hardware module is connected with the computer through the Ethernet;
step S3: the hardware module is connected with a power supply through a power interface to start power supply;
step S4: the method comprises the steps of running a software module on a computer, and firstly configuring a hardware module;
step S5: starting a test, wherein a hardware module starts to acquire a pulse signal output by a tested node, and transmits acquired time stamp data to a software module;
step S6: the software module analyzes and processes the data in real time, and automatically generates a test report after the test is finished.
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