CN116863980B - Dynamic adjusting circuit and method for gating signals - Google Patents
Dynamic adjusting circuit and method for gating signals Download PDFInfo
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Abstract
The application provides a dynamic regulation circuit and method of gating signal, belongs to memory technical field, the circuit includes: a gating signal generation sub-circuit for generating an initial reference gating signal and an initial reference sampling clock signal based on a current read instruction; the sampling sub-circuit is used for shifting the current reference sampling clock signal based on a preset offset to obtain current left shifting and right shifting sampling clock signals, and the returned DQS signals are respectively sampled through the current left shifting, reference and right shifting sampling clock signals to obtain a current sampling value sequence; and the delay adjusting sub-circuit is used for synchronously adjusting the delay amount of the first gating frame and the delay amount of the second gating frame under the condition that the current sampling value sequence is not a preset value until the updated reference gating signal is used as the gating signal corresponding to the current reading operation when the sampling value sequence obtained based on the updated left offset, reference and right offset sampling clock signals is the preset value, and can accurately read the data in the storage equipment.
Description
Technical Field
The present disclosure relates to the field of memory technologies, and in particular, to a dynamic adjustment circuit and method for a gate signal.
Background
With the continuous development of memory technology, the running speed of current products such as DRAM (Dynamic Random Access Memory ) and FLASH is also increasing. In the working process of high-speed devices such as DRAM and FLASH, due to the influence of temperature, electromagnetic interference and the like, clock signals (such as RDQS signals of the DRAM) returned from the high-speed devices are offset, so that a memory controller cannot accurately read data in a memory device, and further the product performance is affected.
Disclosure of Invention
The application provides a dynamic adjusting circuit and a method for a gate control signal, which are used for ensuring that a storage controller can accurately read data in storage equipment and avoiding the influence of environmental factors on the performance of products.
The application provides a dynamic adjustment circuit of gating signal, the circuit includes:
the gating signal generation sub-circuit is used for generating an initial reference gating signal and an initial reference sampling clock signal based on a read instruction corresponding to the current read data operation; the delay amount of a first gating frame corresponding to the initial reference gating signal is the same as that of a second gating frame corresponding to the initial reference sampling clock signal, the length of the first gating frame is matched with the length of an effective DQS signal corresponding to the current read data operation, and the length of the second gating frame is smaller than that of the first gating frame;
The sampling sub-circuit is used for respectively carrying out left offset and right offset operation on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, and respectively sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence;
and the delay adjustment sub-circuit is used for synchronously adjusting the delay amount of the first gating frame and the delay amount of the second gating frame under the condition that the current sampling value sequence is not a preset value, and taking the updated reference gating signal as a target gating signal corresponding to the current read data operation until the sampling value sequence obtained based on the updated left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal is the preset value.
According to the dynamic adjusting circuit of the gating signal, the gating signal generation sub-circuit comprises a reading instruction sending unit, a data generating unit and a parallel-serial conversion unit;
the read instruction sending unit is used for responding to the current read data operation to generate a corresponding read instruction and respectively sending the read instruction to the data generating unit and the storage device;
The data generation unit is used for determining the length of data to be read based on the read instruction and generating parallel data corresponding to an initial reference gating signal and an initial reference sampling clock signal based on the length of the data to be read;
the parallel-serial conversion unit is used for carrying out parallel-serial conversion on parallel data corresponding to the initial reference gating signal and the initial reference sampling clock signal so as to obtain the initial reference gating signal and the initial reference sampling clock signal.
According to the dynamic adjusting circuit of the gating signal, the sampling sub-circuit comprises an offset sampling clock generating unit and a sampling unit;
the offset sampling clock generation unit is used for respectively carrying out left offset and right offset operations on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal;
the sampling is used for sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal respectively to obtain a current sampling value sequence.
According to the dynamic regulating circuit of the gating signal, the delay regulating sub-circuit comprises a sampling value judging unit, a delay amount regulating unit and a target gating signal output unit;
The sampling value judging unit is used for judging whether the current sampling value sequence is a preset value or not;
the delay amount adjusting unit is used for synchronously adjusting the delay amounts of the first gate control frame and the second gate control frame under the condition that the current sampling value sequence is not a preset value;
the target gating signal output unit is used for taking the updated reference gating signal as a target gating signal corresponding to the current read data operation under the condition that the current sampling value sequence is a preset value.
The application also provides a dynamic adjustment method of the gating signal, the method is applied to the dynamic adjustment circuit of the gating signal, and the method comprises the following steps:
step S1, generating an initial reference gating signal and an initial reference sampling clock signal based on a read instruction corresponding to current read data operation; the delay amount of a first gating frame corresponding to the initial reference gating signal is the same as that of a second gating frame corresponding to the initial reference sampling clock signal, the length of the first gating frame is matched with the length of an effective DQS signal corresponding to the current read data operation, and the length of the second gating frame is smaller than that of the first gating frame;
step S2, performing left offset and right offset operations on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, and sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence;
And step S3, synchronously adjusting the delay amounts of the first gating frame and the second gating frame under the condition that the current sampling value sequence is not a preset value, and taking the updated reference gating signal as a target gating signal corresponding to the current read data operation until the sampling value sequence obtained based on the updated left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal is the preset value.
According to the method for dynamically adjusting the gate control signal provided by the application, the step S3 specifically includes:
step S31, judging whether the current sampling value sequence is a preset value, if so, jumping to execute step S33, and if not, executing step S32;
step S32, synchronously adjusting the delay amounts of the first gate frame and the second gate frame, and jumping to execute the step S2;
step S33, the current reference gating signal is used as a target gating signal corresponding to the current read data operation.
According to the method for dynamically adjusting the gate control signal provided by the application, the delay amounts of the first gate control frame and the second gate control frame are synchronously adjusted, and the method specifically comprises the following steps:
determining the adjusting direction and the adjusting step number of the delay amount based on the value of the current sampling value sequence and a preset adjusting step length;
And synchronously adjusting the delay amounts of the first gate control frame and the second gate control frame based on the adjusting direction and the adjusting step number.
According to the dynamic adjustment method of the gating signal, the current reference gating signal is an initial reference gating signal or an updated reference gating signal.
According to the method for dynamically adjusting the gating signal provided by the application, the initial reference gating signal and the initial reference sampling clock signal are generated based on the reading instruction corresponding to the current reading data operation, and the method specifically comprises the following steps:
corresponding read instructions are generated in response to the current read data operation and are respectively sent to the data generation unit and the storage device;
determining the length of data to be read based on the read instruction, and generating parallel data corresponding to an initial reference gating signal and an initial reference sampling clock signal based on the length of the data to be read;
and performing parallel-to-serial conversion on parallel data corresponding to the initial reference gating signal and the initial reference sampling clock signal to obtain the initial reference gating signal and the initial reference sampling clock signal.
According to the dynamic adjustment method for the gating signals, the initial reference gating signal corresponding to the current data reading operation is the same as the delay amount of the target gating signal corresponding to the last data reading operation.
The application provides a dynamic adjusting circuit and a method of a gating signal, wherein the circuit comprises: the gating signal generation sub-circuit is used for generating an initial reference gating signal and an initial reference sampling clock signal based on a read instruction corresponding to the current read data operation; the delay amount of a first gating frame corresponding to the initial reference gating signal is the same as that of a second gating frame corresponding to the initial reference sampling clock signal, the length of the first gating frame is matched with the length of an effective DQS signal corresponding to the current read data operation, and the length of the second gating frame is smaller than that of the first gating frame; the sampling sub-circuit is used for respectively carrying out left offset and right offset operation on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, and respectively sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence; and the delay adjustment sub-circuit is used for synchronously adjusting the delay amount of the first gating frame and the delay amount of the second gating frame under the condition that the current sampling value sequence is not a preset value, and taking the updated reference gating signal as a target gating signal corresponding to the current read data operation when the sampling value sequence obtained based on the updated left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal is the preset value, so that the reference gating signal can be dynamically adjusted based on the sampling value of the DQS signal, the gating frame can be ensured to frame the correct DQS signal, the memory controller can be further ensured to accurately read the data in the memory device, and the influence of environmental factors on the product performance is avoided.
Drawings
For a clearer description of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a dynamic adjustment circuit for a gating signal according to the present disclosure;
FIG. 2 is a graph illustrating the effect of environmental factors on the DQS signal after gating provided by the present application;
FIG. 3 is a flow chart of a method for dynamically adjusting a gating signal according to the present disclosure;
FIG. 4 is a schematic diagram showing the dynamic adjustment effect of the gating signal provided by the present application;
fig. 5 is a schematic structural diagram of an electronic device provided in the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Fig. 1 is a schematic structural diagram of a dynamic adjustment circuit of a gating signal provided in the present application, as shown in fig. 1, the circuit includes:
the gating signal generation sub-circuit is used for generating an initial reference gating signal and an initial reference sampling clock signal based on a read instruction corresponding to the current read data operation; the delay amount of a first gating frame corresponding to the initial reference gating signal is the same as that of a second gating frame corresponding to the initial reference sampling clock signal, the length of the first gating frame is matched with the length of an effective DQS signal corresponding to the current read data operation, and the length of the second gating frame is smaller than that of the first gating frame;
the sampling sub-circuit is used for respectively carrying out left offset and right offset operation on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, and respectively sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence;
and the delay adjustment sub-circuit is used for synchronously adjusting the delay amount of the first gating frame and the delay amount of the second gating frame under the condition that the current sampling value sequence is not a preset value, and taking the updated reference gating signal as a target gating signal corresponding to the current read data operation until the sampling value sequence obtained based on the updated left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal is the preset value.
Specifically, fig. 2 is a schematic diagram of an effect result of environmental factors provided in the present application on a DQS signal after gating, as shown in fig. 2, in a normal case, a memory controller may send a read command to a memory device when performing a data reading operation, the memory device may send a DQS signal and a corresponding data signal to be read to the memory controller after receiving the read command, and the memory controller performs gating processing on the DQS signal through the gating signal to obtain a gated DQS signal (i.e. an effective DQS signal), and performs accurate data signal reading based on the gated DQS signal. However, during the operation of high-speed devices such as DRAM and FLASH, due to the influence of factors such as temperature and electromagnetic interference, the DQS signal returned from the memory device will shift left or right, however, once the phase of the gating signal in the memory controller is determined to remain unchanged, so that the memory controller cannot obtain the complete valid DQS signal through the gating signal under the condition that the DQS signal shifts, and the memory controller cannot accurately read the data signal. To this problem, the application provides a dynamic adjustment circuit of gating signal to dynamic adjustment gating signal's phase place under the circumstances that DQS signal takes place the skew, guarantee effective DQS signal's accurate acquisition, and then guarantee that memory controller can accurately read the data in the storage device, avoid environmental factor to the influence of product performance.
More specifically, the gating signal generation sub-circuit comprises a read instruction sending unit, a data generating unit and a parallel-serial conversion unit;
the read instruction sending unit is used for responding to the current read data operation to generate a corresponding read instruction and respectively sending the read instruction to the data generating unit and the storage device;
the data generation unit is used for determining the length of data to be read based on the read instruction and generating parallel data corresponding to an initial reference gating signal and an initial reference sampling clock signal based on the length of the data to be read;
the parallel-serial conversion unit is used for carrying out parallel-serial conversion on parallel data corresponding to the initial reference gating signal and the initial reference sampling clock signal so as to obtain the initial reference gating signal and the initial reference sampling clock signal.
It can be appreciated that when the user triggers a data reading operation, the read instruction sending unit can generate a corresponding read instruction in response to the current data reading operation and send the corresponding read instruction to the data generating unit and the storage device respectively. The read command includes a data address and a data length to be read, and based on the data address and the data length, the memory device feeds back a corresponding DQS signal and the data signal to be read to the memory controller. Meanwhile, the data generating unit may determine the length of the data to be read based on the read instruction, and generate parallel data corresponding to the initial reference gating signal and the initial reference sampling clock signal based on the length of the data to be read, and the parallel-to-serial converting unit may perform parallel-to-serial conversion on the parallel data corresponding to the initial reference gating signal and the initial reference sampling clock signal to obtain the initial reference gating signal and the initial reference sampling clock signal. It is worth noting that, because there may be multiple data reading operations in the working process of high-speed devices such as DRAM and FLASH, for any data reading operation, the initial reference gating signal corresponding to the current data reading operation and the delay amount of the target gating signal corresponding to the last data reading operation in the embodiment of the present application are the same, based on this, since each data reading operation can timely adjust the delay amount of the gating signal (i.e. the position of the gating frame), the situation that the deviation between the first gating frame and the DQS signal is too large is not caused, and the real-time performance of adjustment can be ensured. It will also be appreciated that for the first read data operation of a high speed device (i.e., the first time the device is put into use), the corresponding delay of the initial reference gating signal is obtained by pre-training. The specific pre-training method may be any currently available gating signal training method (for example, a method of continuously adjusting the delay amount of the gating signal until the read data is determined to be the preset data), which is not specifically limited in this embodiment of the present application. Based on this, through the mode of gradually adjusting the delay amount of the gating signal in this embodiment of the application, the problem that the first gating frame and the DQS signal have too large deviation and need be retrained, waste time and bandwidth, and then influence the overall performance of the high-speed device can be avoided.
Further, the sampling sub-circuit comprises an offset sampling clock generating unit and a sampling unit;
the offset sampling clock generation unit is used for respectively carrying out left offset and right offset operations on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal;
the sampling is used for sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal respectively to obtain a current sampling value sequence.
Based on the foregoing, it can be seen that the length of the first gating frame is matched with the length of the valid DQS signal corresponding to the current read data operation (i.e., the complete valid DQS signal can be ensured to be obtained), and the length of the second gating frame is smaller than that of the first gating frame. In the practical application process, the length of the second gating frame is preferably between 1/4 of the length of the data to be read and 1/2 of the length of the data to be read, and meanwhile, the preset offset is preferably smaller than UI/4, so that accurate sampling of DQS signals and accurate adjustment of the delay amount of the subsequent first gating frame can be ensured.
Notably, embodiments of the present application sample the DQS signal with falling edges of the left offset sample clock signal, the reference sample clock signal, and the right offset sample clock signal. Based on this, it can be understood that, in the case that the data length to be read, the length of the second gating frame, and the delay amount are known, a certain correspondence exists between a sampling value sequence obtained by sampling the DQS signal by the left offset sampling clock signal, the reference sampling clock signal, and the right offset sampling clock signal, and the offset amount of the DQS signal. Based on the correspondence, the embodiment of the application can determine the adjustment strategy of the delay amount of the first gating frame according to the current sampling value sequence. Specifically, the delay adjusting sub-circuit comprises a sampling value judging unit, a delay amount adjusting unit and a target gating signal output unit;
The sampling value judging unit is used for judging whether the current sampling value sequence is a preset value or not;
the delay amount adjusting unit is used for synchronously adjusting the delay amounts of the first gate control frame and the second gate control frame under the condition that the current sampling value sequence is not a preset value;
the target gating signal output unit is used for taking the updated reference gating signal as a target gating signal corresponding to the current read data operation under the condition that the current sampling value sequence is a preset value.
Based on the foregoing, a certain correspondence exists between a sampling value sequence obtained by sampling the DQS signal by the left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal, and the offset of the DQS signal, so that the corresponding sampling value sequence is known (i.e., is a preset value) when the DQS signal is not offset. Therefore, the embodiment of the application judges whether the current sampling value sequence is a preset value through the sampling value judging unit, and synchronously adjusts the delay amounts of the first gating frame and the second gating frame through the delay amount adjusting unit under the condition that the current sampling value sequence is not the preset value until the updated reference gating signal is used as the target gating signal corresponding to the current read data operation through the target gating signal output unit under the condition that the current sampling value sequence is the preset value. Based on the method, the phase of the gating signal can be timely adjusted under the condition that the DQS signal is offset, so that the memory controller can accurately acquire an effective DQS signal, and further accurate reading of data is guaranteed.
The circuit provided by the embodiment of the application comprises: the gating signal generation sub-circuit is used for generating an initial reference gating signal and an initial reference sampling clock signal based on a read instruction corresponding to the current read data operation; the delay amount of a first gating frame corresponding to the initial reference gating signal is the same as that of a second gating frame corresponding to the initial reference sampling clock signal, the length of the first gating frame is matched with the length of an effective DQS signal corresponding to the current read data operation, and the length of the second gating frame is smaller than that of the first gating frame; the sampling sub-circuit is used for respectively carrying out left offset and right offset operation on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, and respectively sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence; and the delay adjustment sub-circuit is used for synchronously adjusting the delay amount of the first gating frame and the delay amount of the second gating frame under the condition that the current sampling value sequence is not a preset value, and taking the updated reference gating signal as a target gating signal corresponding to the current read data operation when the sampling value sequence obtained based on the updated left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal is the preset value, so that the reference gating signal can be dynamically adjusted based on the sampling value of the DQS signal, the gating frame can be ensured to frame the correct DQS signal, the memory controller can be further ensured to accurately read the data in the memory device, and the influence of environmental factors on the product performance is avoided.
Based on any of the foregoing embodiments, fig. 3 is a flow chart of a method for dynamically adjusting a gating signal provided in the present application, where the method is applied to the dynamic adjusting circuit of a gating signal described in the foregoing embodiments, as shown in fig. 3, and the method includes:
step S1, generating an initial reference gating signal and an initial reference sampling clock signal based on a read instruction corresponding to current read data operation; the delay amount of a first gating frame corresponding to the initial reference gating signal is the same as that of a second gating frame corresponding to the initial reference sampling clock signal, the length of the first gating frame is matched with the length of an effective DQS signal corresponding to the current read data operation, and the length of the second gating frame is smaller than that of the first gating frame;
step S2, performing left offset and right offset operations on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, and sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence;
and step S3, synchronously adjusting the delay amounts of the first gating frame and the second gating frame under the condition that the current sampling value sequence is not a preset value, and taking the updated reference gating signal as a target gating signal corresponding to the current read data operation until the sampling value sequence obtained based on the updated left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal is the preset value.
Specifically, the step S3 specifically includes:
step S31, judging whether the current sampling value sequence is a preset value, if so, jumping to execute step S33, and if not, executing step S32;
step S32, synchronously adjusting the delay amounts of the first gate frame and the second gate frame, and jumping to execute the step S2;
step S33, the current reference gating signal is used as a target gating signal corresponding to the current read data operation.
It can be appreciated that if the current sampling value sequence is determined to be the preset value during the first sampling, it is indicated that the DQS signal is not shifted, and the initial reference gating signal is directly used as the target gating signal. Thus, the current reference gating signal may be an initial reference gating signal or an updated reference gating signal.
The step of synchronously adjusting the delay amounts of the first gate control frame and the second gate control frame specifically comprises the following steps:
determining the adjusting direction and the adjusting step number of the delay amount based on the value of the current sampling value sequence and a preset adjusting step length;
and synchronously adjusting the delay amounts of the first gate control frame and the second gate control frame based on the adjusting direction and the adjusting step number.
Based on the foregoing, a certain correspondence exists between a sampling value sequence obtained by sampling the DQS signal by the left offset sampling clock signal, the reference sampling clock signal, and the right offset sampling clock signal, and the offset of the DQS signal, and therefore, the corresponding sampling value sequence is known when the DQS signal has no offset and has an offset. Based on this, the embodiment of the application may determine the offset direction and the offset degree of the DQS signal through the value of the current sampling value sequence, and further determine the adjustment step number of the delay amount based on the preset adjustment step length. It can be understood that the preset adjustment step length may be freely set according to an actual application scenario, for example, 1UI is divided into N equal parts, the length of 1 part is taken as the adjustment step length, and the size of N is not specifically limited in this embodiment.
The generating an initial reference gating signal and an initial reference sampling clock signal based on the read instruction corresponding to the current read data operation specifically comprises the following steps:
corresponding read instructions are generated in response to the current read data operation and are respectively sent to the data generation unit and the storage device;
determining the length of data to be read based on the read instruction, and generating parallel data corresponding to an initial reference gating signal and an initial reference sampling clock signal based on the length of the data to be read;
and performing parallel-to-serial conversion on parallel data corresponding to the initial reference gating signal and the initial reference sampling clock signal to obtain the initial reference gating signal and the initial reference sampling clock signal.
The specific implementation principle and effect of the present invention are described in detail in the foregoing embodiments, and are not described in detail herein.
The steps and effects of the method for dynamically adjusting a gating signal according to the embodiments of the present application are described below with reference to a specific example.
Fig. 4 is a schematic diagram of the dynamic adjustment effect of the gating signal provided in the present application, as shown in fig. 4, when the DQS signal is not shifted, the first gating frame may obtain a complete valid DQS signal, and a sampling value sequence obtained by sampling the DQS signal returned by the storage device by the left shifting sampling clock signal, the reference sampling clock signal, and the right shifting sampling clock signal respectively should be "110" (i.e., a preset value). As shown in FIG. 4, the DQS signal is shifted to the left, where the first case is a smaller shift, where the sample sequence is "100" and the second case is a larger shift, where the sample sequence is "000", where the shift direction and thus the adjustment direction of the delay amount may be determined based on the value of the current sample sequence, and the shift degree may be determined based on the value of the current sample sequence, and thus the adjustment step number of the delay amount may be determined based on a preset adjustment step size. Obviously, the number of adjustment steps in the first case is smaller than that in the second case, and the specific adjustment steps can be determined according to actual needs, which is not specifically limited in the embodiments of the present application. After one round of adjustment, the updated reference sampling clock signals are respectively subjected to left offset and right offset operations based on preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, DQS signals returned by the storage device are respectively sampled through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence, and whether the current sampling value sequence is a preset value is judged. And repeatedly executing the adjusting process to obtain a final target gating signal. Table 1 is an example of a gating frame delay amount adjustment policy provided in an embodiment of the present application:
Table 1 gating frame delay amount adjustment strategy example
As shown in table 1, which corresponds to the DQS signal offset case shown in fig. 4. Wherein, sample 0 refers to the sampling value corresponding to the left offset sampling clock signal, sample 1 refers to the sampling value corresponding to the reference sampling clock signal, sample 2 refers to the sampling value corresponding to the right offset sampling clock signal, 2 steps are reduced to the left offset by 2 adjustment steps, 2 steps are increased to the right offset by 2 adjustment steps, and so on. Based on the foregoing, it can be understood that, since the delay amount of the gating signal is timely adjusted in each read data operation, the situation that the deviation between the first gating frame and the DQS signal is too large is not caused, and meanwhile, since the preset offset is smaller than UI/4, when the sample value sequences are "010", "011", "001" and "101", the sample value sequences are all determined to be abnormal, and an abnormal processing needs to be performed, and the specific mode of the abnormal processing is not specifically limited. It should be noted that the adjustment strategies shown in table 1 are only for the DQS signal offset case shown in fig. 4, and for other offset cases, the corresponding adjustment strategies may be adjusted according to practical situations, which are not exhaustive in the embodiments of the present application.
The method provided by the embodiment of the application comprises the following steps: step S1, generating an initial reference gating signal and an initial reference sampling clock signal based on a read instruction corresponding to current read data operation; the delay amount of a first gating frame corresponding to the initial reference gating signal is the same as that of a second gating frame corresponding to the initial reference sampling clock signal, the length of the first gating frame is matched with the length of an effective DQS signal corresponding to the current read data operation, and the length of the second gating frame is smaller than that of the first gating frame; step S2, performing left offset and right offset operations on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, and sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence; and step S3, under the condition that the current sampling value sequence is not a preset value, synchronously adjusting the delay amounts of the first gating frame and the second gating frame until the sampling value sequence obtained based on the updated left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal is the preset value, taking the updated reference gating signal as a target gating signal corresponding to the current read data operation, dynamically adjusting the reference gating signal based on the sampling value of the DQS signal, ensuring that the gating frame can frame the correct DQS signal, further ensuring that the memory controller can accurately read data in the memory device, and avoiding the influence of environmental factors on the product performance.
Fig. 5 illustrates a physical schematic diagram of an electronic device, as shown in fig. 5, which may include: the device comprises a processor 101, a communication interface 102, a memory 103 and a communication bus 104, wherein the processor 101, the communication interface 102 and the memory 103 are in communication with each other through the communication bus 104. The processor 101 may invoke logic instructions in the memory 103 to perform a method for dynamically adjusting the gating signal provided by the methods described above, the method comprising: step S1, generating an initial reference gating signal and an initial reference sampling clock signal based on a read instruction corresponding to current read data operation; the delay amount of a first gating frame corresponding to the initial reference gating signal is the same as that of a second gating frame corresponding to the initial reference sampling clock signal, the length of the first gating frame is matched with the length of an effective DQS signal corresponding to the current read data operation, and the length of the second gating frame is smaller than that of the first gating frame; step S2, performing left offset and right offset operations on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, and sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence; and step S3, synchronously adjusting the delay amounts of the first gating frame and the second gating frame under the condition that the current sampling value sequence is not a preset value, and taking the updated reference gating signal as a target gating signal corresponding to the current read data operation until the sampling value sequence obtained based on the updated left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal is the preset value.
Further, the logic instructions in the memory 103 may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
In another aspect, the present application also provides a computer program product, the computer program product including a computer program, the computer program being storable on a non-transitory computer readable storage medium, the computer program, when executed by a processor, being capable of executing a method for dynamically adjusting a gating signal provided by the above methods, the method comprising: step S1, generating an initial reference gating signal and an initial reference sampling clock signal based on a read instruction corresponding to current read data operation; the delay amount of a first gating frame corresponding to the initial reference gating signal is the same as that of a second gating frame corresponding to the initial reference sampling clock signal, the length of the first gating frame is matched with the length of an effective DQS signal corresponding to the current read data operation, and the length of the second gating frame is smaller than that of the first gating frame; step S2, performing left offset and right offset operations on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, and sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence; and step S3, synchronously adjusting the delay amounts of the first gating frame and the second gating frame under the condition that the current sampling value sequence is not a preset value, and taking the updated reference gating signal as a target gating signal corresponding to the current read data operation until the sampling value sequence obtained based on the updated left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal is the preset value.
In yet another aspect, the present application further provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform a method for dynamically adjusting a gating signal provided by the above methods, the method comprising: step S1, generating an initial reference gating signal and an initial reference sampling clock signal based on a read instruction corresponding to current read data operation; the delay amount of a first gating frame corresponding to the initial reference gating signal is the same as that of a second gating frame corresponding to the initial reference sampling clock signal, the length of the first gating frame is matched with the length of an effective DQS signal corresponding to the current read data operation, and the length of the second gating frame is smaller than that of the first gating frame; step S2, performing left offset and right offset operations on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, and sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence; and step S3, synchronously adjusting the delay amounts of the first gating frame and the second gating frame under the condition that the current sampling value sequence is not a preset value, and taking the updated reference gating signal as a target gating signal corresponding to the current read data operation until the sampling value sequence obtained based on the updated left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal is the preset value.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as a ROM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (9)
1. A dynamic adjustment circuit for a gating signal, the circuit comprising:
the gating signal generation sub-circuit is used for generating an initial reference gating signal and an initial reference sampling clock signal based on a read instruction corresponding to the current read data operation; the delay amount of a first gating frame corresponding to the initial reference gating signal is the same as that of a second gating frame corresponding to the initial reference sampling clock signal, the length of the first gating frame is matched with the length of an effective DQS signal corresponding to the current read data operation, and the length of the second gating frame is smaller than that of the first gating frame;
the sampling sub-circuit is used for respectively carrying out left offset and right offset operation on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, and respectively sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence;
The delay adjustment sub-circuit is used for synchronously adjusting the delay amount of the first gating frame and the delay amount of the second gating frame under the condition that the current sampling value sequence is not a preset value, and taking the updated reference gating signal as a target gating signal corresponding to the current read data operation until the sampling value sequence obtained based on the updated left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal is the preset value; the preset value is a sampling value sequence corresponding to the DQS signal when no offset exists;
the gate control signal generation sub-circuit comprises a read instruction sending unit, a data generating unit and a parallel-serial conversion unit;
the read instruction sending unit is used for responding to the current read data operation to generate a corresponding read instruction and respectively sending the read instruction to the data generating unit and the storage device;
the data generation unit is used for determining the length of data to be read based on the read instruction and generating parallel data corresponding to an initial reference gating signal and an initial reference sampling clock signal based on the length of the data to be read;
the parallel-serial conversion unit is used for carrying out parallel-serial conversion on parallel data corresponding to the initial reference gating signal and the initial reference sampling clock signal so as to obtain the initial reference gating signal and the initial reference sampling clock signal.
2. The dynamic adjustment circuit of a gating signal of claim 1, wherein the sampling sub-circuit includes an offset sampling clock generation unit and a sampling unit;
the offset sampling clock generation unit is used for respectively carrying out left offset and right offset operations on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal;
the sampling is used for sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal respectively to obtain a current sampling value sequence.
3. The dynamic adjustment circuit of a gate control signal according to claim 2, wherein the delay adjustment sub-circuit includes a sampling value judgment unit, a delay amount adjustment unit, and a target gate control signal output unit;
the sampling value judging unit is used for judging whether the current sampling value sequence is a preset value or not;
the delay amount adjusting unit is used for synchronously adjusting the delay amounts of the first gate control frame and the second gate control frame under the condition that the current sampling value sequence is not a preset value;
the target gating signal output unit is used for taking the updated reference gating signal as a target gating signal corresponding to the current read data operation under the condition that the current sampling value sequence is a preset value.
4. A method of dynamic adjustment of a gating signal, the method being applied to the dynamic adjustment circuit of a gating signal according to claim 3, the method comprising:
step S1, generating an initial reference gating signal and an initial reference sampling clock signal based on a read instruction corresponding to current read data operation; the delay amount of a first gating frame corresponding to the initial reference gating signal is the same as that of a second gating frame corresponding to the initial reference sampling clock signal, the length of the first gating frame is matched with the length of an effective DQS signal corresponding to the current read data operation, and the length of the second gating frame is smaller than that of the first gating frame;
step S2, performing left offset and right offset operations on the current reference sampling clock signal based on a preset offset to obtain a current left offset sampling clock signal and a current right offset sampling clock signal, and sampling DQS signals returned by the storage device through the current left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal to obtain a current sampling value sequence;
and step S3, synchronously adjusting the delay amounts of the first gating frame and the second gating frame under the condition that the current sampling value sequence is not a preset value, and taking the updated reference gating signal as a target gating signal corresponding to the current read data operation until the sampling value sequence obtained based on the updated left offset sampling clock signal, the reference sampling clock signal and the right offset sampling clock signal is the preset value.
5. The method for dynamically adjusting a gate signal according to claim 4, wherein the step S3 specifically comprises:
step S31, judging whether the current sampling value sequence is a preset value, if so, jumping to execute step S33, and if not, executing step S32;
step S32, synchronously adjusting the delay amounts of the first gate frame and the second gate frame, and jumping to execute the step S2;
step S33, the current reference gating signal is used as a target gating signal corresponding to the current read data operation.
6. The method for dynamically adjusting a gate signal according to claim 5, wherein the step of synchronously adjusting the delay amounts of the first gate frame and the second gate frame comprises:
determining the adjusting direction and the adjusting step number of the delay amount based on the value of the current sampling value sequence and a preset adjusting step length;
and synchronously adjusting the delay amounts of the first gate control frame and the second gate control frame based on the adjusting direction and the adjusting step number.
7. The method of claim 6, wherein the current reference gating signal is an initial reference gating signal or an updated reference gating signal.
8. The method for dynamically adjusting a gate signal according to claim 7, wherein the generating an initial reference gate signal and an initial reference sampling clock signal based on a read command corresponding to a current read data operation specifically comprises:
corresponding read instructions are generated in response to the current read data operation and are respectively sent to the data generation unit and the storage device;
determining the length of data to be read based on the read instruction, and generating parallel data corresponding to an initial reference gating signal and an initial reference sampling clock signal based on the length of the data to be read;
and performing parallel-to-serial conversion on parallel data corresponding to the initial reference gating signal and the initial reference sampling clock signal to obtain the initial reference gating signal and the initial reference sampling clock signal.
9. The method of claim 8, wherein the initial reference gating signal corresponding to the current read data operation is the same as the delay of the target gating signal corresponding to the last read data operation.
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