CN116564380B - Correction method and device for gate pulse signals in DRAM (dynamic random Access memory) - Google Patents
Correction method and device for gate pulse signals in DRAM (dynamic random Access memory) Download PDFInfo
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Abstract
The application provides a correction method and a correction device for a gate pulse signal in a DRAM (dynamic random access memory), belonging to the technical field of memories, wherein the method comprises the following steps: determining a maximum phase offset based on the clock period of the DRAM and determining a phase adjustment step based on the maximum phase offset; performing phase adjustment on the initial gating pulse signal based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set; sampling the data strobe signal corresponding to the current correction node based on the gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively to obtain a first sampling value sequence and a second sampling value sequence; and determining a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correcting the initial gating pulse signal to obtain a target gating pulse signal, and taking the target gating pulse signal as the gating pulse signal corresponding to the current correction node, so that the correction can be performed under the condition of not influencing the working of the DRAM, and the working efficiency of the DRAM is improved.
Description
Technical Field
The present application relates to the field of memory technologies, and in particular, to a method and an apparatus for correcting a gate pulse signal in a DRAM.
Background
In a read operation of a memory of a dynamic random access memory (Dynamic Random Access Memory, DRAM) granule, a memory controller needs to read data in the memory based on a data strobe signal (Bidirectional data strobe, DQS) generated by a memory cell. To ensure the accuracy of reading the data, an accurate DQS valid signal is acquired.
To address this problem, in the prior art, a gating pulse signal (i.e. DQS gating signal) equal to the DQS valid signal is output by the memory controller, so as to perform a gating operation on the DQS signal output by the memory unit to obtain a gated DQS signal (i.e. a gated DQS signal), and data is read based on the gated DQS signal. To ensure that the gatedDQS signal is an accurate DQS valid signal, the DQSgating signal needs to be trained in advance. The training process of the DQSrising signal is as follows: and performing multiple read operations on the memory of the DRAM particles, wherein the phase of DQS (data strobe) signals corresponding to each read operation is different, comparing the finally read data with the expected data to determine whether the read operation is correct, and taking the phase of DQSgaring signals corresponding to the correct read operation as the gating pulse signal phase of the subsequent read operation.
By adopting the mode, the accurate reading of the data in the DRAM particles can be ensured to the greatest extent. However, in the actual operation process of the DRAM, the tdqsck parameter may dynamically change along with the temperature and voltage changes within the range specified by the design specification, i.e., the phase of the DQS signal may dynamically change, so that the phase of the DQS gating signal needs to be retrained to ensure that an accurate DQS valid signal is obtained. However, since the training process of the DQS gating signal takes a long time and the normal access to the DRAM needs to be suspended, frequent training of the DQS gating signal will result in a serious decrease in the working efficiency of the DRAM.
Disclosure of Invention
The application provides a method and a device for correcting a gate pulse signal in a DRAM (dynamic random Access memory), which are used for solving the problem that the working efficiency of the DRAM is reduced by the conventional correction mode of the gate pulse signal.
The application provides a correction method of a gate pulse signal in a DRAM, which comprises the following steps:
determining a maximum phase offset based on a clock period of the DRAM and determining a phase adjustment step based on the maximum phase offset;
performing phase adjustment on the initial gating pulse signal based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal is a gating pulse signal corresponding to the last correction node;
Sampling a data strobe signal corresponding to a current correction node based on gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively to obtain a first sampling value sequence and a second sampling value sequence;
and determining a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correcting the initial gating pulse signal based on the phase correction value to obtain a target gating pulse signal, and taking the target gating pulse signal as a gating pulse signal corresponding to a current correction node.
According to the correction method of the gate pulse signal in the DRAM, the maximum phase offset is the phase offset corresponding to half of the clock period of the DRAM, and correspondingly, the phase adjustment step length is the quotient of the maximum phase offset and the preset phase adjustment gear.
According to the method for correcting the gating pulse signal in the DRAM, the initial gating pulse signal is subjected to phase adjustment based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set, and the method specifically comprises the following steps:
Shifting the initial gating pulse signal leftwards for N times based on the phase adjustment step length to obtain a first gating pulse signal set, and shifting the initial gating pulse signal rightwards for N times based on the phase adjustment step length to obtain a second gating pulse signal set; wherein N is the preset phase adjustment gear number.
According to the correction method for the gate pulse signals in the DRAM, the first gate pulse signal set comprises N gate pulse signals corresponding to N left offsets, and the second gate pulse signal set comprises N gate pulse signals corresponding to N right offsets.
According to the method for correcting the gate pulse signal in the DRAM, the data gate signal corresponding to the current correction node is sampled based on the gate pulse signals in the first gate pulse signal set and the second gate pulse signal set respectively to obtain a first sampling value sequence and a second sampling value sequence, and the method specifically comprises the following steps:
sampling data strobe signals corresponding to a current correction node based on rising edges of N gating pulse signals in the first gating pulse signal set respectively to obtain a corresponding first sampling value set, and sequencing all sampling values in the first sampling value set based on phase offset of the gating pulse signals corresponding to all sampling values in the first sampling value set relative to an initial gating pulse signal to obtain a first sampling value sequence;
And respectively sampling the data strobe signals corresponding to the current correction node based on rising edges of N gating pulse signals in the second gating pulse signal set to obtain a corresponding second sampling value set, and sequencing all sampling values in the second sampling value set based on phase offset of the gating pulse signals corresponding to all sampling values in the second sampling value set relative to the initial gating pulse signals to obtain a second sampling value sequence.
According to the method for correcting the gate pulse signal in the DRAM, the phase correction value of the gate pulse signal is determined based on the first sampling value sequence and the second sampling value sequence, and the method specifically comprises the following steps:
determining a current phase shift direction and a phase shift amount of the initial gating pulse signal based on the first sampling value sequence and the second sampling value sequence;
a phase correction value of the gating pulse signal is determined based on a current phase offset direction and a phase offset amount of the initial gating pulse signal.
According to the method for correcting the gating pulse signal in the DRAM, the current phase offset direction and the phase offset of the initial gating pulse signal are determined based on the first sampling value sequence and the second sampling value sequence, and the method specifically comprises the following steps:
Under the condition that sampling values in the first sampling value sequence are 0 and sampling values in the second sampling value sequence are 1, judging that the initial gating pulse signal is free of offset;
and under the condition that sampling values in the first sampling value sequence and the second sampling value sequence comprise 0 and 1, determining the current phase shift direction and the phase shift amount of the initial gating pulse signal based on the positions and the quantity of 0 and 1 in the first sampling value sequence and the second sampling value sequence.
The application also provides a correction device of the gate pulse signal in the DRAM, which comprises:
a first determining module, configured to determine a maximum phase offset based on a clock period of the DRAM, and determine a phase adjustment step based on the maximum phase offset;
the gating pulse signal set generation module is used for carrying out phase adjustment on the initial gating pulse signal based on the phase adjustment step length so as to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal is a gating pulse signal corresponding to the last correction node;
the sampling value sequence generation module is used for sampling the data strobe signal corresponding to the current correction node based on the gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively so as to obtain a first sampling value sequence and a second sampling value sequence;
And the signal correction module is used for determining a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correcting the initial gating pulse signal based on the phase correction value to obtain a target gating pulse signal, and taking the target gating pulse signal as a gating pulse signal corresponding to a current correction node.
The present application also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of correcting a gating pulse signal in a DRAM as described in any of the above.
The application also provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of a method of correcting a gating pulse signal in a DRAM as described in any of the above.
The method and the device for correcting the gate pulse signal in the DRAM determine the maximum phase offset based on the clock period of the DRAM and determine the phase adjustment step length based on the maximum phase offset; performing phase adjustment on the initial gating pulse signal based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal is a gating pulse signal corresponding to the last correction node; sampling a data strobe signal corresponding to a current correction node based on gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively to obtain a first sampling value sequence and a second sampling value sequence; and determining a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correcting the initial gating pulse signal based on the phase correction value to obtain a target gating pulse signal, and taking the target gating pulse signal as a gating pulse signal corresponding to a current correction node.
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In order to more clearly illustrate the application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for correcting a gate pulse signal in a DRAM according to the present application;
FIG. 2 is a schematic waveform diagram corresponding to a method for correcting a gate pulse signal in a DRAM according to the present application;
FIG. 3 is a schematic diagram of a determining flow of phase correction values provided by the present application;
FIG. 4 is a schematic diagram of a calibration device for gate pulse signals in DRAM according to the present application;
fig. 5 is a schematic structural diagram of an electronic device provided by the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Fig. 1 is a flow chart of a method for correcting a gate pulse signal in a DRAM according to the present application, as shown in fig. 1, the method includes:
step 101, determining a maximum phase offset based on a clock cycle of the DRAM, and determining a phase adjustment step based on the maximum phase offset.
Specifically, the maximum phase offset is a phase offset corresponding to half of a clock cycle of the DRAM, and correspondingly, the phase adjustment step length is a quotient of the maximum phase offset and a preset phase adjustment gear. Based on the foregoing, it can be seen that, in the actual working process of the DRAM, the tdqsck parameter dynamically changes along with the change of the temperature and the voltage within the range specified by the design specification, that is, the phase of the DQS signal dynamically changes, and fig. 2 is a waveform schematic diagram corresponding to the correction method of the gating pulse signal in the DRAM according to the present application, as shown in fig. 2, in order to ensure the accuracy of the read operation, it is necessary to ensure that the gating pulse signal (i.e., the DQS gating signal) is aligned with the rising edge of the DQS valid signal, so that when the phase of the DQS signal dynamically changes, the phase of the DQS gating signal must also follow the change. Based on this, the embodiment of the present application first determines the phase fluctuation range of the DQS signal based on the fluctuation range of the tdqsck parameter, and preferably, the embodiment of the present application sets the phase fluctuation range of the DQS signal to half of the clock period of the DRAM, and based on this, to ensure the accuracy of the read operation, it is required to ensure that the phase adjustment range of the DQS gating signal matches the phase fluctuation range of the DQS signal, and therefore, the embodiment of the present application uses the phase offset corresponding to half of the clock period of the DRAM as the maximum phase offset (corresponding to the maximum phase adjustment range) of the gating pulse signal. On the basis, in order to ensure the adjustment precision of the gating pulse signal in the practical application process, the embodiment of the application can preset the phase adjustment gear (namely the adjustment times corresponding to the phase offset of the gating pulse signal from 0 to the maximum phase offset), and the phase adjustment step length can be determined based on the maximum phase offset and the preset phase adjustment gear. It will be appreciated that the phase fluctuation range of the DQS signal is not limited to half the clock period of DRAM, and may be flexibly adjusted based on the fluctuation range of the tdqsck parameter during practical applications. It is also appreciated that during actual use, the phase of the DQS signal may be shifted to the left or right, and thus the aforementioned maximum phase shift actually refers to a maximum phase shift in a single direction (i.e., left or right).
102, performing phase adjustment on the initial gating pulse signal based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal is the gating pulse signal corresponding to the last correction node.
Specifically, the step of performing phase adjustment on the initial gating pulse signal based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set specifically includes:
shifting the initial gating pulse signal leftwards for N times based on the phase adjustment step length to obtain a first gating pulse signal set, and shifting the initial gating pulse signal rightwards for N times based on the phase adjustment step length to obtain a second gating pulse signal set; wherein N is the preset phase adjustment gear number.
It can be understood that the correction node in the embodiment of the present application may be set according to actual needs, for example, correction may be performed based on a preset time interval, or correction may be performed in a unit of one read operation, which is not particularly limited in the embodiment of the present application. However, it is worth noting that, before the DRAM is formally put into use, the first accurate gating pulse signal is still obtained by training the dqs rising signal in advance, based on this, after the DRAM is formally put into use, the gating pulse signal obtained by training can be corrected by using the correction method of the gating pulse signal according to the embodiment of the present application, without retraining, and further, the fast and accurate correction of the gating pulse signal can be performed without affecting the normal access of the DRAM.
As can be further appreciated in conjunction with fig. 2, the rising edge of the gating pulse signal corresponding to the last correction node is aligned with the rising edge of the DQS valid signal corresponding to the last correction node, so that the last correction node can perform accurate data reading. However, due to the variation of the tdqsck parameter, the phase of the DQS signal also varies, so that the rising edge of the DQS valid signal corresponding to the current correction node is shifted, and the data reading error will be caused if the gating pulse signal corresponding to the previous correction node is still adopted. Based on this, the embodiment of the application shifts the initial gating pulse signal to the left N times based on the phase adjustment step length to obtain the first gating pulse signal set, shifts the initial gating pulse signal to the right N times based on the phase adjustment step length to obtain the second gating pulse signal set, and samples the DQS signal corresponding to the current correction node through the gating pulse signals in the first and second gating pulse signal sets, so that the shift condition of the DQS signal corresponding to the current correction node can be judged, and the gating pulse signal is corrected. It can be understood that N is the preset phase adjustment gear number, the first gating pulse signal set includes N gating pulse signals corresponding to N shifts to the left, and the second gating pulse signal set includes N gating pulse signals corresponding to N shifts to the right. Based on this, N gating pulse signals from 1 phase adjustment step to N phase adjustment steps (corresponding to the maximum phase offset) are covered in the first gating pulse signal set, i.e., the left phase offset with respect to the initial gating pulse signal, and N gating pulse signals from 1 phase adjustment step to N phase adjustment steps (corresponding to the maximum phase offset) are covered in the second gating pulse signal set, i.e., the right phase offset with respect to the initial gating pulse signal, on the basis of which the data strobe signals corresponding to the current correction node are sampled by the gating pulse signals in the first gating pulse signal set and the second gating pulse signal set, and the offset condition of the DQS signal corresponding to the current correction node can be determined.
Step 103, sampling the data strobe signal corresponding to the current correction node based on the gate pulse signals in the first gate pulse signal set and the second gate pulse signal set respectively to obtain a first sampling value sequence and a second sampling value sequence.
Specifically, the sampling the data strobe signal corresponding to the current correction node based on the gating pulse signals in the first gating pulse signal set and the second gating pulse signal set to obtain a first sampling value sequence and a second sampling value sequence, specifically includes:
sampling data strobe signals corresponding to a current correction node based on rising edges of N gating pulse signals in the first gating pulse signal set respectively to obtain a corresponding first sampling value set, and sequencing all sampling values in the first sampling value set based on phase offset of the gating pulse signals corresponding to all sampling values in the first sampling value set relative to an initial gating pulse signal to obtain a first sampling value sequence;
and respectively sampling the data strobe signals corresponding to the current correction node based on rising edges of N gating pulse signals in the second gating pulse signal set to obtain a corresponding second sampling value set, and sequencing all sampling values in the second sampling value set based on phase offset of the gating pulse signals corresponding to all sampling values in the second sampling value set relative to the initial gating pulse signals to obtain a second sampling value sequence.
It can be appreciated that based on the above manner, sampling values of different positions of the data strobe signal corresponding to the current correction node can be obtained. For the first sampling value set, the embodiments of the present application preferably sequence the sampling values according to the order from large to small of the phase offset of the corresponding gating pulse signal relative to the initial gating pulse signal, and for the second sampling value set, the embodiments of the present application preferably sequence the sampling values according to the order from small to large of the phase offset of the corresponding gating pulse signal relative to the initial gating pulse signal, as can be seen in conjunction with fig. 2, based on this, it can be ensured that the first sampling value sequence and the second sampling value sequence can intuitively feed back the sampling values from left to right of the data gating signal corresponding to the current correction node, based on this, the phase correction value of the gating pulse signal can be rapidly determined based on the first sampling value sequence and the second sampling value sequence.
Step 104, determining a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correcting the initial gating pulse signal based on the phase correction value to obtain a target gating pulse signal, and taking the target gating pulse signal as a gating pulse signal corresponding to a current correction node.
Specifically, fig. 3 is a schematic diagram of a determining flow of the phase correction value provided by the present application, as shown in fig. 3, where the determining of the phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence specifically includes:
step 201, determining a current phase shift direction and a phase shift amount of the initial gating pulse signal based on the first sampling value sequence and the second sampling value sequence;
step 202, determining a phase correction value of the gating pulse signal based on a current phase offset direction and a phase offset amount of the initial gating pulse signal.
The determining the current phase shift direction and the phase shift amount of the initial gating pulse signal based on the first sampling value sequence and the second sampling value sequence specifically comprises the following steps:
under the condition that sampling values in the first sampling value sequence are 0 and sampling values in the second sampling value sequence are 1, judging that the initial gating pulse signal is free of offset;
and under the condition that sampling values in the first sampling value sequence and the second sampling value sequence comprise 0 and 1, determining the current phase shift direction and the phase shift amount of the initial gating pulse signal based on the positions and the quantity of 0 and 1 in the first sampling value sequence and the second sampling value sequence.
As can be understood from fig. 2, in the case that the sampling values in the first sampling value sequence are all 0 and the sampling values in the second sampling value sequence are all 1, no offset of the DQS signal is illustrated, so that no offset of the initial gating pulse signal is determined;
in case the samples in the first and second sample sequences each comprise 0 and 1, there are two situations, the first one: the sampling values in the first sampling value sequence are N-M0 s and M1 s in sequence, the sampling values in the second sampling value sequence are N-M1 s and M0 s in sequence, which means that the DQS signal is offset leftwards relative to the last correction node by M phase adjustment step sizes, namely the initial gating pulse signal is offset rightwards relative to the DQS signal by M phase adjustment step sizes (namely the current phase offset direction of the initial gating pulse signal is rightwards and the phase offset amount is M phase adjustment step sizes), and based on the initial gating pulse signal, the phase correction value of the gating pulse signal can be determined, and the initial gating pulse signal is corrected based on the phase correction value to obtain the target gating pulse signal. It will be appreciated that the phase correction value of the embodiments of the present application may be positive or negative, where positive represents a rightward shift and negative represents a leftward shift.
Second case: the sampling values in the first sampling value sequence are sequentially M1 s and N-M0 s, the sampling values in the second sampling value sequence are sequentially M0 s and N-M1 s, which means that the DQS signal is shifted rightwards relative to the last correction node by M phase adjustment step sizes, namely the initial gating pulse signal is shifted leftwards relative to the DQS signal by M phase adjustment step sizes (namely the current phase shift direction of the initial gating pulse signal is leftwards and the phase shift amount is M phase adjustment step sizes), and based on the phase adjustment step sizes, the phase correction value of the gating pulse signal can be determined and the initial gating pulse signal is corrected based on the phase correction value. It is understood that M is a positive integer less than N. It can be further understood that the phase adjustment of the initial gate pulse signal and the sampling of the data strobe signal corresponding to the current correction node can be respectively implemented by the existing arbitrary phase adjustment circuit and sampling circuit, and the embodiment of the application is not particularly limited herein as to which type of circuit is specifically adopted.
The method provided by the embodiment of the application comprises the steps of determining the maximum phase offset based on the clock period of the DRAM and determining the phase adjustment step length based on the maximum phase offset; performing phase adjustment on the initial gating pulse signal based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal is a gating pulse signal corresponding to the last correction node; sampling a data strobe signal corresponding to a current correction node based on gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively to obtain a first sampling value sequence and a second sampling value sequence; and determining a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correcting the initial gating pulse signal based on the phase correction value to obtain a target gating pulse signal, and taking the target gating pulse signal as a gating pulse signal corresponding to a current correction node.
Based on any of the above embodiments, fig. 4 is a schematic structural diagram of a correction device for gate pulse signals in a DRAM according to the present application, as shown in fig. 4, the device includes:
a first determining module 301, configured to determine a maximum phase offset based on a clock cycle of the DRAM, and determine a phase adjustment step size based on the maximum phase offset;
a gating pulse signal set generating module 302, configured to perform phase adjustment on the initial gating pulse signal based on the phase adjustment step size to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal is a gating pulse signal corresponding to the last correction node;
a sampling value sequence generating module 303, configured to sample a data strobe signal corresponding to a current correction node based on gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively, so as to obtain a first sampling value sequence and a second sampling value sequence;
the signal correction module 304 is configured to determine a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correct the initial gating pulse signal based on the phase correction value to obtain a target gating pulse signal, and use the target gating pulse signal as a gating pulse signal corresponding to a current correction node.
In the device provided by the embodiment of the application, the first determining module 301 determines the maximum phase offset based on the clock period of the DRAM, and determines the phase adjustment step length based on the maximum phase offset; the gating pulse signal set generation module 302 performs phase adjustment on the initial gating pulse signal based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal is a gating pulse signal corresponding to the last correction node; the sampling value sequence generating module 303 samples a data strobe signal corresponding to the current correction node based on the gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively to obtain a first sampling value sequence and a second sampling value sequence; the signal correction module 304 determines a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, corrects the initial gating pulse signal based on the phase correction value to obtain a target gating pulse signal, and uses the target gating pulse signal as a gating pulse signal corresponding to a current correction node.
Based on the above embodiment, the maximum phase offset is a phase offset corresponding to half of a clock cycle of the DRAM, and correspondingly, the phase adjustment step size is a quotient of the maximum phase offset and a preset phase adjustment gear number.
Based on any one of the foregoing embodiments, the phase adjusting the initial gating pulse signal based on the phase adjusting step length to obtain a first gating pulse signal set and a second gating pulse signal set specifically includes:
shifting the initial gating pulse signal leftwards for N times based on the phase adjustment step length to obtain a first gating pulse signal set, and shifting the initial gating pulse signal rightwards for N times based on the phase adjustment step length to obtain a second gating pulse signal set; wherein N is the preset phase adjustment gear number.
Based on any one of the above embodiments, the first gating pulse signal set includes N gating pulse signals corresponding to N shifts to the left, and the second gating pulse signal set includes N gating pulse signals corresponding to N shifts to the right.
Based on any one of the foregoing embodiments, the sampling the data strobe signal corresponding to the current correction node based on the gating pulse signals in the first gating pulse signal set and the second gating pulse signal set to obtain a first sampling value sequence and a second sampling value sequence, specifically includes:
Sampling data strobe signals corresponding to a current correction node based on rising edges of N gating pulse signals in the first gating pulse signal set respectively to obtain a corresponding first sampling value set, and sequencing all sampling values in the first sampling value set based on phase offset of the gating pulse signals corresponding to all sampling values in the first sampling value set relative to an initial gating pulse signal to obtain a first sampling value sequence;
and respectively sampling the data strobe signals corresponding to the current correction node based on rising edges of N gating pulse signals in the second gating pulse signal set to obtain a corresponding second sampling value set, and sequencing all sampling values in the second sampling value set based on phase offset of the gating pulse signals corresponding to all sampling values in the second sampling value set relative to the initial gating pulse signals to obtain a second sampling value sequence.
Based on any of the foregoing embodiments, the determining the phase correction value of the gating pulse signal based on the first sample value sequence and the second sample value sequence specifically includes:
determining a current phase shift direction and a phase shift amount of the initial gating pulse signal based on the first sampling value sequence and the second sampling value sequence;
A phase correction value of the gating pulse signal is determined based on a current phase offset direction and a phase offset amount of the initial gating pulse signal.
Based on any of the foregoing embodiments, the determining the current phase offset direction and the phase offset of the initial gating pulse signal based on the first sample value sequence and the second sample value sequence specifically includes:
under the condition that sampling values in the first sampling value sequence are 0 and sampling values in the second sampling value sequence are 1, judging that the initial gating pulse signal is free of offset;
and under the condition that sampling values in the first sampling value sequence and the second sampling value sequence comprise 0 and 1, determining the current phase shift direction and the phase shift amount of the initial gating pulse signal based on the positions and the quantity of 0 and 1 in the first sampling value sequence and the second sampling value sequence.
Fig. 5 illustrates a physical schematic diagram of an electronic device, as shown in fig. 5, which may include: the device comprises a processor 401, a communication interface 402, a memory 403 and a communication bus 404, wherein the processor 401, the communication interface 402 and the memory 403 are in communication with each other through the communication bus 404. The processor 401 may call logic instructions in the memory 403 to execute the correction method of the gate pulse signal in the DRAM provided by the above methods, the method includes: determining a maximum phase offset based on a clock period of the DRAM and determining a phase adjustment step based on the maximum phase offset; performing phase adjustment on the initial gating pulse signal based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal is a gating pulse signal corresponding to the last correction node; sampling a data strobe signal corresponding to a current correction node based on gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively to obtain a first sampling value sequence and a second sampling value sequence; and determining a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correcting the initial gating pulse signal based on the phase correction value to obtain a target gating pulse signal, and taking the target gating pulse signal as a gating pulse signal corresponding to a current correction node.
Further, the logic instructions in the memory 403 may be implemented in the form of software functional units and stored in a computer readable storage medium when sold or used as a stand alone product. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
In another aspect, the present application also provides a computer program product, where the computer program product includes a computer program, where the computer program can be stored on a non-transitory computer readable storage medium, where the computer program when executed by a processor can perform a method for correcting a gate pulse signal in a DRAM provided by the above methods, where the method includes: determining a maximum phase offset based on a clock period of the DRAM and determining a phase adjustment step based on the maximum phase offset; performing phase adjustment on the initial gating pulse signal based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal is a gating pulse signal corresponding to the last correction node; sampling a data strobe signal corresponding to a current correction node based on gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively to obtain a first sampling value sequence and a second sampling value sequence; and determining a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correcting the initial gating pulse signal based on the phase correction value to obtain a target gating pulse signal, and taking the target gating pulse signal as a gating pulse signal corresponding to a current correction node.
In yet another aspect, the present application also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform a method of correcting a gate pulse signal in a DRAM provided by the above methods, the method comprising: determining a maximum phase offset based on a clock period of the DRAM and determining a phase adjustment step based on the maximum phase offset; performing phase adjustment on the initial gating pulse signal based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal is a gating pulse signal corresponding to the last correction node; sampling a data strobe signal corresponding to a current correction node based on gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively to obtain a first sampling value sequence and a second sampling value sequence; and determining a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correcting the initial gating pulse signal based on the phase correction value to obtain a target gating pulse signal, and taking the target gating pulse signal as a gating pulse signal corresponding to a current correction node.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as a ROM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (6)
1. A method for correcting a gate pulse signal in a DRAM, the method comprising:
determining a maximum phase offset based on a clock period of the DRAM and determining a phase adjustment step based on the maximum phase offset;
performing phase adjustment on the initial gating pulse signal based on the phase adjustment step length to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal is a gating pulse signal corresponding to the last correction node;
sampling a data strobe signal corresponding to a current correction node based on gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively to obtain a first sampling value sequence and a second sampling value sequence;
Determining a phase correction value of a gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correcting the initial gating pulse signal based on the phase correction value to obtain a target gating pulse signal, and taking the target gating pulse signal as a gating pulse signal corresponding to a current correction node;
the maximum phase offset is a phase offset corresponding to half of a clock cycle of the DRAM, and correspondingly, the phase adjustment step length is a quotient of the maximum phase offset and a preset phase adjustment gear;
the step of phase adjustment is performed on the initial gating pulse signal based on the step of phase adjustment to obtain a first gating pulse signal set and a second gating pulse signal set, and the method specifically comprises the following steps:
shifting the initial gating pulse signal leftwards for N times based on the phase adjustment step length to obtain a first gating pulse signal set, and shifting the initial gating pulse signal rightwards for N times based on the phase adjustment step length to obtain a second gating pulse signal set; wherein N is the preset phase adjustment gear number;
the step of sampling the data strobe signal corresponding to the current correction node based on the gate pulse signals in the first gate pulse signal set and the second gate pulse signal set to obtain a first sampling value sequence and a second sampling value sequence, specifically includes:
Sampling data strobe signals corresponding to a current correction node based on rising edges of N gating pulse signals in the first gating pulse signal set respectively to obtain a corresponding first sampling value set, and sequencing all sampling values in the first sampling value set based on phase offset of the gating pulse signals corresponding to all sampling values in the first sampling value set relative to an initial gating pulse signal to obtain a first sampling value sequence;
sampling data strobe signals corresponding to the current correction node based on rising edges of N gating pulse signals in the second gating pulse signal set respectively to obtain a corresponding second sampling value set, and sequencing all sampling values in the second sampling value set based on phase offset of the gating pulse signals corresponding to all sampling values in the second sampling value set relative to an initial gating pulse signal to obtain a second sampling value sequence;
the determining the phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence specifically comprises the following steps:
determining a current phase shift direction and a phase shift amount of the initial gating pulse signal based on the first sampling value sequence and the second sampling value sequence;
A phase correction value of the gating pulse signal is determined based on a current phase offset direction and a phase offset amount of the initial gating pulse signal.
2. The method for correcting a gate pulse signal in a DRAM according to claim 1, wherein the first set of gate pulse signals includes N gate pulse signals corresponding to N shifts to the left, and the second set of gate pulse signals includes N gate pulse signals corresponding to N shifts to the right.
3. The method for correcting a gate pulse signal in a DRAM according to claim 1, wherein determining a current phase shift direction and a phase shift amount of the initial gate pulse signal based on the first sample value sequence and the second sample value sequence specifically comprises:
under the condition that sampling values in the first sampling value sequence are 0 and sampling values in the second sampling value sequence are 1, judging that the initial gating pulse signal is free of offset;
and under the condition that sampling values in the first sampling value sequence and the second sampling value sequence comprise 0 and 1, determining the current phase shift direction and the phase shift amount of the initial gating pulse signal based on the positions and the quantity of 0 and 1 in the first sampling value sequence and the second sampling value sequence.
4. A correction device for a gate pulse signal in a DRAM, the device comprising:
a first determining module, configured to determine a maximum phase offset based on a clock period of the DRAM, and determine a phase adjustment step based on the maximum phase offset;
the gating pulse signal set generation module is used for carrying out phase adjustment on the initial gating pulse signal based on the phase adjustment step length so as to obtain a first gating pulse signal set and a second gating pulse signal set; the initial gating pulse signal is a gating pulse signal corresponding to the last correction node;
the sampling value sequence generation module is used for sampling the data strobe signal corresponding to the current correction node based on the gating pulse signals in the first gating pulse signal set and the second gating pulse signal set respectively so as to obtain a first sampling value sequence and a second sampling value sequence;
the signal correction module is used for determining a phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence, correcting the initial gating pulse signal based on the phase correction value to obtain a target gating pulse signal, and taking the target gating pulse signal as a gating pulse signal corresponding to a current correction node;
The maximum phase offset is a phase offset corresponding to half of a clock cycle of the DRAM, and correspondingly, the phase adjustment step length is a quotient of the maximum phase offset and a preset phase adjustment gear;
the step of phase adjustment is performed on the initial gating pulse signal based on the step of phase adjustment to obtain a first gating pulse signal set and a second gating pulse signal set, and the method specifically comprises the following steps:
shifting the initial gating pulse signal leftwards for N times based on the phase adjustment step length to obtain a first gating pulse signal set, and shifting the initial gating pulse signal rightwards for N times based on the phase adjustment step length to obtain a second gating pulse signal set; wherein N is the preset phase adjustment gear number;
the step of sampling the data strobe signal corresponding to the current correction node based on the gate pulse signals in the first gate pulse signal set and the second gate pulse signal set to obtain a first sampling value sequence and a second sampling value sequence, specifically includes:
sampling data strobe signals corresponding to a current correction node based on rising edges of N gating pulse signals in the first gating pulse signal set respectively to obtain a corresponding first sampling value set, and sequencing all sampling values in the first sampling value set based on phase offset of the gating pulse signals corresponding to all sampling values in the first sampling value set relative to an initial gating pulse signal to obtain a first sampling value sequence;
Sampling data strobe signals corresponding to the current correction node based on rising edges of N gating pulse signals in the second gating pulse signal set respectively to obtain a corresponding second sampling value set, and sequencing all sampling values in the second sampling value set based on phase offset of the gating pulse signals corresponding to all sampling values in the second sampling value set relative to an initial gating pulse signal to obtain a second sampling value sequence;
the determining the phase correction value of the gating pulse signal based on the first sampling value sequence and the second sampling value sequence specifically comprises the following steps:
determining a current phase shift direction and a phase shift amount of the initial gating pulse signal based on the first sampling value sequence and the second sampling value sequence;
a phase correction value of the gating pulse signal is determined based on a current phase offset direction and a phase offset amount of the initial gating pulse signal.
5. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method for correcting a gating pulse signal in a DRAM as claimed in any of claims 1 to 3 when the program is executed.
6. A non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor, implements the steps of the method of correcting a gate pulse signal in a DRAM as claimed in any of claims 1 to 3.
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| CN115547381A (en) * | 2022-11-30 | 2022-12-30 | 合肥奎芯集成电路设计有限公司 | Gate signal generating circuit of data gate signal and signal generating method thereof |
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| CN115547381A (en) * | 2022-11-30 | 2022-12-30 | 合肥奎芯集成电路设计有限公司 | Gate signal generating circuit of data gate signal and signal generating method thereof |
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