CN113342722A - Eye diagram quality optimization method and device, electronic equipment and storage medium - Google Patents
Eye diagram quality optimization method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The application relates to an eye diagram quality optimization method, an eye diagram quality optimization device, electronic equipment and a storage medium, wherein a processor sends a detection instruction to a memory; acquiring a duty ratio detection result sent by a memory; adjusting the synchronous signal according to the duty ratio detection result until the duty ratio detection result returned by the memory is within the preset duty ratio range; the detection instruction is used for instructing the memory to carry out duty ratio detection on the synchronous signal sent by the processor; the duty ratio of the synchronous signal is related to the eye distortion degree of the data signal sent to the memory by the processor; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold. By adopting the method, the eye diagram quality of the data signal can be improved, and the normal data communication between the processor and the memory can be ensured.
Description
Technical Field
The present application relates to the field of signal processing technologies, and in particular, to an eye diagram quality optimization method and apparatus, an electronic device, and a storage medium.
Background
In electronic devices such as mobile phones, a Dynamic Random Access Memory (DRAM) may interact with a Central Processing Unit (CPU) to complete reading and writing of high-speed digital signals. The CPU can generate an eye pattern of the digital signal and evaluate the quality of the digital signal transmitted between the CPU and the DRAM according to the quality of the eye pattern so as to adjust the signal parameters according to the quality of the eye pattern in time. The eye pattern is formed by overlapping each symbol waveform obtained by scanning the signal, and is shaped like an image of an eye.
In the conventional method, the CPU can obtain better eye pattern quality by increasing the driving current of the digital signal.
However, the improvement effect on the quality of the eye diagram by adopting the method is limited.
Disclosure of Invention
The embodiment of the application provides an eye pattern quality optimization method and device, electronic equipment and a storage medium, which can effectively improve the eye pattern quality of signals.
In a first aspect, the present application provides a method for optimizing quality of an eye diagram, comprising:
sending a detection instruction to a memory; the detection instruction is used for instructing the memory to carry out duty ratio detection on the synchronous signal sent by the processor; the duty ratio of the synchronous signal is related to the eye distortion degree of the data signal sent to the memory by the processor;
acquiring a duty ratio detection result sent by a memory;
adjusting the synchronous signal according to the duty ratio detection result until the duty ratio detection result returned by the memory is within the preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
In a second aspect, the present application provides a method for optimizing quality of an eye diagram, comprising:
receiving a detection instruction sent by a processor;
performing duty ratio detection on a synchronous signal sent by a processor based on a detection instruction; the duty ratio of the synchronous signal is related to the eye distortion degree of the data signal sent to the memory by the processor;
sending a duty ratio detection result to a processor; the duty ratio detection result is used for instructing the processor to adjust the synchronous signal according to the duty ratio detection result until the duty ratio detection result is within a preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
In a third aspect, the present application provides an apparatus for optimizing quality of an eye diagram, comprising:
the sending module is used for sending a detection instruction to the memory; the detection instruction is used for instructing the memory to carry out duty ratio detection on the synchronous signal sent by the processor; the duty ratio of the synchronous signal is related to the eye distortion degree of the data signal sent to the memory by the processor;
the acquisition module is used for acquiring a duty ratio detection result sent by the memory;
the adjusting module is used for adjusting the synchronous signal according to the duty ratio detection result until the duty ratio detection result returned by the memory is within the preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
In a fourth aspect, the present application provides an apparatus for optimizing quality of an eye diagram, comprising:
the receiving module is used for receiving a detection instruction sent by the processor;
the detection module is used for carrying out duty ratio detection on the synchronous signal sent by the processor based on the detection instruction; the duty ratio of the synchronous signal is related to the eye distortion degree of the data signal sent to the memory by the processor;
the indicating module is used for sending a duty ratio detection result to the processor; the duty ratio detection result is used for instructing the processor to adjust the synchronous signal according to the duty ratio detection result until the duty ratio detection result is within a preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
In a fifth aspect, the present application provides an electronic device comprising a processor and a memory, wherein:
the processor is used for sending a detection instruction to the memory;
the memory is used for receiving a detection instruction sent by the processor; based on the detection instruction, carrying out duty ratio detection on the synchronous signal sent by the processor, and sending a duty ratio detection result to the processor; wherein, the duty ratio of the synchronous signal is related to the eye pattern distortion degree of the data signal sent to the memory by the processor;
the processor is used for adjusting the synchronous signal according to the duty ratio detection result until the duty ratio detection result returned by the memory is within the preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
In a sixth aspect, the present application provides an electronic device, including a memory and a processor, where the memory stores a computer program, and the computer program, when executed by the processor, causes the processor to perform the steps of the method for optimizing eye diagram quality.
In a seventh aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, performs the steps of the above-mentioned method for optimizing eye diagram quality.
According to the optimization method and device for the eye diagram quality, the electronic equipment and the storage medium, the processor sends a detection instruction to the memory and instructs the memory to carry out duty ratio detection on the synchronous signal sent by the processor; because the duty ratio of the synchronous signal is related to the eye pattern distortion degree of the data signal sent to the memory by the processor, after the processor acquires the duty ratio detection result sent by the memory, the synchronous signal can be adjusted according to the duty ratio detection result until the duty ratio detection result returned by the memory is within the preset duty ratio range; when the duty ratio detection result of the synchronous signal is within the preset duty ratio range, the eye pattern distortion degree of the data signal is small, and the eye pattern deformity of the data signal caused by the larger or smaller duty ratio can be reduced by adopting the adjusted synchronous signal, so that the eye pattern quality of the data signal is improved, and the normal data communication between the processor and the memory is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram of an exemplary embodiment of a method for optimizing eye diagram quality;
FIG. 2 is a flow diagram of a method for optimizing eye diagram quality in one embodiment;
FIG. 3 is a schematic diagram of a method for optimizing eye diagram quality in one embodiment;
FIG. 4 is a schematic diagram of a method for optimizing eye diagram quality in one embodiment;
FIG. 5 is a schematic diagram of a method for optimizing eye diagram quality in one embodiment;
FIG. 6 is a schematic diagram of a duty cycle detection circuit in one embodiment;
FIG. 7 is a flowchart of a method for optimizing eye diagram quality in another embodiment;
FIG. 8 is a schematic diagram of a method for optimizing eye diagram quality in one embodiment;
FIG. 9 is a flowchart of a method for optimizing eye diagram quality in another embodiment;
FIG. 10 is a block diagram showing an arrangement for optimizing the quality of an eye diagram in one embodiment;
FIG. 11 is a block diagram showing an arrangement for optimizing the quality of an eye diagram in one embodiment;
FIG. 12 is a block diagram showing the structure of an eye diagram quality optimizing apparatus according to an embodiment;
FIG. 13 is a block diagram showing the structure of an eye diagram quality optimizing apparatus according to an embodiment;
fig. 14 is a block diagram showing the configuration of an electronic apparatus in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Fig. 1 is a schematic application environment diagram of an optimization method of eye diagram quality in one embodiment. As shown in fig. 1, the application environment includes an electronic device 100, where the electronic device 100 may include a processor 101 and a memory 102, where the processor 101 and the memory 102 may transmit high-speed Digital signals such as data signals, synchronization signals, and clock signals, and the electronic device may be, but is not limited to, any terminal device such as a mobile phone, a notebook computer, a tablet computer, a smart watch, a PDA (Personal Digital Assistant), a POS (Point of Sales), a vehicle-mounted computer, and a wearable device.
Fig. 2 is a flow chart of a method for optimizing eye diagram quality in one embodiment. The method for optimizing the eye diagram quality in this embodiment is described by taking the processor operating in fig. 1 as an example. As shown in fig. 2, the method includes:
s101, sending a detection instruction to a memory; the detection instruction is used for instructing the memory to carry out duty ratio detection on the synchronous signal sent by the processor; the duty cycle of the synchronization signal is related to the degree of eye distortion of the data signal sent to the memory by the processor.
The memory may be a control arithmetic processor in the electronic device, or may be a microprocessor, an image processor, or the like in the electronic device, and the type of the processor is not limited herein. For example, the Processor may be a Central Processing Unit (CPU), a Micro Processor Unit (MPU), a Micro Controller Unit (MCU), or a Graphics Processing Unit (GPU). The memory may be a Dynamic random access memory (Dynamic RAM, abbreviated as DRAM), a Video memory (Video RAM, abbreviated as VRAM), or a Fast Page Mode Dynamic random access memory (Fast Page Mode DRAM, abbreviated as FPM DRAM), and the type of the memory is not limited herein. The processor and the memory can transmit high-speed digital signals such as synchronous signals, data signals and the like.
The processor may generate an eye pattern of a digital signal such as a synchronization signal, a data signal, etc. to determine the transmission quality of the digital signal according to the eye pattern, that is, the eye pattern is a tool for evaluating the transmission quality of the digital signal, and the quality of the eye pattern may reflect the quality of the transmission quality of the digital signal. The eye pattern is formed by overlapping each symbol waveform obtained by scanning the signal, and is shaped like an image of an eye, as shown in fig. 3. The influence of intersymbol interference and noise of the digital signal can be observed from the eye pattern, the integral characteristic of the digital signal is reflected, and therefore the quality degree of the system can be estimated, and the eye pattern analysis is the core of high-speed digital signal analysis. In addition, the processor can adjust the signal parameters according to the quality of the eye pattern, and the transmission quality of the digital signal is improved. The parameters of the eye pattern may include the opening size of the eye region in the eye pattern, the definition of the eye pattern, etc., and may also include parameters of eye width, eye breadth, eye cross ratio, etc. The opening size of the eye region of the eye pattern reflects the strength of intersymbol crosstalk, the larger the opening size of the eye region is, and the more positive the eye pattern is, the smaller the intersymbol crosstalk is; and conversely, the larger the intersymbol interference. When noise exists in the digital signal, the noise is superposed on the digital signal, so that the traces of the eye pattern observed by the CPU become blurred, and compared with the eye pattern when the noise interferes, the eye pattern curve becomes blurred and the traces become wide.
The synchronization signal may be a source clock signal transmitted between the processor and the memory, or may be other types of signals, which is not limited herein. Optionally, the synchronization signal is a digital probe signal sent by the processor to the memory, and the digital probe signal is used to identify a transmission cycle of the data signal within one clock cycle, so that the memory can accurately receive the data signal.
The duty cycle of the synchronization signal is related to the degree of eye distortion of the data signal. The eye distortion may be incomplete or irregular, and the distortion type is not limited herein. When the duty ratio of the synchronous signal is larger or smaller, the eye pattern of the data signal obtained by the processor is distorted, so that the processor adjusts the data signal based on the distorted eye pattern, and the parameters of the data signal are not the optimal parameters, thereby affecting the system performance. For example, the processor determines a level decision threshold based on the distorted eye pattern, resulting in a threshold being low or high, so that when the memory recognizes a high level or a low level from the data signal and the level decision threshold, a phenomenon of recognizing the high level as a low level or recognizing the low level as a high level occurs, resulting in a higher error rate of the data signal obtained by the memory.
Taking the processor as the CPU and the memory as the DRAM as an example, as shown in fig. 4, the high-speed digital signals transmitted between the CPU and the DRAM include a data signal DQ, a digital probe signal DQs, a clock signal CLK, a control signal CA, and the like. The data signals between the CPU and the DRAM may include a plurality of signals including, for example, DQ _ x, DQ _ y, DQ _ z, and the like; the identification of the transmission cycles of the plurality of data signals all uses the same digital probe signal DQS, and the transmission cycles obtained by using the same DQS cannot be adapted to all the data signals due to the deviation of the initial phases of the plurality of data signals, as shown in fig. 5, the initial phase of the data signal DQ _ y lags, and if the duty ratio of the DQS at this time causes the high level time period of the DQS signal to be reduced and is located at the position of the dotted line in fig. 5, the eye diagram of the data signal DQ _ y is incomplete.
Generally, the processor can increase the driving current of the digital signal to obtain better eye pattern quality. In addition, high frequency components are reduced in the process of digital signal transmission, so that the quality of an eye pattern is deteriorated; the processor can pre-emphasis the digital signal before sending the digital signal to the memory, and enhance high-frequency components in the digital signal to improve the eye diagram quality of the digital signal. However, the above-mentioned method for improving the eye pattern quality can only improve the quality of a single eye region of a single digital signal, and cannot improve the eye pattern abnormality caused by the duty ratio of the synchronization signal.
To improve eye diagram quality, the processor may send a detection instruction to the memory. The detection instruction is used for instructing the memory to carry out duty ratio detection on the synchronous signal sent by the processor, and a duty ratio detection result of the synchronous signal is obtained. The duty ratio detection result may include a duty ratio of the synchronization signal, where the duty ratio may be a ratio of a duration of a high level to a signal period in one signal period of the synchronization signal.
The detection instruction may be transmitted after the processor transmits the synchronization signal to the memory, or may be transmitted before the synchronization signal is transmitted, and the transmission timing of the detection instruction is not limited herein. The detection instruction can carry an identifier of the synchronous signal and can also carry a duty ratio detection identifier, so that after the memory receives the detection instruction, the memory can know that the duty ratio detection needs to be carried out on the synchronous signal; optionally, the detection instruction may also be a memory initialization instruction.
After the memory receives the detection instruction, the synchronization signal may be input to a preset duty ratio detection circuit, or after the synchronization signal is coupled, the signal coupled to the synchronization signal may be input to the duty ratio detection circuit, which is not limited herein. The duty ratio detection circuit can detect the rising edge and the falling edge of the synchronous signal and then calculate the duty ratio according to the time interval between the rising edge and the falling edge; alternatively, the duty detection circuit may be a duty detection circuit as shown in fig. 6, in which a synchronization signal is input to the operational amplifier D1, the capacitor C1 is charged when the synchronization signal is at a high level, which is equivalent to integrating time to obtain a time length of the high level, and finally the duty of the synchronization signal is output by the potential detection module.
And S102, acquiring a duty ratio detection result sent by the memory.
After the memory obtains the duty ratio detection result of the synchronization signal, the processor may receive the duty ratio detection result sent by the memory through a communication connection with the memory.
S103, adjusting the synchronous signal according to the duty ratio detection result until the duty ratio detection result returned by the memory is within a preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
The processor may preset a duty ratio range, and when the duty ratio detected by the memory is within the preset duty ratio range, the eye distortion degree of the corresponding data signal may be smaller than a preset threshold. The preset duty cycle range may include upper and lower thresholds of the duty cycle, for example, greater than or equal to 48%, and less than or equal to 51%, and the processor may adjust the synchronization signal with the upper and lower thresholds as targets. Optionally, the preset duty ratio range includes a reference duty ratio, and the processor may adjust the synchronization signal with the reference duty ratio as a target, where the closer the duty ratio of the digital probe signal is to the reference duty ratio, the smaller the eye distortion degree of the data signal is. The preset duty cycle range further includes a difference threshold from the reference duty cycle, for example, the reference duty cycle of the preset range may be 50%, and the difference threshold of the duty cycle may be 1%, which corresponds to a duty cycle range of 49% to 51%; the form of the preset duty ratio range is not limited herein.
The processor may adjust the synchronization signal based on the duty cycle detection result. The processor may adjust the duration of the high level of the synchronization signal, and may also adjust the period of the synchronization signal, and the specific adjustment parameter is not limited herein. The processor can calculate a target parameter of the synchronous signal according to the duty ratio detection result, and also can determine an adjustment strategy of the synchronous signal according to the duty ratio detection result so as to determine whether to increase the duty ratio of the synchronous signal or decrease the duty ratio of the synchronous signal; the above adjustment method is not limited herein.
After the processor adjusts the synchronous signal, the adjusted synchronous signal can be sent to the memory, so that the memory can continue to detect the duty ratio of the synchronous signal and return a new duty ratio detection result. If the new duty ratio detection result returned by the memory is outside the preset duty ratio range, the processor can continue to adjust the synchronous signal until the returned duty ratio detection result is within the preset duty ratio range. If the duty ratio detection result returned by the memory is within the preset duty ratio range, the duty ratio detection can be determined to be finished, and the synchronous signal does not need to be adjusted. Alternatively, the processor may send a detection completion indication to the processor.
When the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than the preset threshold, that is, when the duty ratio of the synchronous signal returned by the memory is within the preset duty ratio range, the processor can consider that the duty ratio is adjusted in place, and the eye pattern deformity of the data signal caused by the larger or smaller duty ratio can be reduced by adopting the adjusted synchronous signal, so that the eye pattern quality of the data signal is improved.
In the optimization method of the eye pattern quality, the processor sends a detection instruction to the memory to instruct the memory to carry out duty ratio detection on the synchronous signal sent by the processor; because the duty ratio of the synchronous signal is related to the eye pattern distortion degree of the data signal sent to the memory by the processor, after the processor acquires the duty ratio detection result sent by the memory, the synchronous signal can be adjusted according to the duty ratio detection result until the duty ratio detection result returned by the memory is within the preset duty ratio range; when the duty ratio detection result of the synchronous signal is within the preset duty ratio range, the eye pattern distortion degree of the data signal is small, and the eye pattern deformity of the data signal caused by the larger or smaller duty ratio can be reduced by adopting the adjusted synchronous signal, so that the eye pattern quality of the data signal is improved, and the normal data communication between the processor and the memory is ensured.
Fig. 7 is a flowchart illustrating a method for optimizing eye diagram quality in an embodiment, where the embodiment relates to an implementation manner of adjusting a synchronization signal according to a duty ratio detection result by a processor, and on the basis of the above embodiment, as shown in fig. 7, the step S103 includes:
s201, comparing the duty ratio detection result with a preset duty ratio range, and determining the duty ratio adjustment direction of the synchronous signal.
The processor may determine a threshold for a preset duty cycle range, including a duty cycle upper limit and a duty cycle lower limit; further, comparing the value in the duty ratio detection result with the threshold, and if the value in the duty ratio detection result is smaller than the lower limit of the duty ratio, determining that the duty ratio adjustment direction of the synchronization signal is to increase the duty ratio of the synchronization signal; if the value in the duty ratio detection result is greater than the duty ratio upper limit, the duty ratio adjustment direction of the synchronization signal can be determined to be the duty ratio of the reduction synchronization signal.
S202, adjusting the time delay parameter of the synchronous signal according to the duty ratio adjusting direction until the duty ratio detection result returned by the memory is within the preset duty ratio range.
After determining the duty ratio adjustment direction, the processor may adjust the delay parameter of the synchronization signal according to the duty ratio adjustment direction. The delay parameter may include a rising delay of the synchronization signal, a falling delay of the synchronization signal, and a signal period of the synchronization signal. The rising time delay may be a time delay for the synchronization signal to rise from a low level to a high level in the signal period, and the falling time delay may be a time delay for the synchronization signal to fall from a high level to a low level in the signal period, as shown in fig. 8.
Optionally, when the processor adjusts the time delay parameter, if the duty ratio adjustment direction is to decrease the duty ratio of the synchronization signal, the rising time delay of the synchronization signal is increased according to a preset step; and if the duty ratio adjusting direction is to increase the duty ratio of the synchronous signal, the rising time delay is reduced according to the preset step.
The electronic equipment increases the rising time delay of the synchronous signal according to the preset steps, so that the duration of the low level of the synchronous signal is prolonged, the duration of the high level of the synchronous signal is shortened, and the duty ratio of the synchronous signal is reduced. The electronic device decreases the rising time delay of the synchronization signal according to the preset step, so that the duration of the high level of the synchronization signal is longer, and the duration of the low level of the synchronization signal is shorter, thereby increasing the duty ratio of the synchronization signal, as shown in fig. 8.
Further, when the duty ratio detection result is within the preset duty ratio range, the processor may determine the delay parameter corresponding to the duty ratio detection result as the target delay parameter of the synchronization signal.
According to the optimization method for the eye pattern quality, the processor can gradually adjust the duty ratio of the synchronous signal according to the adjustment direction by adjusting the time delay parameter of the synchronous signal, so that the duty ratio is quickly adjusted to the preset duty ratio range, the adjustment efficiency of the duty ratio is improved, the eye pattern quality of the data signal is improved, and the normal communication between the processor and the memory is ensured.
In one embodiment, on the basis of the above embodiment, the processor may send the detection instruction to the memory during the initialization of the memory.
According to the optimization method of the eye pattern quality, the processor can send the detection instruction to the memory in the process of initializing the memory, so that the adjustment of the synchronous signal can be completed in the initialization stage, the adjustment is not needed in the data transmission stage, the data transmission failure caused by the adjustment of the duty ratio of the synchronous signal is avoided, and the accuracy of data transmission is improved.
Fig. 9 is a flow diagram of a method for optimizing eye diagram quality in one embodiment. The optimization method of the eye diagram quality in this embodiment is described by taking the memory operating in fig. 1 as an example. As shown in fig. 9, the method includes:
s301, receiving a detection instruction sent by the processor.
S302, duty ratio detection is carried out on the synchronous signal sent by the processor based on the detection instruction; the duty cycle of the synchronization signal is related to the degree of eye distortion of the data signal sent to the memory by the processor.
S303, sending a duty ratio detection result to a processor; the duty ratio detection result is used for instructing the processor to adjust the synchronous signal according to the duty ratio detection result until the duty ratio detection result is within a preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
The implementation principle and technical effect of the method for optimizing the eye diagram quality are similar to those of the method for optimizing the processor side eye diagram quality, and are not described herein again.
It should be understood that although the various steps in the flow charts of fig. 2-9 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-9 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
Fig. 10 is a block diagram of an eye diagram quality optimization apparatus according to an embodiment. As shown in fig. 11, the above apparatus includes:
a sending module 110, configured to send a detection instruction to a memory; the detection instruction is used for instructing the memory to carry out duty ratio detection on the synchronous signal sent by the processor; the duty ratio of the synchronous signal is related to the eye distortion degree of the data signal sent to the memory by the processor;
an obtaining module 120, configured to obtain a duty ratio detection result sent by a memory;
the adjusting module 130 is configured to adjust the synchronization signal according to the duty ratio detection result until the duty ratio detection result returned by the memory is within the preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
In one embodiment, on the basis of the above embodiment, the synchronization signal is a digital probe signal sent from the processor to the memory, and the digital probe signal is used for identifying the transmission period of the data signal in one clock cycle.
In an embodiment, on the basis of the above embodiment, as shown in fig. 11, the adjusting module 130 includes:
a comparing unit 131, configured to compare the duty ratio detection result with a preset duty ratio range, and determine a duty ratio adjustment direction of the synchronization signal;
the adjusting unit 132 is configured to adjust a delay parameter of the synchronization signal according to the duty ratio adjusting direction until the duty ratio detection result returned by the memory is within the preset duty ratio range.
In an embodiment, on the basis of the foregoing embodiment, the adjusting unit 132 is specifically configured to: under the condition that the duty ratio adjusting direction is to reduce the duty ratio of the synchronous signal, increasing the rising time delay of the synchronous signal according to preset steps; the rising time delay is the time delay of the synchronous signal rising from low level to high level in the signal period; and when the duty ratio adjusting direction is to increase the duty ratio of the synchronous signal, the rising time delay is reduced according to a preset step.
In an embodiment, on the basis of the above embodiment, as shown in fig. 12, the apparatus further includes a determining module 140 configured to: and under the condition that the duty ratio detection result is within the preset duty ratio range, determining the time delay parameter corresponding to the duty ratio detection result as the target time delay parameter of the synchronous signal.
In an embodiment, on the basis of the foregoing embodiment, the sending module 110 is specifically configured to: during the process of initializing the memory, a detection instruction is sent to the memory.
In one embodiment, on the basis of the above embodiment, the preset duty ratio range includes a reference duty ratio, and the closer the duty ratio of the digital probe signal is to the reference duty ratio, the smaller the degree of eye distortion of the data signal.
Fig. 13 is a block diagram of an eye diagram quality optimization apparatus according to an embodiment. As shown in fig. 13, the above apparatus includes:
a receiving module 210, configured to receive a detection instruction sent by a processor;
a detection module 220, configured to perform duty cycle detection on the synchronization signal sent by the processor based on the detection instruction; the duty ratio of the synchronous signal is related to the eye distortion degree of the data signal sent to the memory by the processor;
an indicating module 230, configured to send a duty ratio detection result to the processor; the duty ratio detection result is used for instructing the processor to adjust the synchronous signal according to the duty ratio detection result until the duty ratio detection result is within a preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
The division of the modules in the above-mentioned eye diagram quality optimization device is only used for illustration, and in other embodiments, the eye diagram quality optimization device may be divided into different modules as needed to complete all or part of the functions of the above-mentioned eye diagram quality optimization device.
For the specific definition of the optimization device for the eye diagram quality, reference may be made to the above definition of the optimization method for the eye diagram quality, which is not described herein again. The modules in the eye diagram quality optimization device can be wholly or partially realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, an electronic device is provided, the electronic device comprising a processor and a memory, wherein:
the processor is used for sending a detection instruction to the memory;
the memory is used for receiving a detection instruction sent by the processor; based on the detection instruction, carrying out duty ratio detection on the synchronous signal sent by the processor, and sending a duty ratio detection result to the processor; wherein, the duty ratio of the synchronous signal is related to the eye pattern distortion degree of the data signal sent to the memory by the processor;
the processor is used for adjusting the synchronous signal according to the duty ratio detection result until the duty ratio detection result returned by the memory is within the preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
Fig. 14 is a schematic diagram of an internal structure of an electronic device in one embodiment. The electronic device may be any terminal device such as a mobile phone, a tablet computer, a notebook computer, a desktop computer, a PDA (Personal Digital Assistant), a POS (Point of Sales), a vehicle-mounted computer, and a wearable device. The electronic device includes a processor and a memory connected by a system bus. The processor may include one or more processing units, among others. The processor may be a CPU (Central Processing Unit), a DSP (Digital Signal processor), or the like. The memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The computer program can be executed by a processor for implementing an eye diagram quality optimization method provided by the above embodiments. The internal memory provides a cached execution environment for the operating system computer programs in the non-volatile storage medium.
The implementation of each module in the eye diagram quality optimization device provided in the embodiment of the present application may be in the form of a computer program. The computer program may be run on a terminal or a server. Program modules constituted by such computer programs may be stored on the memory of the electronic device. Which when executed by a processor, performs the steps of the method described in the embodiments of the present application.
The embodiment of the application also provides a computer readable storage medium. One or more non-transitory computer-readable storage media containing computer-executable instructions that, when executed by one or more processors, cause the processors to perform the steps of a method for optimization of eye diagram quality.
Embodiments of the present application also provide a computer program product containing instructions which, when run on a computer, cause the computer to perform a method of optimizing eye diagram quality.
Any reference to memory, storage, database, or other medium used herein may include non-volatile and/or volatile memory. The nonvolatile Memory may include a ROM (Read-Only Memory), a PROM (Programmable Read-Only Memory), an EPROM (Erasable Programmable Read-Only Memory), an EEPROM (Electrically Erasable Programmable Read-Only Memory), or a flash Memory. Volatile Memory can include RAM (Random Access Memory), which acts as external cache Memory. By way of illustration and not limitation, RAM is available in many forms, such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), Double Data Rate DDR SDRAM (Double Data Rate Synchronous Random Access Memory), ESDRAM (Enhanced Synchronous Dynamic Random Access Memory), SLDRAM (Synchronous Link Dynamic Random Access Memory), RDRAM (Random Dynamic Random Access Memory), and DRmb DRAM (Dynamic Random Access Memory).
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (12)
1. A method for optimizing eye diagram quality, comprising:
sending a detection instruction to a memory; the detection instruction is used for instructing the memory to carry out duty cycle detection on a synchronous signal sent by a processor; the duty cycle of the synchronous signal is related to the eye distortion degree of the data signal sent to the memory by the processor;
acquiring a duty ratio detection result sent by the memory;
adjusting the synchronous signal according to the duty ratio detection result until the duty ratio detection result returned by the memory is within a preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
2. The method of claim 1, wherein the synchronization signal is a digital probe signal sent by a processor to the memory, the digital probe signal identifying a transmission period of the data signal within one clock cycle.
3. The method according to claim 1 or 2, wherein the adjusting the synchronization signal according to the duty cycle detection result until the duty cycle detection result returned by the memory is within a preset duty cycle range comprises:
comparing the duty ratio detection result with the preset duty ratio range to determine the duty ratio adjustment direction of the synchronous signal;
and adjusting the time delay parameter of the synchronous signal according to the duty ratio adjusting direction until the duty ratio detection result returned by the memory is within a preset duty ratio range.
4. The method of claim 3, wherein the adjusting the delay parameter of the synchronization signal according to the duty cycle adjustment direction comprises:
if the duty ratio adjusting direction is to reduce the duty ratio of the synchronous signal, increasing the rising time delay of the synchronous signal according to a preset step; the rising time delay is the time delay of the synchronous signal rising from a low level to a high level in a signal period;
and if the duty ratio adjusting direction is to increase the duty ratio of the synchronous signal, reducing the rising time delay according to a preset step.
5. The method of claim 3, further comprising:
and if the duty ratio detection result is within the preset duty ratio range, determining a time delay parameter corresponding to the duty ratio detection result as a target time delay parameter of the synchronous signal.
6. The method of claim 1 or 2, wherein sending the detection instruction to the memory comprises:
and sending the detection instruction to the memory in the process of initializing the memory.
7. The method of claim 2, wherein the preset duty cycle range comprises a reference duty cycle, and wherein the closer the duty cycle of the digital probe signal is to the reference duty cycle, the less the eye distortion of the data signal is.
8. A method for optimizing eye diagram quality, comprising:
receiving a detection instruction sent by a processor;
performing duty ratio detection on the synchronous signal sent by the processor based on the detection instruction; the duty cycle of the synchronous signal is related to the eye distortion degree of a data signal sent to a memory by the processor;
sending a duty cycle detection result to the processor; the duty ratio detection result is used for instructing the processor to adjust the synchronous signal according to the duty ratio detection result until the duty ratio detection result is within a preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
9. An apparatus for optimizing eye diagram quality, comprising:
the sending module is used for sending a detection instruction to the memory; the detection instruction is used for instructing the memory to carry out duty cycle detection on a synchronous signal sent by a processor; the duty cycle of the synchronous signal is related to the eye distortion degree of the data signal sent to the memory by the processor;
the acquisition module is used for acquiring the duty ratio detection result sent by the memory;
the adjusting module is used for adjusting the synchronous signal according to the duty ratio detection result until the duty ratio detection result returned by the memory is within a preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
10. An apparatus for optimizing eye diagram quality, comprising:
the receiving module is used for receiving a detection instruction sent by the processor;
the detection module is used for carrying out duty ratio detection on the synchronous signal sent by the processor based on the detection instruction; the duty cycle of the synchronous signal is related to the eye distortion degree of a data signal sent to a memory by the processor;
the indicating module is used for sending a duty ratio detection result to the processor; the duty ratio detection result is used for instructing the processor to adjust the synchronous signal according to the duty ratio detection result until the duty ratio detection result is within a preset duty ratio range; and when the duty ratio detection result is within the preset duty ratio range, the eye pattern distortion degree of the data signal is smaller than a preset threshold.
11. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program, characterized in that the computer program, when executed by the processor, causes the processor to carry out the steps of the method of optimizing eye diagram quality according to any one of claims 1 to 7.
12. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 8.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114360598A (en) * | 2021-12-28 | 2022-04-15 | 海光信息技术股份有限公司 | Duty cycle training circuit, duty cycle adjusting method and memory controller |
| CN117312086A (en) * | 2023-10-10 | 2023-12-29 | 上海合芯数字科技有限公司 | Method, device, equipment and medium for adjusting USB interface of server |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002082830A (en) * | 2000-02-14 | 2002-03-22 | Mitsubishi Electric Corp | Interface circuit |
| US20090300260A1 (en) * | 2008-05-28 | 2009-12-03 | Rambus Inc. | Selective switching of a memory bus |
| CN103703702A (en) * | 2011-03-25 | 2014-04-02 | 应美盛股份有限公司 | System, apparatus, and method for time-division multiplexed communication |
| CN105808395A (en) * | 2016-03-03 | 2016-07-27 | 北京小米移动软件有限公司 | Intelligent device USB eye pattern improvement method |
| CN109791530A (en) * | 2016-10-10 | 2019-05-21 | 英特尔公司 | Multi-core hardware processor and method |
| CN110083562A (en) * | 2018-01-26 | 2019-08-02 | 辉达公司 | The system and method that reference noise for single ended serial link compensates |
| US10734983B1 (en) * | 2019-02-15 | 2020-08-04 | Apple Inc. | Duty cycle correction with read and write calibration |
-
2021
- 2021-06-24 CN CN202110707812.XA patent/CN113342722A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002082830A (en) * | 2000-02-14 | 2002-03-22 | Mitsubishi Electric Corp | Interface circuit |
| US20090300260A1 (en) * | 2008-05-28 | 2009-12-03 | Rambus Inc. | Selective switching of a memory bus |
| CN103703702A (en) * | 2011-03-25 | 2014-04-02 | 应美盛股份有限公司 | System, apparatus, and method for time-division multiplexed communication |
| CN105808395A (en) * | 2016-03-03 | 2016-07-27 | 北京小米移动软件有限公司 | Intelligent device USB eye pattern improvement method |
| CN109791530A (en) * | 2016-10-10 | 2019-05-21 | 英特尔公司 | Multi-core hardware processor and method |
| CN110083562A (en) * | 2018-01-26 | 2019-08-02 | 辉达公司 | The system and method that reference noise for single ended serial link compensates |
| US10734983B1 (en) * | 2019-02-15 | 2020-08-04 | Apple Inc. | Duty cycle correction with read and write calibration |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114360598A (en) * | 2021-12-28 | 2022-04-15 | 海光信息技术股份有限公司 | Duty cycle training circuit, duty cycle adjusting method and memory controller |
| CN117312086A (en) * | 2023-10-10 | 2023-12-29 | 上海合芯数字科技有限公司 | Method, device, equipment and medium for adjusting USB interface of server |
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