CN103703702A - System, apparatus, and method for time-division multiplexed communication - Google Patents

Abstract

A simplified bus arrangement using only three signal lines allows TDM data to be conveyed to or from a number of slave -only devices without the use of separate command line(s) and without any of the slave-only devices having to operate as a bus master or even support a master operating mode.

Description

System, equipment and method for time division multiplexing communication

The cross reference of related application

Present patent application requires the priority of the U.S. Patent application No.13/071836 submitting on March 25th, 2011 and the U.S. Provisional Patent Application No.61/467538 submitting on March 25th, 2011, at this, by reference each in described document is incorporated to herein in full.

Technical field

Present invention relates in general to communicator that daisy chain connects synchronously, synchronous, addressing and serialization signal are processed again.

Background technology

In some communication system, a plurality of devices send data by being logically divided into the communication channel (single bus) of some time slots in succession to controller, and wherein, each time slot has predetermined figure.Each device sends data to controller according to time slot allocation scheme in the time slot of one or more appointments, and in some communication systems, described time slot allocation scheme is fixed, and in other communication systems, is variable.Described device often sends according to fixing regular interval, therefore often logically described communication channel is divided into some frames, the time slot that each frame contains predetermined quantity, and each device sends by the corresponding time slot in each frame.Thereby for example, first device can send in the first time slot of each frame, the second device can send in the second time slot of each frame, etc.In some systems, device can send by a plurality of time slots, and for example, first device can send in the first and second time slots of each frame, and the second device can send in the third and fourth time slot of each frame, etc.In some systems, different devices can send in the time slot of varying number, for example, first device can send in the first time slot of each frame, the second device can send in the second and the 3rd time slot of each frame, and the 3rd device can send in the 4th time slot of each frame, etc.

For convenience's sake, in literary composition, by adopting N to represent the quantity of the time slot of each frame, in literary composition, by adopting B to represent the figure place of each time slot, in literary composition, will adopt M indication device quantity.Specific embodiment can have 8 32 digit time slots (that is, N=8, B=32) by (for example) every frame, but the invention is not restricted to the particular value of any N and B.The real data sending in each time slot can adopt all B position, or for example can adopt, than all B the position (, can transmit by 32 digit time slots 24 samples of digital audio) that position is few.In various systems, between SCK and position, may there is one-one relationship (for example, for each SCK cycle), or have other relations (for example, the cycle of each two or more SCK) between SCK and position.

Fig. 1 schematically shows the example system with some device 1041-104M, and described device sends data according to TDM mode known in the art to controller 102.In this exemplary configuration, described controller plays a part bus master, and all subordinates play a part slave unit.Controller 102 provides clock signal (SCK) and frame synchronizing signal (WS) to all devices 104.Controller 102 also sends order (for example, the unique address based on each device 104) by one or more order wire to device 104, thereby (for example) carries out time slot configuration for each device 104, to send data by data wire (SD).On the basis of SCK and FS signal, by controller 102, provide configuration information, each device 104 time slot by the one or more appointments on SD line sends.

Fig. 2 schematically shows another and has some example system of the device 2041-204M of data that send to controller 202 according to TDM mode known in the art.This example system (shown in the open text US2008/0069151 of the U.S. of " Variable Time Division Multiplex Transmission System " by name that itself and Satoh etc. submit to and the configuration of describing similar, at this, by reference the document is incorporated in full herein) in, each device 204 not only comprises main operation logic but also comprises from operation logic, for example, can adopt hardware pin on device that the operator scheme of each device 204 is set.In this one exemplary embodiment, first device 2041 as bus master work (is for example set to, by M/S pin, arrange), and described first device 2041 not only provided clock signal to controller 202 but also to other devices 204, described other devices 204 are for example set to, as slave unit work (, arranging by corresponding M/S pin).Device 2041 also provides frame synchronizing signal to controller 202, to mark the beginning of each frame, and to the second device 2042 in described chain, provides the synchronizing signal of delay, to mark the beginning of the time slot of this device.Start from each slave unit in the described chain of the second device 2042 frame synchronizing signal of delay is provided to next device in succession in described chain.

At Low-Power, Highly-Integrated, Programmable16-Bit, 26-KSPS, Dual-Channel CODEC(Texas Instruments, Revised April2005) shown in and described a kind of similar system, at this, by reference it is incorporated in full herein.Particularly, Figure 20 of the document shows the device that some cascades connect, and wherein, the first device in described cascade is configured to main device, and the DSP in described cascade and all the other devices are all as the slave unit work of described main device.Each slave unit is configured to provide to next slave unit in succession to the frame synchronizing signal of delay, described device can be determined the quantity of the device in described cascade automatically, and can automatically distribute address to described device.A problem relevant to such configuration be, all devices had all both carried main logic, carried again subordinate logic, wherein, and by the master/slave operation of M/S pin choice device.Each device has especially increased cost and the complexity of each device as main device or from the ability of device work.

Summary of the invention

According to an aspect of the present invention, provide a kind of system for time division multiplex communication, it comprises: data wire; Comprise clock output for clock signal is provided, for provide the some frames in succession of indication each the frame synchronization output of frame synchronizing signal of beginning and the controller that is coupled to the data pin of described data wire; And at least one communicates by letter with described controller is only the device of subordinate.Each only comprises the data pin of inputting, be coupled to described data wire for receiving the clock of described clock signal, frame synchronization input and the frame synchronization output of the clock output that is coupled to described controller for the device of subordinate.Described controller and described at least one only for the device of subordinate is to take interconnection in the chain type structure that described controller is starting point, wherein, by each only for the frame synchronization that the frame synchronization input of the device of subordinate is coupled to the last device in described chain is exported.Described controller provides frame synchronizing signal in its frame synchronization output, and in data transfer mode, each is only for the device of subordinate provides the frame synchronizing signal from its frame synchronization input that has occurred to postpone to its frame synchronization output, and by its data pin, access described data wire in the predetermined time slot group of each frame, thereby realize to the data of described controller send and from the data receiver of described controller at least one of them, wherein, described predetermined time slot group is that described only for the device of subordinate, the frame synchronizing signal based on receiving in its frame synchronization input and the clock signal that receives in its clock input are selected only.

In various alternate embodiments, one or more described in only for the device of subordinate can comprise digital MEMS microphone.Described system can comprise single only for the device of subordinate or can to comprise a plurality of be only the device of subordinate in described chain, and only can fix for the quantity of the device of subordinate in described chain, also can change.Can by all only for the device of subordinate be configured to access each frame equal number time slot (for example, a time slot of every frame, two time slots of every frame etc.), or can by least two only for the device of subordinate be configured to access every frame varying number time slot (for example, a device can be accessed a time slot of every frame, and another device can be accessed two time slots of every frame etc.).All can be only the device (for example, being all digital MEMS microphone) of same type for the device of subordinate, or described only at least two in the device of subordinate can be dissimilar device.In certain embodiments, can be by a plurality of only for the device of subordinate be integrated on one single chip, described one single chip also can comprise described controller.

In other embodiments, can by each only for the device of subordinate be configured to determine based on described clock signal and frame synchronizing signal that described controller supports only for the maximum quantity of the device of subordinate (for example, clock number to each frame is counted, by it, determine the timeslot number of every frame, and determine that by it what support is only the maximum quantity of the device of subordinate).Each is only for the data pin of the device of subordinate can comprise programmable driver, in this case, can by each only for the device of subordinate be configured to based on described controller support only for the maximum quantity of the device of subordinate is programmed to the power setting of described programmable driver.

Should be understood that, can be in the situation that the data pin that is only the device of subordinate by each be disposed for data to send to by described data wire the output of described controller, in the situation that the data pin that is only the device of subordinate by each is disposed for the input from described controller receiving data by described data wire, or be configured to allow in the situation that described controller and the described I/O pin that only carries out two-way communication between the device for subordinate are realized each embodiment in the data pin that by each is only the device of subordinate.

According to a further aspect in the invention, provide a kind of device for working at system for time division multiplex communication.Described device comprise clock input for receive clock signal, for receive the some successive frames of indication each beginning frame synchronizing signal frame synchronization input, for the frame synchronization output of the frame synchronizing signal of output delay and be coupled to described clock input, frame synchronization input and frame synchronization export and comprise for be coupled to data wire data pin be only the TDM bus interface of subordinate.Described TDM bus interface is configured to frame synchronization output, provide the frame synchronizing signal from frame synchronization input that delay has occurred in data transfer mode, and by data pin, access described data wire in the predetermined time slot group of every frame, thereby realize to the data of described data wire send and from the data receiver of described data wire at least one of them, wherein, described predetermined time slot group is that described only for the TDM bus interface of subordinate, the frame synchronizing signal based on receiving in described frame synchronization input and the clock signal that receives in described clock input are selected only.

In various alternate embodiments, described device can comprise digital MEMS microphone.In described TDM bus interface can being configured to determine chain based on described clock signal and the frame synchronizing signal that receives in the input of described frame synchronization, support only for the maximum quantity of the device of subordinate (for example, clock number to every frame is counted, by it, determine the timeslot number of every frame, and determine that by it what support is only the maximum quantity of the device of subordinate).Described data pin can comprise programmable driver, in this case, described TDM bus interface can be configured to based on described only for the maximum quantity of the device of subordinate is programmed to the power setting of described programmable driver.

Should be understood that, can be in the situation that data pin be disposed for sending the output of data on described data wire, in the situation that data pin is disposed for receiving from described data wire the input of data, or in the situation that be configured to allow the I/O pin that carries out two-way communication by described data wire to realize each embodiment data pin.

Can disclose extra embodiment and advocate the protection to it.

Accompanying drawing explanation

With reference to accompanying drawing, by following, to of the present invention, further illustrate the above and other advantage that present invention will become more fully understood, wherein:

Fig. 1 schematically shows has some example system of the device of data that send to controller according to TDM mode known in the art;

Fig. 2 schematically shows another and has some example system of the device of data that send to controller according to TDM mode known in the art;

Fig. 3 schematically shows the TDM communication system according to one exemplary embodiment of the present invention;

Fig. 4 schematically shows according to the associated components of the digital MEMS microphone of one exemplary embodiment of the present invention;

Fig. 5 schematically shows according to the associated components of the TDM bus interface of one exemplary embodiment of the present invention;

Fig. 6 schematically shows according to the general operation of the slave unit in normal operating conditions of one exemplary embodiment of the present invention;

Fig. 7 schematically shows controller and supports every frame to have nearly 8 time slots (being N=8), and in described chain, has the exemplary sequential chart of the embodiment of the slave unit that 8 (being M=8) send by 32 digit time slots in every frame;

Fig. 8 schematically shows controller and supports every frame to have nearly 8 time slots (being N=8), but in described chain, only has the exemplary sequential chart of the embodiment that 4 slave units (being M=4) and each slave unit 32 digit time slots by every frame send;

Fig. 9 schematically shows controller and supports every frame to have the exemplary sequential chart of the embodiment that by every frame two 32 digit time slots in succession of 8 time slots (being N=8) nearly and described slave unit send;

Figure 10 schematically shows according to the transmission of 24 samples in 32 of one exemplary embodiment of the present invention frames;

Figure 11 schematically shows according to the transmission of the order succeeded by initial data in time slot of one exemplary embodiment of the present invention;

Figure 12 schematically shows according to the conversion from low to high of the valid frame signal of one exemplary embodiment of the present invention, and the work period of frame synchronizing signal (duty cycle) is the demonstration sequential chart of the embodiment of a SCK;

Figure 13 schematically shows and adopts the sequential shown in Figure 12 as in Figure 10, in 32 frames, to transmit 24 samples;

Figure 14 schematically shows according to the interrelated logic piece of the circuit that dynamically generates internal work clock of one exemplary embodiment of the present invention;

Figure 15 is the flow chart for TDM operation according to one exemplary embodiment of the present invention;

Figure 16 schematically show according to one exemplary embodiment of the present invention for according to the sequential chart of the operation of the process of Figure 15;

Figure 17 schematically shows according to the interrelated logic piece of the circuit of dynamically setting SD pin power level of one exemplary embodiment of the present invention;

Figure 18 schematically show according to one exemplary embodiment of the present invention for making the microphone sequential chart in synchronous auto-initiation stage;

Figure 19 is according to the flow chart of five frame auto-initiation methods of one exemplary embodiment of the present invention;

Figure 20 schematically shows the TDM working condition according to one exemplary embodiment of the present invention, and under this situation, slave unit is sampled and sends according to synchronization mode;

Figure 21 schematically shows a kind of TDM working condition as an example, and in described situation, one of slave unit has lost synchronously in the middle of the operation shown in Figure 20;

Figure 22 schematically show according to one exemplary embodiment of the present invention be used for make slave unit can automatically determine the sequential chart of its relevant position in daisy chain;

Figure 23 schematically shows the synchronizing sequence again for described TDM daisy chain according to one exemplary embodiment of the present invention;

Figure 24 schematically show according to one exemplary embodiment of the present invention for adopting the sequential chart of frame signal configuration slave unit address;

Figure 25 schematically shows the daisy chain configuration of type discussed above, but it also comprises I2C bus (being SDA and SCLK line);

Figure 26 schematically show according to one exemplary embodiment of the present invention for by the sequential chart of I2C bus configuration slave unit address in succession;

Figure 27 A schematically shows according to the flow chart of the slave unit address allocation pattern for the type shown in Figure 26 of one exemplary embodiment of the present invention;

Figure 27 B schematically shows according to the state transition diagram of the slave unit address allocation pattern for the type shown in Figure 27 A of one exemplary embodiment of the present invention;

Figure 28 schematically shows the daisy chain configuration for generation of set output according to one exemplary embodiment of the present invention.

It should be pointed out that above-mentioned accompanying drawing with and the element of interior drafting may not be according to consistent ratio or according to any scale.Unless context points out, otherwise all by element like similar Reference numeral representation class.

Embodiment

In an embodiment of the present invention, only adopt the simplification bus arrangement of three signal line to allow controller in the situation that not adopting order wire and in the situation that not needing to make any slave unit must serve as bus master and even support main mode of operation, to some be only the device of subordinate send tdm data and/or from some be only the device reception tdm data of subordinate.Described controller is configured to provide the frame synchronizing signal WS of the beginning of bit clock signal SCK and each frame of mark.Described SCK signal is passed to all slave units, described ws signal is passed to the first device in described chain simultaneously, and making it from a slave unit to another slave unit, carry out daisy chain connection, each slave unit increases the delay of scheduled volume to described ws signal.On described SCK signal and daisy chain are gone forward one by one the basis of ws signal, each slave unit can be determined its corresponding time slot automatically, and without any need for the dedicated signaling independently installing.Embodiments of the invention especially allow to remove or omit order wire, also especially allow from slave unit, to remove or omit main logic (and M/S pin), thereby no matter be all to have saved space for controller or to slave unit, reduced complexity, and/or reduced power consumption, especially in the middle of a plurality of slave units being attached to the embodiment in single assembly (for example, wherein, on wafer or integrated circuit, identical slave unit logical block is copied M time, and in described slave unit logical block, without any logical block, comprise main logic or order wire).Typically, controller operation be identical and no matter the actual quantity of the slave unit on data wire how, this has greatly simplified system and operation.

Fig. 3 schematically shows the TDM communication system according to one exemplary embodiment of the present invention.In this one exemplary embodiment, controller 302 plays a part bus master, it provides SCK to all slave units 304, and provide WS to the first slave unit 3041, wherein, ws signal is gone forward one by one to the WS input (WSI) (note, WSOx is the WSO signal from device x) of next slave unit in succession from WS output (WSO) daisy chain of each slave unit.Controller 302 can be configured to support every frame have the time slot of predetermined quantity (N), in the situation that each slave unit being configured to by transmission in time slot of every frame or receiving, described daisy chain can have nearly N slave unit.In various embodiments, can adopt all time slots also can adopt the part time slot in whole time slots.For example, controller 302 can be configured to support nearly 16 slave units, each sends in time slot of every frame, different modification can have from one to 16 slave unit not etc. (typically according to the needs of specific product or realization or expection, N is 2 power, but this not necessarily).The quantity of slave unit can be (for example, be integrated in M slave unit on one single chip or have the discrete design of the parts of fixed qty) of fixing, and can be also (for example, can As time goes on and increase and decrease slave unit) changing.

Once enable, described slave unit starts according to specific frequency dividing ratio, SCK to be inputted and carries out frequency division conventionally, to generate internal work clock, for example, it is for carrying out timing to analog to digital converter (ADC), to generate the numeral sample of analog input, or carry out timing for logarithmic mode transducer (DAC), thereby the numeral sample receiving is changed to (by SD line) and start according to the mode of below discussing, according to the mode of below discussing, on described SD line, send (or reception) data.Can be by any mode in variety of way (for example, in can the clock signal on SCK line being detected or adopt independent chip enable signal) (for example enable described slave unit, each slave unit 304 can have chip and enable pin, wherein, the chip of described slave unit is enabled to pin and be connected to public chip enable signal, for example, the chip of controller 302 is enabled output pin, it allows to enable selectively slave unit, or can simply the chip of slave unit be enabled to pin and be connected to high potential, thereby make it always in initiate mode).

In an embodiment of the present invention, controller can be the device of any suitable programming or configuration, such as digital signal processor (DSP), microcontroller, integrated circuit, field programmable gate array, discrete logic etc.In specific embodiment described below, in normal (data transmission) operation, controller is configured to generate WS and SCK signal, make fSCK=N*B*fWS(every N*B SCK cycle generate described ws signal, for example,, for B=32 clock SCK cycle/time slot, N=8 time slot/frame, fSCK=256*fWS), still in various alternate embodiments, also can adopt other signal timings.The device of some types (for example, some non-customized DSP and microcontroller) has built-in programmable timer, and the generation of described WS and SCK signal can relate to the suitable programming to described timer, to generate WS and the SCK clock with appropriate frequency.Or described controller can comprise the custom hardware logic that generates described WS and SCK signal.

And, in an embodiment of the present invention, described slave unit can be any transmission and/or the device that receives digital information, for example, (for example carry out analog-to-digital device, the MEMS device of numeral MEMS microphone and other types, for example, free gyroscope, accelerometer, pressure sensor, oscillator etc. and audio codec, communication/networking transceiver etc.), (for example carry out the device of digital-to-analogue conversion, audio codec, communication/networking transceiver etc.) or the device of other types (for example, microprocessor or digital signal processor), it comprises the combination of the dissimilar device in same bus.

In a specific embodiment, slave unit is digital MEMS microphone, and wherein, each digital MEMS microphone provides digitized audio sample to controller.Compare with the microphone of other kinds, digital MEMS microphone is conventionally less, more cheap, and more flexible, and it is integrated microphone, amplifier, analog to digital converter (ADC) and digital signal processing block that some is possible on one single chip conventionally.Often adopt a plurality of microphones to form an array, it can significantly improve systematic function simultaneously.Such microphone array is listed in a lot of fields and has a wide range of applications, and for example, aspect phone, speech recognition system and auditory localization, this just slightly gives a few examples certainly.The simple TDM interface of describing in literary composition makes the realization of such microphone array simple, and has low cost.

Fig. 4 schematically shows according to the associated components of the digital MEMS device such as microphone or other devices of one exemplary embodiment of the present invention.Described digital MEMS device especially comprises the simulation part with MEMS device and ADC modulator 402, (for example also especially comprise the numerical portion of digital engine 404, digital engine for MEMS microphone can comprise the parts such as digital filter and controller), and TDM bus control unit 410.

TDM operation

Fig. 5 schematically shows according to the associated components of the TDM bus control unit 410 of one exemplary embodiment of the present invention.Although it should be pointed out that the parts that in literary composition, TDM bus control unit 410 are described as to digital MEMS device, such TDM bus control unit 410 is common to the slave unit adopting in embodiments of the invention.Described TDM bus control unit 410 especially comprises the delay block 502 that generates WSO signal, the WSI that described WSO signal has normally been delayed, and delay amplitude is to distribute to the number of the slot time of described slave unit, wherein, a slot time equals B position.In basic embodiment of the present invention, between SCK and position, there is man-to-man relation, each slave unit sends in the single time slot of each frame, and delay block 502 makes B the SCK cycle of WSI signal delay conventionally.As mentioned above, one or more slave units can be configured to send or receive in a plurality of time slots, in this case, delay block 502 will make the slot time of described WSI signal delay right quantity.TDM bus control unit 410 is also included in the TDM bus interface 506 that sends (or reception) initial data 504 on the basis of described WSI and SCK signal by SD line.For example, when WSI signal being detected, TDM bus interface 506 can send initial data in the time slot of the quantity for this device appointment on described SD line, or similarly, can in the time slot of the quantity for this device appointment, receive the initial data from described SD line.

Fig. 6 schematically shows according to the general operation of the slave unit in normal operating conditions of one exemplary embodiment of the present invention.(it can be when slave unit is enabled in normal operation, also can be after initial phase as discussed below), each slave unit is accessed SD data wire when receiving effective frame signal by its WSI pin, in frame signal described in this example, it is conversion from high to low, but also can adopt other signalings (for example, conversion from low to high, the signal level in SCK cycle that continues predetermined quantity or predetermined sequence or conversion).Conventionally, just adopt the beginning of ws signal indication frame, in this case, the duty ratio of WS is not particular importance, and to realize it can be different (showing 50% duty ratio) for different.Conventionally, each slave unit is received or is sent by a time slot of each frame, and for example, each slave unit receives or send the data that can reach B position after receiving effective frame signal by its WSI pin.As mentioned above, one or more slave units can be configured to utilize a plurality of time slots, thereby (for example) is configured to by two time slots, be sent or received after receiving valid frame signal by its WSI pin by slave unit the data that reach as high as (2*B) position.When not sending, the SD pin (output) of slave unit is (being high-impedance state) of tri-state, and it allows other slave units to drive bus.By ws signal daisy chain being gone forward one by one and each slave unit makes ws signal postpone an integer slot time (being generally a slot time may be still also a plurality of slot times), described slave unit can be in the situation that access described SD line in time slot in succession without any need for the order of independently installing.The WSO signal that it should be pointed out that the last device (being unshowned WSOM) that described daisy chain is central in this example is the signal that does not add use that does not drive the WSI pin of another slave unit.

Fig. 7 schematically shows controller and supports every frame to have nearly 8 time slots (being N=8), and in described chain, has the exemplary sequential chart of embodiment that carries out 8 (being M=8) slave units of sending and receiving by 32 digit time slots in every frame.The SCK signal that the frequency that described controller generated frequency is ws signal is multiplied by N*B or 256 (that is, fSCK=B*N*fWS=256*fWS).By ws signal daisy chain is gone forward one by one, described eight slave units respectively time slot in succession of eight by every frame send.

Fig. 8 schematically shows controller and supports every frame to have nearly 8 time slots (being N=8), but in described chain, only has the exemplary sequential chart of the embodiment that 4 slave units (being M=4) and each slave unit 32 digit time slots by every frame send or receive.In this example, the SCK signal that the frequency that described controller generated frequency is ws signal is multiplied by N*B or 256 (that is, fSCK=B*N*fWS=256*fWS).By described ws signal is carried out to daisy chain, go forward one by one, described four slave units respectively by every frame front four in succession time slot send or receive, four time slots of all the other of every frame are not used.

Fig. 9 schematically shows controller and supports every frame to have the exemplary sequential chart (showing for convenience's sake the sequential of two devices) of the embodiment that by every frame two 32 digit time slots in succession of 8 time slots (being N=8) nearly and described slave unit send or receive.

It should be pointed out that the operation of controller aspect the generation of WS and SCK signal is identical with the embodiment shown in Fig. 7-9, although the quantity of the slave unit having and/or time slot allocation are different.

For example, although each time slot in TDM bus is B position (, being 32 in above-described example), slave unit can send or receive the initial data that is less than B position in each time slot, thereby some positions in time slot are obsolete.Figure 10 schematically shows according to the transmission of 24 bit data samples in 32 digit time slots of one exemplary embodiment of the present invention.In this example, after the frame synchronizing signal detecting on WSI line, slave unit sends or receives 24 samples in the D1-D24 of the position of described time slot, wherein, in this example, from receiving described WSI signal, make D1 postpone a SCK cycle, and have seven SCK clock cycle after following D24 closely.The transmission of 24 bit data samples is particularly useful for 24 samples (or being converted to the bit stream that can be divided into 24 sections) voice applications that audio conversion is changed to such as digital MEMS microphone.It should be pointed out that this just transmits an example that is less than B position in each B digit time slot.

Or or in addition, can in each time slot, together with described initial data, transmit other information.Figure 11 schematically shows according to the transmission of the control/command information succeeded by initial data in time slot of one exemplary embodiment of the present invention.For example, in 32 digit time slots, can after 8 control/command informations, follow 24 initial data.Can to described control/command information, (for example encode by any mode in the middle of variety of way, unit or multiple bit fields), described control/command information can be passed on any information in various information (for example, the encoding scheme of slave unit identifier or address, initial data, number of timeslots, power level, operating state or other information relevant to slave unit).It should be pointed out that this just transmits an example of the information of a plurality of types in time slot.

In above-described example, by the map table from high to low on WSI line, show effective frame signal, the duty ratio of frame synchronizing signal is 50%.Yet, as mentioned above, can adopt frame signal and the duty ratio of other types.It is the conversion from low to high and work period of frame synchronizing signal is the demonstration sequential chart of the embodiment of a SCK that Figure 12 schematically shows according to the valid frame signal of one exemplary embodiment of the present invention.Figure 13 schematically shows and adopts the sequential shown in Figure 12 as in Figure 10, in 32 frames, to transmit 24 samples.

It should be pointed out that to be the two-way communication between support controller and slave unit by TDM Interface realization.For example, can in some designated frame, even in some assigned timeslot, send the outbound information from controller to slave unit, can in other designated frames or time slot, send the inbound communication from described slave unit to described controller.For example, described device can be in some frame according to outbound data work pattern (for example, for example, at the initial phase that adopts () address and/or job information that slave unit is configured/is programmed), in other frames for example, according to inbound communication pattern work (, after initial phase).Or or in addition, described device can replace on basis frame by frame or on other bases between departures and inbound communication pattern.

As mentioned above and below discuss more fully, can be by any mode in variety of way only for the device distribution address of subordinate (for example, hard coded, employing controller distributes, by described be only that the device of subordinate is automatically determined etc.), can adopt such addressing scheme to realize between controller and slave unit, and even the various clean cultures between slave unit, multicast and/or broadcast communication, for example, it is for to being only configured for the device of subordinate, to the device that is only subordinate, send order/control information, from being only the device acquisition state information of subordinate, or it can be the communication of other types.

The generation of internal work clock

As mentioned above, once enable, slave unit starts, according to specific frequency dividing ratio, SCK is inputted to frequency division to generate internal work clock conventionally, and for example, it is for to ADC regularly, to generate the numeral sample of analog input.Internal work clock often according to and frame synchronizing signal between fixed relationship work (for example, 64*fWS), in above-described one exemplary embodiment, according to the maximum timeslot number N of every frame, SCK signal is carried out to convergent-divergent.In certain embodiments, can will (for example in the timeslot number N of every frame, build in the middle of system, N=8), thereby can adopt fixedly frequency dividing ratio (to be for example configured slave unit, for the fSCK=256*fWS that there are 8 32 digit time slots for every frame, can make frequency dividing ratio be fixed on R=256/64=4).Or slave unit can dynamically be determined frequency dividing ratio, for example, its mode is for counting (COUNT) and for example calculating frequency dividing ratio R(, R=COUNT/64 for this object lesson based on COUNT to the quantity in the SCK cycle of every frame).Conventionally will, before slave unit starts to send by SD line or receives initial data, at initial phase, complete such determining.

Figure 14 schematically shows according to the interrelated logic piece of the circuit that dynamically generates internal work clock of one exemplary embodiment of the present invention.Described logic especially comprises cycle rate counter 1402 that the quantity in the SCK cycle in frame is counted, for the first memory register 1404(literary composition of storing value COUNT, can be referred to as SCK_num register), the first frequency divider 1406(based on COUNT calculated value R is in this example, R=COUNT/64), for the second memory register 1408 of storing value R and the frequency-dividing clock generator 1410 that generates the internal work clock with frequency f DIVIDED_SCK=fSCK/R.It should be pointed out that this just generates an example of internal work clock.

Figure 15 is the flow chart for TDM operation according to one exemplary embodiment of the present invention.While receiving frame clock in piece 1502, logic enters initial phase in piece 1503, and in piece 1512 through being 32 in B(this example) after the individual SCK cycle, start to export ws signal.In piece 1503, logic is counted the quantity in the SCK cycle in frame, to determine COUNT.In piece 1504, logic determine alternatively can be in daisy chain largest device quantity (in this example, N=COUNT/32, can use it for power adjustment or other objects, as mentioned below).In piece 1506, logic generates the internal system time clock (in this example, R=COUNT/64=4, fDIVIDED_SCK=fSCK/4=64*fWS) with frequency f DIVIDED_SCK=fSCK/R.Afterwards, described logic proceeds to piece 1508, and in described, device enters normal mode of operation, for example, based on internal work clock generated data, and by assigned timeslot, on SD line, exports data in piece 1510.

Figure 16 schematically show according to one exemplary embodiment of the present invention for according to the sequential chart of the operation of the process of Figure 15.

Power adjustment based on largest device number

Each slave unit can adopt with the timeslot number N(that determines every frame for the similar technology of definite description of R above for example, N=COUNT/B), and can determine that result determines the maximum quantity of the slave unit that can be coupled to SD line by this.For example, if each slave unit can send by a time slot of each frame, the maximum quantity of slave unit will be typically N so; If each slave unit is configured to send by two time slots of each frame, the maximum quantity of slave unit will be N/2 conventionally so; Etc..

Determining of the maximum quantity of such slave unit especially can be used in the SD pin driver intensity of setting in proportion each slave unit with respect to the maximum quantity of slave unit.Generally speaking, the slave unit for transmitting on SD line connecting is more, and SD line is just longer, and load is just larger.Can adopt SD pin driver able to programme/configurable to be configured each slave unit, and can SD pin driver intensity (even if the slave unit of this quantity not being physically connected to described SD line) be set the maximum quantity based on being connected to the slave unit of described SD line.The power of battery of the slave unit that the support of such dynamic power control in especially can economy system is a small amount of.Such dynamic power control will complete in the initial phase start to send initial data on SD line at slave unit before conventionally.

Figure 17 schematically shows according to the interrelated logic piece of the circuit of dynamically setting SD pin power level of one exemplary embodiment of the present invention.Described logic especially comprises the frequency divider 1702 of COUNT value based on from register 1404 and value B calculated value N, the SD pin driver 1706 able to programme that SD pin driver intensity is set for register 1704 and the value based on N of storing value N.As mentioned above, value N can not represent to be connected to the maximum quantity of the slave unit of SD line, and can correspondingly revise the logic shown in Figure 17 (for example, if each slave unit sends by two time slots, N=COUNT/2B so).

Slave unit is synchronous and synchronous again

In some cases, be necessary or wish to make all slave units synchronous, particularly, making the internal work clock synchronous of described slave unit.For example, when slave unit is digital MEMS microphone, may need or wish that all microphones all sample to audio sync according to identical sample frequency, then in same frame, described synchronized audio sample is sent it back to controller, may need or wish the internal work clock phase mutually synchronization of slave unit, and for example, with respect to the frame clock synchronous (, thering is the identical time of delay with respect to external frame clock) that carrys out self-controller.In this way, even slave unit on the different time (, in different time slots) to controller, send synchronized audio sample data, but described synchronization audio sample also all arrives at controller in a frame, described controller can be processed described synchronized audio sample data afterwards.Any signal of the signal that such synchronization audio sample is applicable to various advanced persons in processing processed, and for example, wave beam forms, reducing noise/elimination or auditory localization, and this just slightly gives a few examples certainly.

Be below the example for the auto-initiation process of digital MEMS microphone, but usually also can be applied to the device of other types.

Figure 18 schematically show according to one exemplary embodiment of the present invention for making the microphone sequential chart in synchronous auto-initiation stage.Although adopted microphone in this example, it should be pointed out that usually can be by such auto-initiation the device for other types.For the purpose of convenient and simplification, only show the sequence of the first two microphone (being called subordinate 1 and subordinate 2) in daisy chain, but the sequence of extra microphone is also obvious.Note, the signal that adopts asterisk (*) mark is at the inner signal generating of microphone.SD_OEN signal is internal signal, and when a high position, it makes SD pin be tri-state (high impedance), and when low level, it exports data on SD pin.

As discussed above, described controller output WS and SCK, and read and/or write data by SD data wire.Ws signal is only used to indicate the beginning (in this example, on rising edge) of frame.When changing chip enable signal into a high position, the microphone in described chain is started working, and described the first microphone starts from controller, to receive ws signal by its WSI pin.

In this example, the initialization of each microphone occupies five sample frame (that is, each microphone is exported SD data since the 5th frame), and it is divided into three phases: SCK counting stage, chain alignment stage and normal TDM operational phase.Figure 19 is according to the flow chart of five frame auto-initiation methods of one exemplary embodiment of the present invention.

SCK counting stage

This one-phase comprises the first two frame.After enabling, subordinate 1 device obtains the rising edge of the ws signal of self-controller, and enters SCK counting stage (other slave units are still being waited in this).In frame 1, subordinate 1 is only counted the quantity (COUNT) in the SCK cycle in sample frame.In frame 2, carry out several operations:

1) at the rising edge place of frame 2, COUNT is stored into in register SCK_num, (for the microphone embodiment describing in literary composition, this quantity should be 64 multiple; In this concrete example, this quantity is 256);

2) the maximum quantity M(that employing is stored in the device in the COUNT computing array in SCK_num is in this example, M=COUNT/32), also calculate frequency dividing ratio (R) between SCK and Divided_SCK (wherein, Divided_SCK is internal work clock, in this example, it is fixed to fDIVIDED_SCK=fSCK/R, wherein, and R=COUNT/64; And

3) from frame 2 start the SCK cycle is counted, to generate the quantity in contained SCK cycle, input identical frame interior clock with WS, that is, described frame interior clock has the frequency identical with the frame clock that carrys out self-controller, and its also with frame clock alignment from described controller.In this one-phase, on WSO pin, will not export any pulse, and described SD pin is in high impedance status (that is, SD_OEN is in a high position).

In addition, as mentioned above, for example, owing to can estimate the quantity (, represented by the calculated value of N) of the microphone in chain at this one-phase, thereby can automatically adjust the driving intensity of SD pin according to N value.

Chain alignment stage

This one-phase also contains two frames (the third and fourth frame), exports frame interior clock (certain pulses is the pulse with a SCK cycle in this example) within this stage on WSO pin.Frame signal by this signal as next microphone in described chain, it impels next microphone to carry out SCK counting stage and chain alignment stage, and is passed to next microphone in succession together with frame interior clock, etc.In this way, all microphones in described chain are all triggered, and experience described SCK counting stage and chain alignment stage.

Should be understood that, each microphone has identical rising edge position (due to the reason of the feature of frame interior clock) and this feature will be propagated down along described daisy chain to two pulses of WSO pin output and the initial frame clock that carrys out self-controller during its corresponding chain alignment stage, thereby make all subordinate built-in functions all with the frame clock alignment that carrys out self-controller, (for example) realizes synchronization audio sample thus.

The normal TDM operational phase

Each microphone in TDM chain is after above-mentioned two stages (being SCK counting and chain alignment stage), and microphone enters normal operation phase, within this stage, during its assigned timeslot, on SD pin, is exporting data.In this one-phase, since the 5th frame (that is, the 4th frame interior clock), by adopting the ratio of SCK counting stage generation to carry out frequency division to SCK, in inside, generate divided_SCK(64*Fs) clock.Adopt this clock, MEMS microphone starts to generate the voice data of expection, and in its time slot, its data is driven on described SD data wire.In the example of the TDM daisy chain that contains eight microphones as shown in Figures 12 and 13, each time slot continues 32 SCK cycles, and in each sample frame, exports 24 voice datas in the middle of the time slot that is assigned at it of each microphone.As shown in figure 13, in this concrete example, on first SCK trailing edge after first rising edge of the pulse of microphone on WSI pin, start to export its 24 bit data, and SD pin is remained in high impedance status (Hi-Z), until it need to send data in next frame.

Meanwhile, in order to make next microphone export its SD data in next time slot (32SCK), in WSO pin place output pulse, this pulse 32SCK that has been pulse daley from receiving at WSI pin.

In this way, concrete subordinate SWI signal (i) will, always than the late 32SCK of WSI signal of subordinate (i-1), therefore will distribute the data of each slave unit, as shown in figure 12 in the situation that not overlapping in corresponding time slot.Thereby, at all slave units, all entering normal TDM after the operational phase (will use 2N+3 frame, wherein, N is the quantity of slave unit), described TDM system will enter overall operations (that is, all microphones all send data to controller).

Figure 20 schematically shows the TDM working condition according to one exemplary embodiment of the present invention, and under this situation, slave unit is sampled and sends according to synchronization mode.

Above-described one exemplary embodiment can be summarized as follows:

In first frame period for the frame synchronizing signal with respect to receiving in frame synchronization input, the quantity of the clock signal period in frame is counted;

In the second frame period for the frame synchronizing signal with respect to receiving, based on described frame synchronization input signal, generate frame interior clock in frame synchronization input;

In the 3rd frame period for the frame synchronizing signal with respect to receiving, in frame synchronization output, export frame interior clock in described frame synchronization input;

In the 4th frame period for the frame synchronizing signal with respect to receiving, in described frame synchronization output, export frame interior clock in described frame synchronization input; And

In the 5th frame period for the frame synchronizing signal with respect to receiving, enter data transfer mode in frame synchronization input, the frame synchronizing signal of delay is offered to frame synchronization output in this pattern, and generate internal work clock based on described clock signal and the counting that obtains in described the first frame period.

It should be pointed out that and may not sequentially carry out these steps in this way or according to this.For example, can in different frames, complete the counting to the quantity of the clock signal in frame, it all may be omitted in certain embodiments (for example, if COUNT be hard wire or by another kind of mode, configure).Can be on some frames execution or repeating part or all described steps.Described step may not be carried out in successive frame.Thereby in this manual, " first ", " second ", " the 3rd ", " the 4th ", " the 5th " these deictic words are intended to indicate different frames, and may not refer to the order of frame, also may not say that described frame is continuous.

Synchronous more fast

May lose undesirably every now and then slave unit synchronous, for example, due to operation or clocking error, or at controller because do not want to have stopped frame clock or serial clock from slave unit reception data in the situation that.Figure 21 schematically shows a kind of TDM working condition as an example, and in described situation, one of slave unit has lost synchronously in the middle of the operation shown in Figure 20.

Thereby, may be necessary or wish synchronous again to slave unit every now and then, can for example, after () detects synchronous forfeiture, complete again synchronous, also can be synchronous again regardless of whether losing described in synchronously all periodically completing.

Some embodiment of the present invention does not force slave unit (for example to experience whole initialize process mentioned above, by slave unit being restarted and carrying out whole initialization, this just makes slave unit synchronous a kind of mode again), but carry out synchronizing process simply again, this process makes slave unit synchronous more immediately with few hardware spending substantially.In order to realize proposed synchronous method again, each slave unit in described chain is determined its position in chain, and its positional information is stored in memory, and described operation is carried out conventionally in initialization procedure.As mentioned above, in the middle of normal TDM operation, each slave unit conventionally receives and has B(for example 32 from last device) the frame clock of individual SCK cycle delay, first slave unit in described chain is directly from controller received frame clock (WSI).On the other hand, adopt above-described synchronization mechanism, each slave unit can generate with respect to the frame interior clock that carrys out the frame clock synchronisation of self-controller (for example,, with the frame clock alignment that carrys out self-controller).Adopt this two kinds of frame clocks, be WSI input and the inner frame clock generating, and SCK, can calculate according to K=N/32+1 the position (K) of each slave unit, wherein, N be the rising edge from frame interior clock start till the frame clock receiving at WSI pin count the quantity in SCK cycle, Figure 22 has provided and has schematically shown this.

In order to make concrete slave unit synchronous again, controller is by independent communication interface (not shown), hardware " synchronous again " pin for example, or for example, for example, on () SD line, to slave unit, send synchronizing signal again by independent command interface (, I2C bus or other command interfaces that controller and slave unit are interconnected).Described in receiving again after synchronizing signal, slave unit adopts the frame synchronizing signal receive on its WSI pin as making the synchronous reference again of internal work clock, described synchronously more specifically complete to the required retardation of next synchronization internal work clock signal from described frame synchronizing signal by determining.At the mentioned above internal work clock that makes, synchronize with the WS output of controller, and the frame synchronizing signal that makes concrete slave unit K from B the SCK cycle of described internal work clock normal delay (K-1) * (for example, for device K=1, postpone 0 cycle, for device K=2, postpone 32 cycles, etc.) one exemplary embodiment in, can after the cycle, restart by B the SCK of frame clock delay (N-K+1) * receiving from WSI pin internal work clock makes the internal work clock of slave unit synchronous (from enforceable angle again, when receiving again synchronizing signal, slave unit can stop generating Divided_SCK, and start to postpone (N-K+1) * B SCK and after the cycle, generate frame interior pulse receiving described frame clock from WSI pin, according to this new frame interior pulse, again generate Divided_SCK afterwards, wherein, can make Divided_SCK and described frame interior impulsive synchronization, or can make Divided_SCK from the SCK cycle of described frame interior pulse daley predetermined quantity).In this way, adopt the frame clock of self-controller to make described slave unit synchronous again, and described slave unit start in the definite SCK quantity of SCK counting stage, to generate again its frame interior clock by metering.

Controller can for example, send independent synch command again by () to each in the not only slave unit in chain, or can be simultaneously to all common synch command again of slave unit application, to force them and to carry out synchronizeing again to framing clock of self-controller, make thus the not only slave unit in described chain synchronous again.Figure 23 schematically shows the synchronizing sequence again for described TDM daisy chain according to one exemplary embodiment of the present invention.In this exemplary scenario, because stopping generating SCK clock during frame 2 and frame 3, controller lost synchronously.Because SCK suspends, frame interior clock and Divided_SCK no longer with external frame clock synchronous, that is, the synchronous regime of all slave units has been subject to destruction, output data are unreliable.In order to make described slave unit synchronous again, controller sends synchronizing signal again to all slave units frame 4 is interior.Thereby, from frame 5, as described above, by the positional information K of storage with than the WSI input of the late time slot of last slave unit, regenerate frame interior clock, thereby make it carry out the frame clock synchronous of self-controller.Therefore, Divided_SCK again with the frame clock synchronous of controller, in this example, be to start on the rising edge of frame interior clock pulse.From frame 6, all slave units have all been got back in the middle of normal TDM operation.

Can adopt such synchronous method again to make any slave unit synchronous again, as long as it has received synchronizing signal again and the work clock for described TDM chain.This again and again synchronization mechanism only need time (frame period) and operation seldom seldom.

It should be pointed out that the information of collecting in initialization procedure, for example, be worth K, generally must not be damaged, could adopt so described synchronizing process again to carry out again synchronous.Thereby, for example, if being unexpectedly reset or becoming, slave unit is damaged, need so whole chain to restart.

Shall also be noted that the value K that each slave unit can be calculated is for other functions.

As an example, can adopted value K as the basis of unique address is provided to each slave unit, thereby (for example) for communicating between controller and slave unit.For example, address that can each slave unit is set to K or (basic address+K) or (basic address+L*K), wherein, L is integer, wherein, described basic address (BAddr0) is can predetermined basis address hard wire or be set to default value when slave unit is reset at first, and for all slave units in bus, described basic address can be identical.For example, BAddr0 can be inner hard wire address or can be any programmable address in basic address register able to programme (BAR).Can set separately basic address able to programme, also can set basic address able to programme for all slave units simultaneously.Note, before described device has independent unit address, the BAR of each slave unit will have identical value conventionally.

As another example, can adopted value K(if slave unit priori is known) in the situation that not needing above-mentioned synchronization process, generate internal work clock, its mode is exactly through (N-K+1) * B SCK, to start to generate internal work clock after the cycle simply.

Slave unit addressing

In some applications, may be necessary or wish various (or being equal to) slave unit in daisy chain is configured separately.Wanting to send to the example of the different control informations of described various devices can be signal gain, power rating and time of delay (for example,, for microphone array system).The example of common control bus is I2C bus.In order to communicate by letter with each device separately in such bus, each device needs unique unit address conventionally.Conventionally described device is designed to there is different unit addresses, or can to adopt (static) external pin be that described device is programmed into different addresses.Yet these methods generally will increase cost and the area of device and system.

Although introduced described method in literary composition under the background of TDM bus, not all strictly need in all cases this background.In other words, also can in non-TDM system, adopt introduced address distribution method.For example, conventionally need 5 address pin just can construct and there is 32(2^5) system of individual individually addressable parts.Can adopt the method for describing in literary composition to utilize and be no more than the different addresses that 3 pins are realized any amount.In thering is the TDM system of above-described type, adopt the advantage of these methods to depend on such a fact, can be by three (WSI, SCK and WSO) TDM pins that existed for this address assignment.

As discussed above, after the slave unit initialization following closely for TDM operation, and suppose described chain to be configured to allow carry out controller to subordinate (departures) communication, controller can send addressing and/or other information by slave unit described in described SD alignment so.

Or as mentioned above, each slave unit can be determined its relative position K in daisy chain automatically, for example, as above discussed with reference to figure 22-23, and can adopted value K as slave unit address or distribute slave unit address.Can in the situation that not needing controller clearly to configure slave unit, carry out such addressing.

In another alternate embodiment, can adopt frame signal (WSI/WSO) both to transmit frame start indicator (it can be pulse or special-purpose predefine synchronization header), the address of transmitting again slave unit.Figure 24 schematically show according to one exemplary embodiment of the present invention for adopting the sequential chart of frame signal configuration slave unit address.In this example, addr_assign_mode represents the state of address allocation pattern, its signal that can carry out self-controller (for example, hardware pin or other signals, for example, the order sending by I2C bus), or described addr_assign_mode can be the pattern that slave unit for example, enters when () starts or during a certain other events automatically.Typically, as described above, described address allocation pattern will be worked before TDM bus initialization and/or device initialization.And in this example, addr_done signal is the internal signal of the address assignment state of a slave unit of indication.When addr_done signal is low, it means also the address register of this slave unit not upgrade, when address register has been carried out to configuration, it is high that addr_done signal turns, and then conventionally can not to address register, write until next address allocation model again.

Configuration to slave unit address is as follows.For example, when entering address allocation pattern (, when controller generates signal), controller sends frame start signal, and subsequently succeeded by the address bit of predetermined quantity, described address bit represents the address (Addr1) of first slave unit in described chain.When receiving described frame signal on its WSI pin, slave unit receives described address bit, and is stored in its address register.For example, and described slave unit has produced the frame signal (, having postponed B SCK cycle) postponing on its WSO pin, subsequently succeeded by the address bit of predetermined quantity, described address bit represents the address (Addr2) of the second slave unit in described chain.Addr2 is generally equal to Addr1 and adds that constant (for example, Addr2=Addr1+1), but also can adopt other addressing schemes.Each slave unit carries out daisy chain to described frame/address signal similarly and goes forward one by one, thereby is that each slave unit in succession distributes unique address.When completing described address allocation pattern (for example, at the SCK of predetermined quantity after the cycle), described address allocation pattern is deactivated, and described daisy chain can be inserted in the middle of TDM initialization and/or synchronization, for example, it be take chip enable signal as indication or activates by other means.

It should be pointed out that the address information transmitting along WS line may not be complete slave unit address.For example, slave unit address by basic address part (for example can be, 3 highest significant positions) and programmable address part (for example, 4 least significant bits) 7 bit address that form, only need to partly carry out from the transmission of device auto levelizer programmable address in this case, and basic address part can be that fix and/or programmable, as discussed above.

In another alternate embodiment, not adopting WS(frame synchronization) pin is passed to next slave unit by address from a slave unit, but can during address allocation pattern, adopting SD pin (to suppose that by SD pin configuration be the I/O pin on various devices) to slave unit transfer address.Here, when entering address allocation pattern (for example, when carrying out the signal of self-controller), controller is delta frame synchronizing signal on described WS line simply, and send address in each time slot, in the situation that with the same ws signal that goes forward one by one of the daisy chain with delay that adopts in TDM operator scheme, each slave unit just can receive its corresponding address from described SD line in the time slot of its appointment.Described TDM bus design for transmitting, the data for conventional can not entered, until completed the described address arranging stage.

In another alternate embodiment, can adopt with the similar signaling schemes of last kind and coordinate the address assignment in I2C bus or other buses.Figure 25 schematically shows the daisy chain configuration of type discussed above, but it also comprises I2C bus (being SDA and SCLK line).In such embodiments, each device has independent address register (IAR) conventionally, and its content is determining described independent unit address.In order to make every part all there is unique unit address, every part must receive unique address in its IAR register, but for all slave units, described IAR has identical I2C address, thereby the ws signal that adopts daisy chain to go forward one by one by described controller activates each slave unit in succession selectively, to realize address assignment.Thereby, although all slave units all will receive all I2C address assignment orders, during described address allocation pattern, only have a slave unit to identify writing to described IAR at every turn.For the I2C bus of each address assignment do by to(for) described controller, only identify to that slave unit writing of IAR and be only the part with following characteristics:

1) it has received effective WSI input after entering described address allocation pattern; But

2) but since entering described address allocation pattern, not yet received to the writing of its IAR register, its addr_done signal is low.

At concrete slave unit, received effective IAR and write fashionablely, it enables its WSO output, and therefore the next part in described chain is set to receive IAR and upgrades.Thereby, (for example adopt one group of signal, WSI, WSO) as input and output, wherein, input (WSI) tell described part its when should check I2C bus, to obtain the renewal to its IAR, and adopt output (WSO) to tell next part in described chain to take turns to it to carry out IAR and upgraded.The IAR that like this, at every turn only has a part to identify from I2C bus upgrades.

Figure 26 schematically show according to one exemplary embodiment of the present invention for by the sequential chart of I2C bus configuration slave unit address in succession.Here, when controller starts on WS line delta frame synchronizing signal, first slave unit activating in described chain carries out by the address assignment of described I2C bus, described the first slave unit is not sent to described ws signal its WSO pin, for example, unless by the time (distributed address and/or other information from described controller by I2C bus for it, can during this address allocation pattern, carry out other configuration features, and described controller can adopt specific command to indicate the end of the configuration phase that slave unit is configured by described I2C bus).After the first slave unit having been carried out to configuration, start by described ws signal or have postpone or undelayed situation under be sent to its WSO pin, activate thus next slave unit and carry out address assignment.Similarly, each slave unit in succession all will be waited for similarly the configuration via I2C bus before ws signal being sent on its WSO pin.

Figure 27 A schematically shows the flow chart for this slave unit address allocation pattern according to one exemplary embodiment of the present invention.Particularly, during address allocation pattern (, addr_assign_mode=1), as long as slave unit has received frame pulse (addr_en transfers height at the rising edge of pulse) and its addr_done is low, this slave unit is processed the I2C order that writes its address register (and/or other configuration information).When configuration completes (for example, address register is write fashionable or at another prearranged signals, for example,, during the expression signal that represents to have configured), addr_done designator is set to a high position, to indicate, this slave unit is configured.Addr_done designator can be saved in memory, for example, for confirm later to described slave unit carried out suitable configuration (for example, if be low level making slave unit addr_done designator after addr_assign pattern exits, it represents that configuration not yet completes so, so described slave unit can generate error signal, or controller can (for example) by making each slave unit report that the state of its addr_done designator detects this situation).

Modification belongs to employing an addr_assign mode signal for each partial interior, and this signal can be established by chip power-on reset, and can after receiving effective IAR renewal, by chip, cancel this signal.

Figure 27 B schematically shows according to the state transition diagram of the slave unit address allocation pattern for the type shown in Figure 27 A of one exemplary embodiment of the present invention.From initial state, described logic transforms to " wait frame pulse " state while having enabled address allocation pattern detecting.In " wait frame pulse " state, described logic is ignored any I2C order receiving by I2C bus.When receiving frame pulse, logical conversion is to " configuration " state, under this state, described logic (is for example processed at least one the I2C order receiving by I2C bus, configuration can complete after receiving the single I2C order writing to slave unit address register, or configuration can, in a certain other events, for example, complete after the clearly indication that controller provides).When having completed configuration, logical conversion is to " end " state.If cancel address allocation pattern in logic during in " wait frame pulse " state or " configuration " state, so described logical conversion is to " end " state, and it is not in fact still in being subject to configuration status.When in " configuration " state, described logic is ignored any frame pulse receiving substantially, that is, in this example, frame pulse does not cause state transformation.

Note, in most of the cases, all registers in concrete chip are all by the impact of the individual addresses layout scheme that is subject to describing in literary composition.Yet, may exist hope can some registers of all slave units be changed into the situation of same value simultaneously.For example, such register can be for system cut-off, and can be the register for the address allocation pattern below mentioning is controlled.Therefore, may be interested in to make some public control register addresses not to be subject to the impact of individual addresses layout scheme described herein.It has avoided writing separately these public control to each device.In order to realize this purpose, a slave unit can be designed to have two unit addresses.(command device address, CAddr) always identical for all slave units, it allows master controller, and by write-once, operation changes the public control register in all devices into same value to a unit address simultaneously.Can make during fabrication another unit address (individual devices address of all slave units, IAddr) acquiescence has identical basic address (BAddr0), but can adopt the virtual bench address distribution method of describing in literary composition to be configured to make each device to have unique address described another unit address.

Serialization signal is processed

In above-described various microphone examples, each microphone sends audio sample in each frame, thereby makes described controller generally in each frame, receive a sample from each microphone.Afterwards, described controller will be processed received sample.

Or, can a plurality of slave units be configured and be operated, thereby in each frame, generate single set (for example, wave beam forming) output.Figure 28 schematically shows the daisy chain configuration for generation of set output according to one exemplary embodiment of the present invention.Here, no longer make slave unit send on SD line according to above-described TDM mode, but make SD output carry out daisy chain from a slave unit to next slave unit, go forward one by one.Thereby each slave unit has SD input pin (SDI) and SD output pin (SDO).So, each slave unit can make the data that the former receives from it (for example be combined with the data of himself, generated data and) or the data that receive from last device are carried out to other processing, and it is combined with the treated data of self, and single (for example, merging) output is sent to its SD output.Adopt the WS daisy chain of above-described type to go forward one by one and simultaneous techniques, can make microphone embodiment carry out isochronous audio sampling, and according to TDM mode, transmit SD output along SD daisy chain, with form Controller-oriented merging (for example, wave beam forming) output, wherein, the SDO pin by last slave unit in daisy chain offers described controller by described merging output.Although be only coupled to alternatively for the SDI pin of the device of subordinate is shown the two-way communication that the SDO pin of described controller is below discussed by first in Figure 28, but when not expecting such two-way communication, generally will not use described first to be only the SDI pin of the device of subordinate, can it not connected (floating) or can as required it be connected for specific implementation in this case, for example, be connected to a high position, be connected to low level, ground connection etc.

In addition, can be by the optional SDO pin of controller being coupled to described first only for the SDI pin of the device of subordinate completes between described controller and slave unit, or even the two-way communication between different slave units, formed thus annular confirmation, it allows controller (for example to send information to slave unit, order and/or data), from slave unit, receive data, even from a slave unit to another slave unit, transmit data (for example, from downstream slave unit upstream slave unit).In addition, at the slave unit embodiment relevant to individual addresses (for example, as discussed above), can adopt individual devices address to controller to subordinate and/or be slave to subordinate communication and carry out clean culture, or can be by described communication multicast/broadcast to all devices or a plurality of device.Thereby for example, described controller can for example, to all slave unit broadcasting commands or data (, reset command), or can send order or data (for example, providing configuration information, requesting state information etc.) to individual slave unit.So slave unit can for example, process according to the plan destination of the source of the type of () data, data or data the data that are received from upstream device selectively.For example, be only that the device of subordinate can be carried out the processing of serialization signal to some data, make other data pass through simultaneously, allow thus to transmit dissimilar data in bus.

Miscellaneous

Although it should be pointed out that above and described some example with reference to thering is the slot time in 32 SCK cycles, the invention is not restricted to have the slot time in 32 SCK cycles, be also not limited to any concrete slot time.For example, embodiment can be configured to there is lower resolution on (for example, 8 clocks of every time slot or 16 clocks) or there is higher resolution (for example, 64 clocks of every time slot), and each clock signal of convergent-divergent (for example, WS, internal work clock) correspondingly.

It should be pointed out that and adopted for convenience's sake title above, in no case should be regarded as is limitation of the present invention.

Can embody various aspects of the present invention by various form, it for example, comprises the measure of their any combination including but not limited to the computer program for example, using together with processor (, microprocessor, microcontroller, digital signal processor or all-purpose computer), the FPGA (Field Programmable Gate Array) of using together with programmable logic device (field programmable gate array (FPGA) or other PLD), discrete parts, integrated circuit (application-specific integrated circuit (ASIC) (ASIC)) or other.Conventionally the part or all of computer program of realizing described function is embodied as to one group of computer program instructions, described instruction is converted into the executable form of computer, be stored in computer-readable medium like this, and by microprocessor, moved under the control of operating system.Can adopt the FPGA of one or more suitable configurations to realize for implementing the part or all of hardware based logic of described function.

Can be used for implementing first the part or all of computer program logic of the function of description above by embodied in various forms, described form can execute form and various intermediate form (form for example, being generated by assembler, compiler, linker or locator) including but not limited to source code form, computer.Source code by various programming languages (for example can comprise, object code, assembler language, high-level language, for example, Fortran, C, C++, JAVA or HTML) in the computer program instructions for using together with various operating system or operating environment of any realization.Described source code can define and use various data structures and communication information.Described source code can have the executable form of computer (for example, passing through interpreter), or source code can be changed to (for example,, by decoder, assembler or compiler) be the executable form of computer.

Can be by computer program according to any form (for example, source code form, computer can execute form or intermediate forms) permanently or be temporarily fixed in tangible storage medium, for example, semiconductor storage (for example, RAM, ROM, PROM, EEPROM or flash RAM able to programme), magnetic memory apparatus (for example, floppy disk or hard disk), optical storage (for example, CD-ROM), PC card (for example, pcmcia card) or other storage devices.Computer program can be fixed to any technology that can adopt in the various communication technologys according to any form is sent in the middle of the signal of computer, the described communication technology for example, including but not limited to analogue technique, digital technology, optical technology, wireless technology (, bluetooth), Network Connection and Internet technology.Can described computer program (for example be distributed together along with having the removable storage medium of document that print or electronics according to any form, shrink-wrapped software), can adopt computer system (for example to carry out prestrain to described computer program, be pre-loaded on system ROM or fixed disk), or can pass through communication system (for example, Internet or World Wide Web) distributes described computer program from server or BBS (Bulletin Board System).

Can adopt traditional manual method to be designed for and realize first the part or all of hardware logic (comprising the FPGA (Field Programmable Gate Array) for using together with programmable logic device) of the middle function of describing above, or can adopt various tool, for example, computer-aided design (CAD), hardware description language are (for example, VHDL or AHDL) or PLD programming language (for example, PALASM, ABEL or CUPL) with the mode of electronics to described hardware logic design, capture, simulation or document process (documented).

Can FPGA (Field Programmable Gate Array) permanently or be temporarily fixed in tangible storage medium, for example, semiconductor storage (for example, RAM, ROM, PROM, EEPROM or flash RAM able to programme), magnetic memory apparatus (for example, floppy disk or fixed disk), optical storage (for example, CD-ROM) or other storage devices.Described FPGA (Field Programmable Gate Array) can be fixed to any technology that can adopt in the various communication technologys is sent in the middle of the signal of computer, the described communication technology for example, including but not limited to analogue technique, digital technology, optical technology, wireless technology (, bluetooth), Network Connection and Internet technology.Can be by described FPGA (Field Programmable Gate Array) for example, along with (distributing together with the removable storage medium of document that print or electronics, shrink-wrapped software), can adopt computer system (for example to carry out prestrain to described FPGA (Field Programmable Gate Array), be pre-loaded on system ROM or fixed disk), or can pass through communication system (for example, Internet or World Wide Web) distributes described FPGA (Field Programmable Gate Array) from server or BBS (Bulletin Board System).Certainly, some embodiments of the present invention can be embodied as to the combination of software (for example computer program) and hardware.Other embodiment of the present invention can be embodied as hardware completely or be embodied as software completely.

Can characterize by the possible claim of enumerating in this section paragraph below various embodiment of the present invention (basic right that being in the application's end provides require before).These possible claims have formed the part of the application's written description.Therefore, relating to the application or relating to any the application of usining and can preferably adopt the content of following possible claim as actual claim in the middle of basis requires the legal procedure of application of priority afterwards.

The possible theme (above titled with letter " P ", to avoid require to obscure with the basic right below proposing) that can advocate protection includes but not limited to:

Synchronously

P1. a system for time division multiplex communication, it comprises:

Data wire;

Controller, comprise clock output for clock signal is provided, for provide the some frames in succession of indication each the frame synchronization output of frame synchronizing signal of beginning and the data pin that is coupled to described data wire; And

What at least one was communicated by letter with described controller is only the device of subordinate, each is only for the device of subordinate comprises: clock input, be coupled to the clock output of described controller for receiving described clock signal, be coupled to the data pin of described data wire, frame synchronization input and frame synchronization output, described controller and described at least one only for the device of subordinate is according to take the chain type structure interconnection that described controller is starting point, wherein, the frame synchronization input that is only the device of subordinate by each is coupled to the frame synchronization output of the last device in described chain, and wherein, described controller provides described frame synchronizing signal in its frame synchronization output, wherein, each is only for the device of subordinate is configured to carry out the auto-initiation process that comprises following content:

For frame synchronizing signal is monitored described frame synchronization input; And

When receive at least two frame synchronizing signals in described frame synchronization input after:

Based on a plurality of frame synchronizing signals that receive, generate frame interior clock, described frame interior clock and the frame synchronizing signal providing in described controller frame synchronization output are synchronous;

In described frame synchronization output, export described frame interior clock; And

Enter data transfer mode, comprise based on described frame interior clock and generate internal work clock.

P2. according to the system described in claim P1, wherein, generation frame interior clock comprises based on described clock signal and described a plurality of frame synchronizing signal determines the clock signal period quantity in frame, and wherein, described generation internal work clock comprises that the quantity of the clock signal period based in frame interior clock and frame generates internal work clock.

P3. according to the system described in claim P1, wherein, described at least one for the device of subordinate comprises a plurality of, be only only the device of subordinate, and wherein, by all time slots that are only configured to access the equal number of every frame for the device of subordinate.

P4. according to the system described in claim P1, wherein, described at least one for the device of subordinate comprises a plurality of, be only only the device of subordinate, and wherein, by least two time slots that are only configured to access the varying number of every frame for the device of subordinate.

P5. according to the system described in claim P1, wherein, described at least one for the device of subordinate comprises a plurality of, be only only the device of subordinate, and wherein, all is all only the device of same type for the device of subordinate.

P6. according to the system described in claim P1, wherein, described at least one for the device of subordinate comprises a plurality of, be only only the device of subordinate, and wherein, at least two only for the device of subordinate is dissimilar device.

P7. according to the system described in claim P1, wherein, what each was only configured to determine based on described clock signal and frame synchronizing signal that described controller supports for the device of subordinate is only the maximum quantity of the device of subordinate.

P8. according to the system described in claim P7, wherein, each is only for the data pin of the device of subordinate comprises programmable driver, and wherein, by each only for the device of subordinate be configured to based on described controller support only for the maximum quantity of the device of subordinate is programmed to the power setting of described programmable driver.

P9. according to the system described in claim P1, wherein, by each only for the data pin of the device of subordinate be configured to or can be configured as carry out following operation at least one of them:

By described data wire, send data; Or

From described data wire, receive data.

P10. according to the system described in claim P1, wherein, described at least one only for the device of subordinate comprises at least one digital MEMS microphone arrangement.

P11. one kind comprises that at least one is only the equipment of the device of subordinate for what work at tdm communication system, described time-division multiplex system has and described at least one controller of only communicating by letter for the device of subordinate, and each is only for the device of subordinate comprises:

Clock input for receive clock signal;

Frame synchronization input, for receiving each the frame synchronizing signal of beginning of the some successive frames of indication;

Be used for the frame synchronization output of the frame synchronizing signal of output delay; And

Be only the TDM bus interface of subordinate, be coupled to described clock input, frame synchronization input and frame synchronization output and comprise that, for being coupled to the data pin of data wire, wherein, described TDM bus interface is configured to carry out auto-initiation process, this process comprises:

For frame synchronizing signal is monitored described frame synchronization input; And

When receive at least two frame synchronizing signals in described frame synchronization input after:

Based on a plurality of frame synchronizing signals that receive, generate frame interior clock, described frame interior clock and the frame synchronizing signal providing in described controller frame synchronization output are synchronous;

In described frame synchronization output, export frame interior clock; And

Enter data transfer mode, comprise based on described frame interior clock and generate internal work clock.

P12. according to the equipment described in claim P11, wherein, described TDM bus interface is configured to determine based on described clock signal and described a plurality of frame synchronizing signal to the quantity of the clock signal period in frame, and the quantity that wherein, also described TDM bus interface is configured to the clock signal period based in described frame interior clock and frame generates internal work clock.

P13. according to the equipment described in claim P12, wherein, also described TDM bus interface is configured to determine that based on described clock signal and the frame synchronizing signal that receives what can in chain, support is only the maximum quantity of the device of subordinate in the input of described frame synchronization.

P14. according to the equipment described in claim P13, wherein, described data pin comprises programmable driver, and wherein, the maximum quantity also described TDM bus interface being configured to based on being only the device of subordinate is programmed to the power setting of described programmable driver.

P15. according to the equipment described in claim P11, wherein, described data pin is configured to or can be configured as carry out following operation at least one of them:

By described data wire, send data; Or

From described data wire, receive data.

P16. according to the equipment described in claim P11, also comprise described in being coupled to being only the digital MEMS microphone of the TDM bus interface of subordinate.

P17. according to the equipment described in claim P11, wherein, described at least one for the device of subordinate comprises a plurality of, be only only the device of subordinate, and wherein, by described a plurality of only for the device of subordinate is integrated on one single chip.

P18. according to the equipment described in claim P17, also comprise with described and a plurality ofly only together with the device of subordinate, be integrated into the controller on one single chip.

P19. one kind for only carrying out the method for auto-initiation to tdm communication system for the device of subordinate, described system has and at least one controller of only communicating by letter for the device of subordinate, wherein, in successive frames, send data, each frame comprises the time slot of predetermined quantity, and described method comprises:

For frame synchronizing signal, by only for the TDM interface monitor of the device of subordinate is only for the frame synchronization of the device of subordinate is inputted; And

When receive at least two frame synchronizing signals in described frame synchronization input after:

Described in generating based on a plurality of frame synchronizing signals that receive, be only the frame interior clock of the device of subordinate, described frame interior clock is synchronizeed with the frame synchronizing signal of described controller output;

Described, only in the frame synchronization output for the device of subordinate, export frame interior clock; And

Enter data transfer mode, only comprise described in generating based on described frame interior clock the internal work clock for the device of subordinate.

P20. according to the method described in claim P19, wherein, generate internal work clock and comprise:

Clock input by described slave unit receives the clock signal from described controller;

Based on clock signal and described a plurality of frame synchronizing signal, determine the quantity of the clock signal period in frame; And

The quantity of the clock signal period based in described frame interior clock and frame generates internal work clock.

P21. according to the method described in claim P20, also comprise:

Based on described clock signal and frame synchronizing signal, determine to be only the maximum quantity of the device of subordinate.

P22. according to the method described in claim P21, wherein, described only for the device of subordinate comprises the programmable driver for data output, and wherein, described method also comprises:

Maximum quantity based on being only the device of subordinate is programmed to described programmable driver.

P23. according to the method described in claim P20, wherein, described only for the device of subordinate comprises analog to digital converter or digital to analog converter, and wherein, described method also comprises:

Described frame interior clock is offered to described transducer.

P24. according to the method described in claim P23, wherein, described transducer is the microphone of generating digital audio sample.

P25. be used in the daisy chain device in position K to generate the method for internal work clock, described daisy chain is worked in every frame has the TDM communication system of N time slot, and described method comprises:

Receive serial clock signal;

Received frame clock signal; And

After the cycle of the predetermined quantity of described serial clock signal, generate internal work clock, wherein, it is basis that described predetermined quantity be take K and N.

P26. according to the method described in claim P25, wherein, described predetermined quantity equals (N-K+1) * B, and wherein, B is predetermined constant.

P27. according to the method described in claim P25, also comprise:

The quantity in the cycle of the serial clock signal by counting between frame clock signal and determined value N dynamically.

P28. according to the method described in claim P25, wherein, take following proposal at least one of them:

Value K is hardwired in described device;

Value K is programmed in described device; Or

By described device determined value K dynamically.

Synchronous again

P29. for to the internal work clock of the device in position K in a daisy chain synchronous method again, described daisy chain is worked for have the TDM communication system of N time slot at every frame, and described method comprises:

Receive serial clock signal;

Received frame clock signal;

Generate the internal work clock signal of synchronizeing with external reference clock signal;

Poor determined value K based between described internal work clock signal and described frame clock signal;

Receive synchronizing signal again; And

After the cycle of the predetermined quantity of described serial clock signal, generate described internal work clock, wherein, it is basis that described predetermined quantity be take K and N.

P30. according to the method described in claim P29, wherein, described predetermined quantity equals (N-K+1) * B, and wherein, B is predetermined constant.

P31. according to the method described in claim P29, wherein, by the amount of cycles of the serial clock signal between frame clock signal, count and dynamically determine N.

Address arranging based on relative position

A method of P32. automatically distributing address for the device connecting to daisy chain, described method comprises by each device:

Difference based between two clock signals is determined the relative position of this device in described daisy chain automatically; And

Based on described relative position distributor address.

P33. according to the method described in claim P32, wherein, the difference based between two clock signals determines that the relative position of this device in described daisy chain comprises automatically:

Generate first clock signal of synchronizeing with reference clock signal;

Receive second clock signal;

Determine the retardation between described second clock signal and described the first clock signal; And

Based on described retardation, determine described relative position.

P34. according to the method described in claim P33, wherein, determine that the retardation between described second clock signal and described the first clock signal comprises:

Receive the 3rd clock signal;

Measure the periodicity (N) of the 3rd clock signal between described the first clock signal and second clock signal.

P35. according to the method described in claim P34, wherein, amount of cycles (N) is the multiple of predetermined constant (B), and wherein, relative position K=N/B+1.

P36. the method at the relative position of daisy chain for automatic determination apparatus, described method comprises:

Generate first clock signal of synchronizeing with reference clock signal;

Receive second clock signal;

Determine the retardation between described second clock signal and described the first clock signal; And

Based on described retardation, determine described relative position.

P37. according to the method described in claim P36, wherein, determine that the retardation between described second clock signal and described the first clock signal comprises:

Receive the 3rd clock signal;

Count the periodicity (N) of the 3rd clock signal between described the first clock signal and second clock signal.

P38. according to the method described in claim P37, wherein, amount of cycles (N) is the multiple of predetermined constant (B), and wherein, relative position K=N/B+1.

Address arranging based on other factors

P39. for the slave unit to daisy chain, distribute a method for address, described method comprises:

Controller sends frame start signal, sends afterwards address value, and this address value can be used for by the first slave unit in daisy chain distributing address into himself; And

Each in daisy chain slave unit in succession receives the frame start signal of following address value below, and based on described address value, store the addresses in the memory of described slave unit, the frame start signal generate postponing, following after this frame start signal be different from address value that described slave unit receives, for the address value of next slave unit of daisy chain.

P40. according to the method described in claim P39, wherein, described next address value equals received address value and adds predetermined constant.

P41. according to the method described in claim P39, wherein, described address value is the part address of described slave unit.

P42. for the slave unit to daisy chain, distribute a method for address, described method comprises:

Controller is delta frame synchronizing signal on frame synchronization pin, and in each in a plurality of time slots in succession, sends unique address value on data wire; And

Each in daisy chain slave unit received frame synchronizing signal in succession, the corresponding time slot from data wire is read address value, and the frame synchronizing signal of delay is sent to next slave unit in succession in daisy chain.

P43. one kind in daisy-chain communication system for to the method for specifying slave unit to be configured, described daisy-chain communication system has the controller of communicating by letter with at least one slave unit, in described system, each slave unit is configured to receive in frame synchronization input from the frame synchronizing signal of the last device in daisy chain and provides frame synchronizing signal in frame synchronization output, wherein said slave unit is communicated by letter with controller by bus, and described method comprises by described appointment slave unit:

While receiving frame synchronizing signal in described frame synchronization input, judge whether to have carried out configuration, if do not had, enter so configuration mode, under this pattern, by described appointment slave unit, carry out at least one order receiving by described bus, when the configuration of the described appointment slave unit of judgement completes, stop described configuration mode, and provide frame synchronizing signal in described frame synchronization output, wherein, described appointment slave unit is ignored before described configuration mode and the order receiving by described bus subsequently, until all slave units have all completed configuration.

Serialization signal is processed

P44. a system for time division multiplex communication, comprising:

Controller, comprises clock output for clock signal is provided, for each frame synchronization output and the data input of frame synchronizing signal of beginning of the some frames in succession of indication is provided; And

What a plurality of and described controller was communicated by letter is only the device of subordinate, each is only coupled to the clock output of described controller for the clock input of receive clock signal for the device of subordinate comprises, data input, data output, frame synchronization input and frame synchronization output, described controller and described at least one only for the device of subordinate is according to take the chain structure interconnection that described controller is starting point, the frame synchronization input that wherein (1) is only the device of subordinate by each is coupled to the frame synchronization output of the last device in described chain, and (2) last is only coupled to the data input of described controller for the data output of the device of subordinate, by each all the other are only only the data input of the device of subordinate for the data output of the device of subordinate is coupled to ensuing in described chain, wherein, described controller provides frame synchronizing signal in described frame synchronization output, and in data transfer mode, each only for the device of subordinate by frame synchronization export in described chain next in succession the frame synchronizing signal of delay is only provided for the device of subordinate, each is only for the device of subordinate sends data in the time slot at predetermined quantity based on input the frame synchronizing signal receiving in frame synchronization in its data output, wherein, described at least one data that only send in data output for the device of subordinate be included in the data that receive in data input and described be only the combination of the inner data that generate of device of subordinate.

P45. according to the system described in claim P44, wherein, by each, only for the device of subordinate is configured to carry out auto-initiation process, this process comprises:

By receiving in frame synchronization input in the first stage that prearranged signals triggers, the quantity of the clock signal period in every frame is counted, and the frame interior clock aimed at described frame synchronizing signal of generation;

In second stage, in described frame synchronization output, export frame interior clock; And

Within the phase III, in data transfer mode, work.

P46. according to the system described in claim P45, wherein, one of them is only for the device of subordinate comprises the analog to digital converter being configured to based on frame interior clock work.

P47. according to the system described in claim P46, wherein, described analog to digital converter is the microphone of generating digital audio sample.

P48. according to the system described in claim P44, wherein, by described a plurality of only for the device of subordinate is integrated on one single chip.

P49. according to the system described in claim P48, wherein, described controller is a plurality ofly only integrated on one single chip with described together with the device of subordinate.

Miscellaneous claim

P50. any in said system, apparatus and method, wherein, the information sending on data wire can comprise in unidirectional or two-way order/control information together with data (for example,, from modulus or digital to analog converter).

P51. the system, the apparatus and method that comprise described synchronously, the more any feasible combination that synchronous, address assignment and/or serialized data are processed.

In the situation that not deviating from actual range of the present invention, can embody the present invention by other concrete forms.One exemplary embodiment of the present invention is all intended to mention in the place of any mentioning " the present invention ", should not be regarded as and refer to all embodiment of the present invention, unless context requirement separately.No matter, from which aspect, all should regard described embodiment as illustrative and nonrestrictive.

Claims (19)

1. a system for time division multiplex communication, comprising:

Data wire;

Controller, comprise clock output for clock signal is provided, for provide the some frames in succession of indication each the frame synchronization output of frame synchronizing signal of beginning and the data pin that is coupled to described data wire; And

What at least one was communicated by letter with described controller is only the device of subordinate, each is only for the device of subordinate comprises: clock input, be coupled to the clock output of described controller for receiving described clock signal, data pin, be coupled to described data wire, frame synchronization input and frame synchronization output, described controller and described at least one only for the device of subordinate is according to take the chain type structure interconnection that described controller is starting point, wherein, the frame synchronization input that is only the device of subordinate by each is coupled to the frame synchronization output of the last device in described chain, and wherein, described controller provides described frame synchronizing signal in its frame synchronization output, and during data transfer mode, each is only for the device of subordinate provides from the frame synchronizing signal of its frame synchronization input delay to its frame synchronization output, and by its data pin, access described data wire in the predetermined time slot group of each frame, for to described controller, send data and from described controller receiving data at least one of them, described predetermined time slot group is that only for the device of subordinate, the frame synchronizing signal based on receiving in its frame synchronization input and the clock signal that receives in its clock input are selected separately by described.

2. system according to claim 1, wherein, described at least one only for the device of subordinate comprises that a plurality of is only the device of subordinate.

3. system according to claim 2, wherein, by all time slots that are only configured to access the equal number of each frame for the device of subordinate.

4. system according to claim 2, wherein, by least two time slots that are only configured to access the varying number of each frame for the device of subordinate.

5. system according to claim 2, wherein, all is all only the device of same type for the device of subordinate.

6. system according to claim 2, wherein, at least two only for the device of subordinate is dissimilar device.

7. system according to claim 2, wherein, by described a plurality of only for the device of subordinate is integrated on one single chip.

8. system according to claim 7, wherein, makes described controller a plurality ofly only together with the device of subordinate, be integrated on one single chip with described.

9. system according to claim 1, wherein, what each was only configured to determine based on described clock signal and frame synchronizing signal that described controller supports for the device of subordinate is only the maximum quantity of the device of subordinate.

10. system according to claim 9, wherein, each is only for the data pin of the device of subordinate comprises programmable driver, and wherein, by each only for the device of subordinate be configured to based on described controller support only for the maximum quantity of the device of subordinate is programmed to the power setting of described programmable driver.

11. systems according to claim 1, wherein, the data pin that is only the device of subordinate by each is disposed for sending to described controller by described data wire the output of data.

12. systems according to claim 1, wherein, the data pin that is only the device of subordinate by each is configured to the input from described controller receiving data by described data wire.

13. systems according to claim 1, wherein, described at least one only for the device of subordinate comprises at least one digital MEMS microphone arrangement.

14. 1 kinds of devices for working at system for time division multiplex communication, described device comprises:

Clock input for receive clock signal;

For receiving each the frame synchronization input of frame synchronizing signal of beginning of the some successive frames of indication;

Be used for the frame synchronization output of the frame synchronizing signal of output delay; And

It is only the TDM bus interface of subordinate, be coupled to described clock input, frame synchronization input and frame synchronization are exported and comprise for being coupled to the data pin of data wire, wherein, described TDM bus interface is configured to during data transfer mode, the frame synchronizing signal from described frame synchronization input delay be provided to described frame synchronization output, and by described data pin, access described data wire in the predetermined time slot group of each frame, for on described data wire, send data and from described data wire receive data at least one of them, described predetermined time slot group is that only for the TDM bus interface of subordinate, the frame synchronizing signal based on receiving in described frame synchronization input and the clock signal that receives in described clock input are selected separately by described.

15. devices according to claim 14, wherein, are also configured to described TDM bus interface frame synchronizing signal based on receiving in the input of described frame synchronization and clock signal and determine that what can in chain, support is only the maximum quantity of the device of subordinate.

16. devices according to claim 15, wherein, described data pin comprises programmable driver, and wherein, also described TDM bus interface is configured to based on described only for the maximum quantity of the device of subordinate is programmed to the power setting of described programmable driver.

17. devices according to claim 14, wherein, are disposed for described data pin data are sent to the output on described data wire.

18. devices according to claim 14, wherein, are disposed for receiving the input from the data of described data wire by described data pin.

19. devices according to claim 14, also comprise described in being coupled to being only the digital MEMS microphone of the TDM bus interface of subordinate.

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