CN114360598A - Duty cycle training circuit, duty cycle adjusting method and memory controller - Google Patents
Duty cycle training circuit, duty cycle adjusting method and memory controller Download PDFInfo
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- CN114360598A CN114360598A CN202111623743.0A CN202111623743A CN114360598A CN 114360598 A CN114360598 A CN 114360598A CN 202111623743 A CN202111623743 A CN 202111623743A CN 114360598 A CN114360598 A CN 114360598A
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Abstract
The embodiment of the disclosure provides a duty ratio training circuit, a duty ratio adjusting method and a memory controller. The duty cycle training circuit includes a duty cycle measurement unit configured to obtain a measurement of a duty cycle of a memory; a training engine configured to generate a duty cycle adjustment command to instruct the memory to adjust the duty cycle according to the measurement result sent by the duty cycle measurement unit. The duty ratio training circuit realizes accurate adjustment of the duty ratio of the data strobe signal of the memory by monitoring the duty ratio measurement data, so that the duty ratio of the data strobe signal is in an optimal state, and the performance and the stability of high-speed access of the memory are optimized.
Description
Technical Field
The embodiment of the disclosure relates to a duty ratio training circuit, a duty ratio adjusting method and a memory controller.
Background
Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is a main Memory of a computer system, and has been developed to the 5 th generation, namely DDR5SDRAM through years of development. Compared with the prior generation, the DDR5SDRAM supports lower IO voltage, has higher processing speed and larger capacity, and can meet the requirements of the cloud computing and high-performance servers which are increasingly developed at present on a system memory with low power consumption, high speed and large capacity. However, as the transmission speed increases and the interface voltage decreases, greater challenges are presented to the integrity of SDRAM signal transmissions.
DDR5 provides some new features over DDR4 that support correction of the data strobe duty cycle for read commands. After the memory controller sends a read command to the SDRAM, the SDRAM returns read data and a data declaration signal to the memory controller after a Column Access Latency (CL) time. The memory controller samples the read data based on the received data strobe signal. Under poor signal integrity conditions, the duty cycles of the read strobe and read data may shift, no longer being at the ideal 50%. This can have a significant impact on the sampling of the memory controller. The concept of Duty Cycle Adjuster (DCA) is cited in the DDR5SDRAM specification promulgated by the Joint Electron Device Engineering Council, JEDEC organization.
Disclosure of Invention
At least one embodiment of the present disclosure provides a duty cycle training circuit, including a duty cycle measurement unit configured to obtain a measurement of a duty cycle of a memory; the training engine is configured to generate a duty cycle adjustment command to instruct the memory to adjust the duty cycle according to the measurement result sent by the duty cycle measurement unit.
For example, an embodiment of the present disclosure provides a duty cycle training circuit further including: a command generator configured to generate a memory command for altering a value of a mode register within the memory in accordance with a duty cycle adjustment command sent by the training engine.
For example, in the duty cycle training circuit provided in an embodiment of the present disclosure, the command generator is further configured to select a command to be transmitted to the memory from a preset plurality of memory commands according to the duty cycle adjustment command.
For example, in the duty cycle training circuit provided in an embodiment of the present disclosure, the duty cycle measuring unit is further configured to measure the duty cycle of the memory according to the received data strobe signal to obtain the measurement result.
For example, in a duty cycle training circuit provided in an embodiment of the present disclosure, the data strobe signal is a differential signal, the duty cycle measuring unit includes a comparator configured to compare the data strobe signal to obtain a measurement result, and output the measurement result to the training engine, where the measurement result includes a high level and a low level, the high level indicates that the duty cycle value is greater than 50%, and the low level indicates that the duty cycle value is less than 50%.
For example, in a duty cycle training circuit provided in an embodiment of the present disclosure, the training engine is configured to: responding to the initialization of a memory or the change of the working environment of the memory, and entering a duty ratio adjusting mode; and sending a read command to the memory to enable the memory to send a data strobe signal to the duty cycle measuring unit.
For example, in a duty cycle training circuit provided in an embodiment of the present disclosure, the training engine is configured to: generating a duty cycle adjustment command instructing to decrease the duty cycle when the measurement result indicates that the duty cycle value is greater than 50%; when the measurement indicates that the duty cycle value is less than 50%, a duty cycle adjustment command is generated that indicates an increase in the duty cycle.
For example, in a duty cycle training circuit provided by an embodiment of the present disclosure, the command generator is configured to find an optimal duty cycle of the data strobe signal using a binary method, or in an increasing or decreasing manner, and generate the memory command.
For example, in a duty cycle training circuit provided by an embodiment of the present disclosure, the training engine is configured to determine that the duty cycle is in the optimal state and stop adjusting the duty cycle when receiving the measurement result indicating that the duty cycle value is continuously changed between more than and less than 50% within a preset time period.
For example, an embodiment of the present disclosure provides that the duty cycle training circuit further comprises a software access interface configured to provide external software with functionality to access the duty cycle training circuit.
At least one embodiment of the present disclosure provides a duty cycle adjusting method, including: obtaining a measurement result of the duty ratio of the memory; and generating a duty ratio adjusting command to instruct the storage to adjust the duty ratio according to the measuring result sent by the duty ratio measuring unit.
For example, an embodiment of the present disclosure provides a method further including: a memory command is generated for altering a value of a mode register within the memory in accordance with the duty cycle adjustment command.
For example, an embodiment of the present disclosure provides a method further including: a command to be transmitted to the memory is selected from a preset plurality of memory commands according to the duty ratio adjustment command.
For example, in a method provided by an embodiment of the present disclosure, obtaining a measurement of a duty cycle of a read data strobe signal of a memory includes: and measuring the duty ratio of the read data strobe signal of the memory according to the received data strobe signal to obtain a measurement result.
For example, in a method provided by an embodiment of the present disclosure, measuring a duty cycle of a data strobe signal of a memory according to a received data strobe signal to obtain a measurement result includes: the data strobe signals are compared to obtain a measurement comprising a high level indicating that the duty cycle value is greater than 50% and a low level indicating that the duty cycle value is less than 50%.
For example, an embodiment of the present disclosure provides a method further including: responding to the initialization of a memory or the change of the working environment of the memory, and entering a duty ratio adjusting mode; a read command is sent to the memory to cause the memory to output a data strobe signal.
For example, in a method provided by an embodiment of the present disclosure, generating a duty ratio adjustment command according to a measurement result sent by a duty ratio measurement unit includes: generating a duty cycle adjustment command instructing to decrease the duty cycle when the measurement result indicates that the duty cycle value is greater than 50%; when the measurement indicates that the duty cycle value is less than 50%, a duty cycle adjustment command is generated that indicates an increase in the duty cycle.
For example, in a method provided by an embodiment of the present disclosure, generating a memory command for changing a value of a mode register within a memory according to a duty cycle adjustment command includes: the memory command is generated using a binary method, or in an incremental or decremental manner.
For example, an embodiment of the present disclosure provides a method further including: and when the measurement result is received within the preset time period and represents that the duty ratio value is continuously changed between more than and less than 50%, determining that the duty ratio is in the optimal state, and stopping adjusting the duty ratio.
For example, an embodiment of the present disclosure provides a method further including: and sending the measurement result to external software or receiving a duty ratio adjusting command of the external software.
At least one embodiment of the present disclosure provides a memory controller including a duty cycle training circuit as in any one of the above embodiments.
At least one embodiment of the present disclosure provides a duty cycle training circuit, a duty cycle adjusting method, and a memory controller, which implement accurate adjustment of a duty cycle of a data strobe signal of a memory by monitoring duty cycle measurement data, so that the duty cycle of the data strobe signal is in an optimal state, thereby optimizing performance of the memory and stability of high-speed access.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it should be apparent that the drawings described below only relate to some embodiments of the present disclosure and are not limiting on the present disclosure.
Fig. 1A and 1B are schematic diagrams of a duty cycle training circuit provided in at least one embodiment of the present disclosure;
fig. 2 is a schematic diagram of a duty cycle measuring unit according to at least one embodiment of the present disclosure;
fig. 3 is a schematic diagram of a memory according to at least one embodiment of the disclosure;
fig. 4 is a flowchart of a duty cycle training method according to at least one embodiment of the present disclosure;
fig. 5 is a schematic diagram of a memory controller according to at least one embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The duty cycle adjustment of current Dynamic Random Access Memory (DRAM) read Data is usually put into a training step of the DDR5, such as a read Data training, and an eye pattern obtained by the read Data training is used to determine whether the duty cycle of a current Data Strobe Signal (DQS) is optimal. Factors affecting the size of the eye pattern for reading data training are many, such as the phase of the sampling clock, the reference voltage, the signal noise, and the like, so that the eye pattern cannot truly reflect the condition of the DQS duty cycle, and further cannot obtain accurate data of the DQS duty cycle.
As the DDR protocol evolved to the fifth generation, DDR5SDRAM, the maximum rate of DDR has risen to 6400 mbps, and the duty cycle problem of the read data strobe signal has more and more significant impact on the correct sampling of data. JEDEC defines a set of Mode Registers (MRs) in the DDR5SDRAM specification to regulate the read data strobe signal and the duty cycle of the read data signal. However, in the specification, only one Training Assist Mode (Training Assist Mode) of DCA is defined on the MR 42, and no Training scheme or method of DCA is specified.
At least one embodiment of the present disclosure provides a duty cycle training circuit including a duty cycle measurement unit and a training engine. Wherein the duty cycle measurement unit is configured to obtain a measurement of a duty cycle of a data strobe signal of the memory. The training engine is configured to generate a duty cycle adjustment command to instruct the memory to adjust the duty cycle according to the measurement result sent by the duty cycle measurement unit.
At least one embodiment of the present disclosure provides a duty cycle adjusting method. The method includes obtaining a measurement of a duty cycle of a memory. And generating a duty ratio adjusting command to instruct the memory to adjust the duty ratio according to the measuring result sent by the duty ratio measuring unit.
At least one embodiment of the present disclosure provides a duty cycle training circuit, a duty cycle adjusting method, and a memory controller, which implement accurate adjustment of a duty cycle of a data strobe signal of a memory by monitoring duty cycle measurement data, so that the duty cycle of the data strobe signal is in an optimal state, thereby optimizing performance of the memory and stability of high-speed access.
Fig. 1A illustrates a schematic diagram of a duty cycle training circuit 100 provided according to an embodiment of the present disclosure.
As shown in fig. 1A, the duty cycle training circuit 100 includes a duty cycle measurement unit 101 and a training engine 102. Duty cycle measurement unit 101 is coupled to training engine 102, and duty cycle measurement unit 101 is also coupled to memory 103 external to duty cycle training circuit 100. The Memory 103 may be a DRAM, a Dual Inline Memory Module (DIMM), or the like.
The duty cycle measurement unit 101 is configured to obtain a measurement of the duty cycle of the memory 103. In the present disclosure, the duty ratio is a duty ratio of the data strobe signal of the memory 103, and may also be referred to as a duty ratio or a duty ratio of the memory 103. The measurements include a duty cycle greater than 50% and a duty cycle less than 50%. Although ideally, the duty ratio of the memory 103 should be equal to 50%, the duty ratio in the vicinity of 50% may be considered to be the optimum state for the process due to various unavoidable factors such as a manufacturing process and the like. For example, the measurement results are 1 and 0, or high level and low level, the measurement result is "1" or "high level" indicates that the duty ratio is more than 50%, and the measurement result is "0" or "low level" indicates that the duty ratio is less than 50%. The duty ratio measuring unit 101 may be implemented using, for example, an analog circuit.
Optionally, the measurement result may also be a specific value of the duty ratio, which is in a range of 0-100%, for example, 78%, 34%, and the like.
The training engine 102 is configured to generate a duty cycle adjustment command to instruct the memory 103 to adjust the duty cycle according to the measurement result sent by the duty cycle measurement unit 101. The training engine 102 may be implemented in various suitable microprocessors, such as ARM (advanced RISC machines)/RISCV (RISC-V Architecture), etc., and the training engine 102 may also be a hardware control circuit.
For example, if the training engine 102 receives that the measurement result sent by the duty ratio measurement unit 101 is that the duty ratio is greater than 50%, the training engine 102 generates a duty ratio adjustment command instructing to decrease the duty ratio, thereby causing the memory 103 to perform an adjustment operation of decreasing the duty ratio.
The duty ratio training circuit 100 can be used to adjust the duty ratio parameter independently, thereby avoiding the inaccuracy of adjusting the duty ratio by using an eye pattern.
Fig. 1B illustrates a schematic diagram of a duty cycle training circuit 100' provided in accordance with yet another embodiment of the present disclosure.
Similar to fig. 1A, the duty cycle training circuit 100' includes a duty cycle measurement unit 101 and a training engine 102, and further includes a command generator 104. Duty cycle measurement unit 101 is coupled to training engine 102, and duty cycle measurement unit 101 is also coupled to memory 103 external to duty cycle training circuit 100. The training engine 102 is coupled to a command generator 104.
The command generator 104 is configured to generate memory commands for altering the values of the mode registers within the memory 103 in accordance with the duty cycle adjustment commands sent by the training engine 102. For example, the memory command is a DRAM command, and the command generator 104 generates a DRAM command conforming to the DDR5 specification. The command generator 104 is, for example, a microprocessor or a dedicated hardware accelerator or the like.
The use of a single command generator 104 may reduce the performance requirements of the training engine 102, making the duty cycle training circuit easier to implement, and also providing a variety of schemes for implementing the duty cycle training circuit to address more scenarios.
With continued reference to fig. 1A, the duty cycle measurement unit 101 is further configured to measure the duty cycle of the memory 103 based on the received DQS signal to obtain a measurement.
The DQS signal is a data strobe signal that the memory 103 outputs in response to a read data command (which may also be referred to as a read command). The duty cycle of the DRAM, i.e., the duty cycle of the DQS signal, is measured in this application. The duty ratio measuring unit 101 measures the duty ratio based on the DQS signal, and the duty ratio can be directly obtained efficiently and accurately, so that the duty ratio can be adjusted more accurately.
Fig. 2 shows a schematic diagram of a duty cycle measurement unit 101 according to an embodiment of the present disclosure.
In fig. 2, the duty ratio measuring unit 101 includes a comparator 113. The comparator 113 is configured to compare the DQS signal to obtain a measurement and output the measurement to the training engine, the measurement including a high level and a low level, the high level indicating that the duty cycle value is greater than 50% and the low level indicating that the duty cycle value is less than 50%.
The DQS signal is typically a differential signal, such that comparator 113 receives differential DQS and DQS
And to DQS and
a comparison is made. For example, the comparator 113 outputA "1" indicates that the DQS duty cycle is greater than 50% and a "0" output by comparator 113 indicates that the DQS duty cycle is less than 50%.
Optionally, the duty ratio measuring unit 101 further includes an RC filter, and the RC filter may obtain a continuous analog quantity of the duty ratio of the DQS, and then quantize the analog quantity of the duty ratio into a digital signal by the comparator 113.
Fig. 2 shows an embodiment of the duty cycle measuring unit 101, so that the measurement of the duty cycle can be simply implemented. Other duty cycle measuring units can also be adopted in the embodiment of the application, for example, the duty cycle is measured through an eye pattern.
Referring again to fig. 1A, the training engine 102 is configured to: entering a duty ratio adjusting mode in response to the initialization of the memory 103 or the change of the working environment of the memory 103; a read command is sent to memory 103 to cause memory 103 to send the DQS signal to duty cycle measurement unit 101.
In the embodiment of the present disclosure, the training and/or adjustment of the duty cycle is performed in the duty cycle adjustment mode, which is entered when the memory 103 is powered on and initialized. After initialization, if it is determined that the duty cycle offset exceeds the threshold value due to a change in the operating environment of the memory 103 or the read data has been severely affected, the duty cycle adjustment mode is also entered without waiting for powering off and then powering on again.
For example, after determining that the operating environment of the memory 103 has changed, the training engine 102 generates an instruction to suspend the read/write operations to the memory 103 and enter the duty cycle adjustment mode. Training engine 102 then sends a read command to memory 103, causing memory 103 to feed back the DQS signal to duty cycle measurement unit 101. The read command may be a preset read command or a randomly generated read command.
Thus, according to the present embodiment, not only the training/adjustment of the duty ratio can be performed once when the memory 103 is powered on, but also a change in the working environment can be coped with.
Optionally, the training engine 102 is further configured to: generating a duty cycle adjustment command instructing to decrease the duty cycle when the measurement result indicates that the duty cycle value is greater than 50%; when the measurement indicates that the duty cycle value is less than 50%, a duty cycle adjustment command is generated that indicates an increase in the duty cycle.
Further optionally, the command generator 104 is configured to generate the DRAM command using a binary method, or in an incremental or decremental manner. The corresponding DRAM commands are generated using different methods or approaches. The binary method or incremental or decremental method is adopted in the embodiment to generate the DRAM command to find the optimal duty ratio of the data strobe signal, and meanwhile, the number of times of trying to find the optimal duty ratio can be reduced, so that the efficiency is improved.
In the embodiment of the present disclosure, the command generator 104 may generate a plurality of different DRAM commands according to the duty ratio adjustment command, where each DRAM command enables the memory 103 to modify the value of the mode register MR therein, that is, the DRAM command is a command instructing to modify the mode register MR. The plurality of DRAM commands are preset, respectively corresponding to different values of the modified mode register MR.
When the duty ratio adjustment command cannot accurately indicate the value of the current duty ratio, the command generator 104 only knows whether the current duty ratio is greater than 50% or less than 50% after receiving the duty ratio adjustment command. The command generator 104 further selects a DRAM command to be transmitted to the memory 103 from a preset plurality of DRAM commands by using a binary division, or in an increasing or decreasing manner. For example, 10 DRAM commands are preset, wherein DRAM commands No. 1-5 are used to increase the duty cycle, and DRAM commands No. 1-5 are sequentially increasing the amplitude increase of the duty cycle, DRAM commands No. 6-10 are used to decrease the duty cycle, and DRAM commands No. 6-10 are sequentially decreasing the amplitude increase of the duty cycle. Thus, when the duty cycle adjustment commands continuously received by the command generator 104 all indicate that the duty cycle is greater than 50%, the command generator 104 sequentially sends DRAM commands No. 6-10 to the memory 103 until the command generator 104 receives the duty cycle adjustment command indicating that the duty cycle is less than 50%. Similarly, when the duty cycle adjustment commands continuously received by the command generator 104 all indicate that the duty cycle is less than 50%, the command generator 104 sequentially sends DRAM commands No. 1-5 to the memory 103 until the command generator 104 receives the duty cycle adjustment command indicating that the duty cycle is greater than 50%.
For another example, when the duty ratio adjustment command cannot accurately indicate the value of the current duty ratio, and when the duty ratio adjustment commands continuously received by the command generator 104 all indicate that the duty ratio is less than 50%, the command generator 104 sequentially sends the DRAM commands No. 3, No. 2, or No. 4, No. 1, or No. 5 to the memory 103 by using the bisection method.
Optionally, the training engine 102 is configured to determine that the duty cycle is in the optimal state and stop the adjustment of the duty cycle when receiving the measurement result indicating that the duty cycle value is continuously changing between more than and less than 50% within a preset time period.
For example, the training engine 102 may begin timing each time a measurement is received and may restart timing if both the first and second measurements received indicate a duty cycle greater than 50% or both indicate a duty cycle less than 50%. If the received first measurement result and the second measurement result indicate that the duty ratio is more than 50% and the duty ratio is less than 50% (or the duty ratio is less than 50% and the duty ratio is more than 50%), continuing timing, and after the timing reaches a preset time period, considering that the duty ratio is in an optimal state of 50%.
Optionally, the training engine 102 may also use a counting method to determine whether the duty cycle is in an optimal state. For example, when 10 measurements indicating that the duty ratio is shifted between more than 50% and less than 50% are preset to be continuously received, it is determined that the current duty ratio is already in the optimum state. For example, training engine 102 receives measurement 1 indicating that the duty cycle is greater than 50%, measurement 2 indicating that the duty cycle is less than 50%, measurement 3 indicating that the duty cycle is greater than 50%, measurement 4 indicating that the duty cycle is less than 50%, … …, measurement 9 indicating that the duty cycle is greater than 50%, and measurement 10 indicating that the duty cycle is less than 50%, the 10 results indicating that the duty cycle has been changed 9 times around 50% and thus is considered to be stable around 50%.
When the duty ratio adjustment command can accurately indicate the value of the current duty ratio, after the command generator 104 receives the duty ratio adjustment command, a suitable DRAM command can be directly selected from a plurality of preset DRAM commands, so that the duty ratio is directly adjusted to the optimal state.
It should be noted that, in the present technology, a duty ratio of 50% is regarded as the optimal state of the duty ratio, and it is understood that, in the future technology development, if the optimal state is other values, the circuit and method in the present embodiment may also be adopted.
Optionally, the duty cycle training circuit 100 may further include a software access interface configured to provide functionality to access the duty cycle training circuit 100 to external software. For example, the software access interface is coupled to the training engine 102. For example, software (or firmware) running in the CPU of the system may each access the duty cycle training circuit 100 through the software access interface, such that external software may retrieve the measurement and in turn the external software may generate the duty cycle adjustment command or record the measurement, and the training engine 102 may receive an indication of the external software through the software access interface. According to the embodiment, the processing work of the duty ratio training circuit 100 and the performance requirement on the duty ratio training circuit can be further reduced, and various flexible optional schemes are provided for different application scenarios.
The software access Interface may support a variety of protocols, such as Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI), I2C (Inter Integrated Circuit), and so on.
FIG. 3 shows a schematic diagram of a memory according to an embodiment of the present disclosure.
As shown in fig. 3, the memory involved in embodiments of the present disclosure may be a DIMM 300 including a mode register 302.
The mode register 302 may include one or more mode registers, and the MR 302 is a mode register defined in, for example, the DDR5SDRAM specification.
Alternatively, the DIMM 300 may be an already packaged memory bank, such that the DIMM 300 may include DRAMs including the mode register 302. The DRAM in this embodiment may be understood as a memory granule on a memory bank, but the DRAM in the present disclosure is not limited to the memory granule, and may broadly refer to a memory.
Fig. 4 shows a flow chart of a duty cycle adjustment method according to an embodiment of the present disclosure.
As shown in fig. 4, the duty cycle adjusting method includes the steps of:
and S410, obtaining the measurement result of the duty ratio of the memory.
And S420, generating a duty ratio adjusting command to instruct the memory to adjust the duty ratio according to the measurement result.
Alternatively, the method of fig. 4 may be applied to the duty cycle training circuit shown in fig. 1A and 1B, and may also be implemented by a processor executing commands stored in a memory. Accordingly, the implementation of the method shown in fig. 4 can refer to the above description, and is not repeated herein.
By performing the method as shown in fig. 4, the measurement result of the duty cycle can be directly used to adjust the duty cycle, thereby avoiding the error caused by the prior art eye diagram scheme.
Optionally, the method further comprises generating a memory command for altering a value of a mode register within the memory in accordance with the duty cycle adjustment command.
Optionally, the method further comprises selecting a command to be sent to the memory from a preset plurality of memory commands according to the duty cycle adjustment command. The implementation mode can realize organic combination with DCA defined by DDR5SDRAM specification, thereby simply realizing the adjustment of duty ratio by utilizing the existing technical resources without large-scale improvement.
Optionally, obtaining the measurement of the duty cycle of the memory comprises measuring the duty cycle of the memory according to the received DQS signal to obtain the measurement.
Optionally, measuring a duty cycle of the memory to obtain a measurement result according to the received DQS signal, comprising: the DQS signal is compared to obtain a measurement that includes a high level indicating that the duty cycle value is greater than 50% and a low level indicating that the duty cycle value is less than 50%. The present embodiment provides a simple and feasible duty cycle acquisition approach.
Optionally, the method further comprises entering a duty cycle adjustment mode in response to a memory initialization or a change in an operating environment of the memory; a read command is sent to the memory to cause the memory to output the DQS signal. According to the embodiment, the duty ratio can be adjusted during the initialization of the memory, and the performance of the memory can be improved by responding to the change of the working environment.
Optionally, when the measurement result indicates that the duty cycle value is greater than 50%, generating a duty cycle adjustment command instructing to decrease the duty cycle; when the measurement indicates that the duty cycle value is less than 50%, a duty cycle adjustment command is generated that indicates an increase in the duty cycle.
Optionally, generating a memory command for changing a value of a mode register within a memory according to the duty cycle adjustment command comprises: the memory command is generated using a binary method, or in an incremental or decremental manner. The implementation mode provides a plurality of flexible and selectable command generation modes for coping with different working scenes.
Optionally, the method further comprises: and when the measurement result is received within the preset time period and represents that the duty ratio value is continuously changed between more than and less than 50%, determining that the duty ratio is in the optimal state, and stopping adjusting the duty ratio. The embodiment is not limited to obtaining an accurate value of the duty ratio, and the implementation is simpler, better results can be obtained, and the requirement on the computing capability can be reduced.
Optionally, the method further comprises: sending the measurement result to external software or receiving a duty ratio adjustment command of the external software. The implementation manner can flexibly adjust the execution main body for realizing the duty ratio adjusting method according to the limit or requirement of the computing resource or the processing resource required by the operation method.
Fig. 5 is a schematic diagram of a memory controller according to an embodiment of the disclosure. In fig. 5, memory controller 500 includes duty cycle training circuit 501, duty cycle training circuit 501 being coupled to memory 103. The duty training circuit 501 is, for example, a duty training circuit shown in fig. 1A or 1B. The memory controller 500 may implement the duty cycle training as described in the above embodiments, and may also perform the duty cycle adjustment method as described in the above embodiments. The specific implementation is not described herein.
The following points need to be explained:
(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.
(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.
Claims (21)
1. A duty cycle training circuit comprising:
a duty ratio measuring unit configured to acquire a measurement result of a duty ratio of a data strobe signal of the memory;
a training engine configured to generate a duty cycle adjustment command to instruct a memory to adjust a duty cycle of a data strobe signal according to the measurement result transmitted by the duty cycle measurement unit.
2. The duty cycle training circuit of claim 1, further comprising:
a command generator configured to generate a memory command to alter a value of a mode register within the memory in accordance with the duty cycle adjustment command sent by the training engine.
3. The duty cycle training circuit of claim 2, wherein the command generator is further configured to select a command to be sent to the memory from a preset plurality of memory commands according to the duty cycle adjustment command.
4. The duty cycle training circuit of claim 1, wherein the duty cycle measurement unit is further configured to measure a duty cycle of a data strobe signal of the memory to obtain the measurement from the received data strobe signal.
5. The duty cycle training circuit of claim 4, wherein the data strobe signal is a differential signal, the duty cycle measurement unit comprising:
a comparator configured to compare the data strobe signals to obtain the measurement, output the measurement to the training engine,
wherein the measurement result comprises a high level and a low level, the high level indicating that the duty cycle value is greater than 50% and the low level indicating that the duty cycle value is less than 50%.
6. The duty cycle training circuit of claim 1, wherein the training engine is further configured to:
entering a duty cycle adjustment mode in response to the initialization of the memory or a change in an operating environment of the memory;
sending a read command to the memory to cause the memory to send a data strobe signal to the duty cycle measurement unit.
7. The duty cycle training circuit of claim 1, wherein the training engine is further configured to:
generating a duty cycle adjustment command indicating a decreasing duty cycle when the measurement indicates a duty cycle value greater than 50%;
generating a duty cycle adjustment command indicating an increased duty cycle when the measurement indicates that the duty cycle value is less than 50%.
8. The duty cycle training circuit of claim 2,
the command generator is configured to generate the memory command using a binary method, or in an increasing or decreasing manner.
9. The duty cycle training circuit of claim 1,
the training engine is further configured to determine that the duty cycle is in an optimal state and stop adjusting the duty cycle when receiving the measurement result representing that the duty cycle value is continuously changed between more than and less than 50% within a preset time period.
10. The duty cycle training circuit of claim 1, wherein the duty cycle training circuit further comprises:
a software access interface configured to provide external software with functionality to access the duty cycle training circuit.
11. A duty cycle adjustment method, comprising:
obtaining a measurement result of the duty ratio of the memory;
and generating a duty ratio adjusting command to instruct a memory to adjust the duty ratio according to the measuring result sent by the duty ratio measuring unit.
12. The method of claim 11, further comprising:
generating a memory command for altering a value of a mode register within the memory in accordance with the duty cycle adjustment command.
13. The method of claim 11, further comprising:
and selecting a command to be sent to the memory from a plurality of preset memory commands according to the duty ratio adjusting command.
14. The method of claim 11, wherein the obtaining a measurement of a duty cycle of a data strobe signal of a memory comprises:
and measuring the duty ratio of the data strobe signal of the memory according to the received data strobe signal to obtain the measurement result.
15. The method of claim 14, wherein the measuring a duty cycle of a data strobe signal of the memory to obtain the measurement from the received data strobe signal comprises:
the data strobe signals are compared to obtain the measurement, which includes a high level and a low level, the high level indicating that the duty cycle value is greater than 50% and the low level indicating that the duty cycle value is less than 50%.
16. The method of claim 11, further comprising:
entering a duty cycle adjustment mode in response to the initialization of the memory or a change in an operating environment of the memory;
a read command is sent to the memory to cause the memory to output a data strobe signal.
17. The method of claim 11, wherein the generating the duty cycle adjustment command according to the measurement result sent by the duty cycle measurement unit comprises:
generating a duty cycle adjustment command indicating a decreasing duty cycle when the measurement indicates a duty cycle value greater than 50%;
generating a duty cycle adjustment command indicating an increased duty cycle when the measurement indicates that the duty cycle value is less than 50%.
18. The method of claim 12, wherein generating a memory command to alter a value of a mode register within the memory in accordance with the duty cycle adjustment command comprises:
the memory command is generated using a binary method, or in an incremental or decremental manner.
19. The method of claim 11, further comprising:
and when the measurement result is received within a preset time period and represents that the duty ratio value is continuously changed between more than 50% and less than 50%, determining that the duty ratio is in the optimal state, and stopping adjusting the duty ratio.
20. The method of claim 11, further comprising:
transmitting the measurement result to external software or receiving a duty ratio adjustment command that the external software is.
21. A memory controller, comprising:
the duty cycle training circuit of any one of claims 1-10.
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