CN116013394B - Memory training circuit and memory training method - Google Patents
Memory training circuit and memory training method Download PDFInfo
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- CN116013394B CN116013394B CN202310035056.XA CN202310035056A CN116013394B CN 116013394 B CN116013394 B CN 116013394B CN 202310035056 A CN202310035056 A CN 202310035056A CN 116013394 B CN116013394 B CN 116013394B
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Abstract
The invention provides a memory training circuit and a memory training method, wherein the circuit comprises: the device comprises a data transmission circuit, a plurality of delay sampling circuits, a comparison circuit and a training circuit; the data transmission circuit is used for controlling the memory device to transmit test data to the memory controller and transmitting the test data to the delay sampling circuit and the comparison circuit in blocks; the delay sampling circuit is used for carrying out delay sampling on a current clock signal and a current test data block of the memory device based on a current corresponding delay gear to obtain delay sampling data; the comparison circuit is used for comparing the delay sampling data with the current test data block and outputting a data matching result; the training circuit is used for determining a training result based on the data matching result, controlling the data transmission circuit to transmit the next test data block when the training result is not finished, and recording the delay gear currently corresponding to the corresponding delay sampling circuit when the training result is finished. The invention improves the efficiency of memory training.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a memory training circuit and a memory training method.
Background
Memory is often used to meet different levels of data exchange and storage requirements, however, factors such as increased frequency, clock jitter, phase drift, and unreasonable layout and wiring may lead to reduced stability of access to memory by the CPU (Central Processing Unit ). Therefore, in order to improve the access stability of the memory (such as DRAM (Dynamic Random Access Memory, dynamic random access memory), FLASH (FLASH memory), etc.), the memory may be trained, and the clock phase is shifted to an optimal phase according to the training mode by continuously adjusting the delay gear of the clock. However, in the current memory training mode, the operation of reading or writing once is sent each time, only one time of adjustment of the delay gear can be completed, if the range of the delay gear is wider, the very frequent memory reading and writing operation can be brought, the memory training efficiency is lower, and the starting or switching speed of the corresponding device is prolonged.
Disclosure of Invention
The invention provides a memory training circuit and a memory training method, which are used for solving the defect of low memory training efficiency in the prior art.
The invention provides a memory training circuit, which is deployed in a memory controller and comprises:
the device comprises a data transmission circuit, a plurality of delay sampling circuits, a comparison circuit and a training circuit;
the data transmission circuit is used for controlling the memory device to transmit test data to the memory controller and transmitting the test data to the delay sampling circuit and the comparison circuit in blocks;
the delay sampling circuit is used for carrying out delay sampling on a current clock signal and a current test data block of the memory device based on a current corresponding delay gear to obtain delay sampling data; the delay gears corresponding to the different delay sampling circuits are different, and the delay gears corresponding to the same delay sampling circuit when carrying out delay sampling on different test data blocks are different;
the comparison circuit is used for comparing the delay sampling data with the current test data block and outputting a data matching result;
the training circuit is used for determining a training result based on the data matching result, controlling the data transmission circuit to transmit the next test data block when the training result is not finished, and recording the delay gear currently corresponding to the corresponding delay sampling circuit when the training result is finished.
According to the memory training circuit provided by the invention, the plurality of delay sampling circuits are divided into N delay sampling circuit groups, N is more than or equal to 2, and each delay sampling group comprises a plurality of delay sampling circuits;
if the delay sampling circuit currently performing delay sampling is the delay sampling circuit in the ith delay sampling circuit group, the training circuit controls the data transmission circuit to transmit the next test data block to the delay sampling circuit in the (i+1) mod (n+1) th delay sampling circuit group when the training result is not finished, wherein 0<i is less than or equal to N.
According to the memory training circuit provided by the invention, the circuit further comprises a delay gear recorder, wherein the delay gear recorder is used for recording the highest delay gear currently corresponding to each delay sampling circuit;
in the process that the delay sampling circuit in the ith delay sampling circuit group carries out delay sampling on the clock signal of the memory device and the current test data block based on the current corresponding delay gear, the delay sampling circuit in the (i+1) mod (n+1) th delay sampling circuit group updates the current corresponding delay gear of the corresponding delay sampling circuit and the value of the delay gear recorder based on the value of the delay gear recorder.
According to the memory training circuit provided by the invention, the delay sampling circuit comprises a clock delay device and a sampler;
the clock delayer is used for delaying the current clock signal of the memory device based on the current corresponding delay gear to obtain a delay clock signal; the sampler is used for sampling the delay clock signal output by the clock delayer in the same delay sampling circuit and the current test data block to obtain delay sampling data.
According to the memory training circuit provided by the invention, the delay sampling circuit comprises a data signal delayer and a sampler;
the data signal delayer is used for delaying the data signal corresponding to the current test data block based on the current corresponding delay gear to obtain a delay data signal; the sampler is used for sampling a delay data signal output by the data signal delayer in the same delay sampling circuit and a current clock signal of the memory device to obtain delay sampling data.
According to the invention, the memory training circuit is further used for:
when the data matching result is matching and the first delay boundary value is empty, recording the delay gear corresponding to the corresponding delay sampling circuit currently and assigning the delay gear to the first delay boundary value, and determining that the training result is not finished;
when the data matching result is not matched, the first delay boundary value is not null and the second delay boundary value is null, recording the delay gear corresponding to the corresponding delay sampling circuit currently, assigning the delay gear to the second delay boundary value, and determining that the training result is finished; and determining a stable delay gear based on the first delay boundary value and the second delay boundary value, selecting one delay sampling circuit from the plurality of delay sampling circuits to keep an on state, and pushing the stable delay gear to the delay sampling circuit kept in the on state.
According to the memory training circuit provided by the invention, the data transmission circuit is specifically used for writing the test data into the memory device through the write instruction, and sending the read instruction to the write address in the write instruction, so as to control the memory device to transmit the test data to the memory controller.
The invention also provides a memory training method based on any one of the memory training circuits, which comprises the following steps:
the method comprises the steps of controlling a memory device to transmit test data to a memory controller by utilizing a data transmission circuit, dividing the test data into blocks, and transmitting a current test data block to a delay sampling circuit and a comparison circuit;
performing delay sampling on a current clock signal and a current test data block of the memory device based on a current corresponding delay gear by using the delay sampling circuit to obtain delay sampling data; the delay gears corresponding to the different delay sampling circuits are different, and the delay gears corresponding to the same delay sampling circuit when carrying out delay sampling on different test data blocks are different;
comparing the delay sampling data with the current test data block by using a comparison circuit to obtain a data matching result;
and determining a training result by using the training circuit based on the data matching result, controlling the data transmission circuit to transmit the next test data block when the training result is not finished, and recording the delay gear currently corresponding to the corresponding delay sampling circuit when the training result is finished.
According to the memory training method provided by the invention, the plurality of delay sampling circuits are divided into N delay sampling circuit groups, N is more than or equal to 2, and each delay sampling group comprises a plurality of delay sampling circuits;
if the delay sampling circuit currently performing delay sampling is the delay sampling circuit in the ith delay sampling circuit group, the training circuit is utilized to control the data transmission circuit to transmit the next test data block to the delay sampling circuit in the (i+1) th mod (n+1) th delay sampling circuit group when the training result is not finished, wherein 0<i is less than or equal to N.
According to the memory training method provided by the invention, in the process of carrying out delay sampling on the clock signal of the memory device and the current test data block based on the current corresponding delay gear by utilizing the delay sampling circuit in the ith delay sampling circuit group, the delay sampling circuit in the (i+1) mod (N+1) th delay sampling circuit group is utilized to update the current corresponding delay gear of the corresponding delay sampling circuit and the value of the delay gear recorder based on the value of the delay gear recorder.
According to the memory training circuit and the memory training method provided by the invention, the memory device is controlled to transmit a section of longer test data to the memory controller at one time based on the data transmission circuit, then the longer test data is segmented and then sequentially transmitted to the delay sampling circuit and the comparison circuit under the control of the training circuit, so that the read-write times of the memory device are greatly reduced, and the read-write time cost of the memory device in the training process is reduced; the delay sampling circuit performs delay sampling on a current clock signal and a current test data block of the memory device based on a current corresponding delay gear to obtain delay sampling data, and then judges whether a proper delay gear is obtained based on the comparison circuit and the training circuit so as to determine the time when training is finished; the test data block received at the same moment can be tested by adopting a plurality of delay gears at the same time, and whether the delay gears are proper delay gears or not is judged, so that the training speed of the memory is greatly improved; in addition, for the same delay sampling circuit, delay sampling can be carried out on test data blocks transmitted at different moments when training is not finished, and delay gears corresponding to the delay sampling are different when delay sampling is carried out on different test data blocks, so that the delay gear test range which can be born by test data transmitted by the memory device for one time is further widened, the training capacity of the test data transmitted by the memory device for one time is enhanced, the times that a read instruction is sent to the memory device by the memory controller is reduced, the response time of the memory controller waiting for the memory device is further reduced, and the efficiency of memory training is further improved.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory training circuit according to the present invention;
FIG. 2 is a flow chart of a memory training method provided by the present invention;
FIG. 3 is a schematic flow chart of the delay sampling method according to the present invention;
FIG. 4 is a second flow chart of the delay sampling method according to the present invention;
FIG. 5 is a flow chart of the training control method provided by the invention;
reference numerals:
110: a memory controller; 120: a data transmission circuit; 130: a delay sampling circuit;
140: a comparison circuit; 150: a training circuit; 160: a memory device.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a schematic diagram of a memory training circuit according to the present invention, and as shown in fig. 1, the memory training circuit is disposed in a memory controller 110, and the memory training circuit includes: a data transmission circuit 120, a plurality of delay sampling circuits 130, a comparison circuit 140, and a training circuit 150;
the data transmission circuit 120 is configured to control the memory device 160 to transmit test data to the memory controller 110, and transmit the test data to the delay sampling circuit 130 and the comparison circuit 140 in blocks;
the delay sampling circuit 130 is configured to perform delay sampling on a current clock signal and a current test data block of the memory device 160 based on a current corresponding delay gear to obtain delay sampling data; the delay gears corresponding to the different delay sampling circuits 130 are different, and the delay gears corresponding to the same delay sampling circuit 130 when delay sampling is performed on different test data blocks are different;
the comparison circuit 140 is configured to compare the delay sampled data with the current test data block and output a data matching result;
the training circuit 150 is configured to determine a training result based on the data matching result, control the data transmission circuit 120 to transmit a next test data block when the training result is not finished, and record a delay gear currently corresponding to the corresponding delay sampling circuit when the training result is finished.
Specifically, the data transmission circuit 120 may control the memory device 160 to transmit a longer length of test data to the memory controller 110 at a time, and then the data transmission circuit 120 may block the longer length of test data and sequentially transmit the block of test data to the delay sampling circuit 130 and the comparison circuit 140 under the control of the training circuit 150. Wherein the test data block obtained after the test data block is used to adjust the delay gear to confirm the appropriate delay gear that can phase match the data signal transmitted by the memory device 160 with the clock signal of the memory device 160. The delay gear may be delay time, the number of basic delay units or delay grade, which may indicate delay time, and the embodiment of the present invention is not limited in particular. If the plurality of test data blocks obtained after the test data are segmented are enough to enable the training circuit to acquire the proper delay gear, the training is successful, and the memory device 160 is not required to be subjected to read-write operation, so that the read-write times of the memory device 160 are greatly reduced, and the time cost of the memory device in the training process is reduced.
After the data transmission circuit 120 transmits the current test data block to the delay sampling circuit 130 and the comparison circuit 140, the delay sampling circuit 130 performs delay sampling on the current clock signal of the memory device 160 and the current test data block based on the current corresponding delay gear, so as to obtain delay sampling data. For the same test data block, a plurality of different delay sampling circuits 130 may be used to sample the test data block in a delay manner, and delay gears corresponding to the plurality of different delay sampling circuits are different. Therefore, for the test data block received at the same time, a plurality of delay gears can be used for testing at the same time, so as to determine whether the delay gears are suitable delay gears capable of matching the data signals transmitted by the memory device 160 and the clock signals of the memory device 160, thereby greatly improving the training speed of the memory. In addition, for the same delay sampling circuit, delay sampling can be performed on test data blocks transmitted at different moments when training is not finished, and delay gears corresponding to the delay sampling are different when delay sampling is performed on different test data blocks, so that the delay gear test range which can be born by test data transmitted by the memory device 160 for one time is further widened, the training capacity of the test data transmitted by the memory device 160 for one time is enhanced, and the time cost of reading and writing of the memory device in the training process is reduced.
The delay sampling circuit 130 performs delay sampling on the current clock signal and the current test data block of the memory device 160 based on the current corresponding delay gear, which is not particularly limited in the embodiment of the present invention:
(1) The delay object is a clock signal: the delay sampling circuit 130 includes a clock delay and a sampler; the delayer is configured to delay the current clock signal of the memory device 160 based on the current corresponding delay gear to obtain a delayed clock signal; the sampler is configured to sample the delayed clock signal output by the clock delayer in the same delay sampling circuit 130 and the current test data block, so as to obtain delay sampling data.
(2) The delay object is the current test data block: the delay sampling circuit 130 includes a data signal delay device and a sampler; the data signal delayer is used for delaying the data signal corresponding to the current test data block based on the current corresponding delay gear to obtain a delay data signal; the sampler is configured to sample the delayed data signal output by the data signal delayer in the same delay sampling circuit and the current clock signal of the memory device 160, so as to obtain delay sampling data.
The delay sampling circuit 130 performs delay sampling on the current clock signal and the current test data block of the memory device 160, and outputs delay sampling data to the comparison circuit 140 after obtaining delay sampling data. The comparison circuit 140 compares the received delay sampled data with the current test data block (i.e., the test data block received by the corresponding delay sampled circuit), and determines whether the delay sampled data is consistent with the current test data block, thereby outputting a corresponding data matching result. And if the delay sampling data is consistent with the current test data block, the data matching result is matching, otherwise, the data matching result is not matching. Then, the comparison circuit 140 outputs the data matching result corresponding to each of the delay sample data to the training circuit 150. Training circuit 150 may determine training results based on the data matching results described above.
If the data matching result corresponding to the delay sampling data output by any delay sampling circuit 130 is a match, it may be considered that a suitable delay gear capable of matching the phase of the data signal transmitted by the memory device 160 with the phase of the clock signal of the memory device 160 is obtained currently, so that it may be determined that the training result is finished, and the delay gear currently corresponding to the corresponding delay sampling circuit is recorded, and is used as the delay gear for the subsequent normal data transceiving of the memory device 160, to perform delay sampling on the current clock signal and the transmission data of the memory device 160. At this time, only one delay sampling circuit may be kept in an on state, and the other delay sampling circuits may be turned off. If the data matching results corresponding to the delay sampling data output by each delay sampling circuit are not matched, the fact that the delay gears corresponding to the delay sampling circuits are not suitable at present is indicated, and therefore other delay gears need to be continuously tested. At this time, the training circuit 150 may control the data transmission circuit 120 to transmit the next test data block to the delay sampling circuit 130 and the comparison circuit 140. When the delay sampling circuit 130 receives the next test data block, the current clock signal of the memory device 160 and the test data block are delay-sampled based on the updated delay gear. The updated delay gear corresponding to any delay sampling circuit is different from the historical delay gears used in the previous training process of all delay sampling circuits.
According to the circuit provided by the embodiment of the invention, the memory device is controlled to transmit a section of longer test data to the memory controller once based on the data transmission circuit, then the longer test data is segmented and then sequentially transmitted to the delay sampling circuit and the comparison circuit under the control of the training circuit, so that the read-write times of the memory device are greatly reduced, and the time cost of the memory device in the training process is reduced; the delay sampling circuit performs delay sampling on a current clock signal and a current test data block of the memory device based on a current corresponding delay gear to obtain delay sampling data, and then judges whether a proper delay gear is obtained based on the comparison circuit and the training circuit so as to determine the time when training is finished; the test data block received at the same moment can be tested by adopting a plurality of delay gears at the same time, and whether the delay gears are proper delay gears or not is judged, so that the training speed of the memory is greatly improved; in addition, for the same delay sampling circuit, delay sampling can be carried out on test data blocks transmitted at different moments when training is not finished, and delay gears corresponding to the delay sampling are different when delay sampling is carried out on different test data blocks, so that the delay gear test range which can be born by test data transmitted by the memory device for one time is further widened, the training capacity of the test data transmitted by the memory device for one time is enhanced, the times that a read instruction is sent to the memory device by the memory controller is reduced, the response time of the memory controller waiting for the memory device is further reduced, and the efficiency of memory training is further improved.
Based on the embodiment, the plurality of delay sampling circuits are divided into N delay sampling circuit groups, N is more than or equal to 2, and each delay sampling group comprises a plurality of delay sampling circuits;
if the delay sampling circuit currently performing delay sampling is the delay sampling circuit in the ith delay sampling circuit group, the training circuit controls the data transmission circuit to transmit the next test data block to the delay sampling circuit in the (i+1) mod (n+1) th delay sampling circuit group when the training result is not finished, wherein 0<i is less than or equal to N.
Specifically, the plurality of delay sampling circuits may be divided into a plurality of portions on average, resulting in N delay sampling circuit groups. Wherein N is more than or equal to 2, each delay sampling group comprises a plurality of delay sampling circuits, and the delay sampling circuits of each delay sampling circuit group are used for alternately carrying out delay sampling on the received test data block and the clock signal. When one part of delay sampling circuits are in a working state to carry out delay sampling, the idle time can be effectively utilized to enable the other part of delay sampling circuits to carry out delay gear switching operation and prepare for next delay sampling, so that the time cost of each delay sampling circuit when switching delay gears is reduced by ping-pong operation, and the efficiency of memory training is further improved.
Specifically, if the delay sampling circuit currently performing delay sampling is the delay sampling circuit in the ith delay sampling circuit group, the delay sampling circuit in the (i+1) th mod (n+1) th delay sampling circuit group performs delay sampling, so the training circuit 150 transmits the next test data block to the delay sampling circuit in the (i+1) th mod (n+1) th delay sampling circuit group when the training result is not finished. Wherein 0<i is less than or equal to N.
Based on any one of the above embodiments, the circuit further includes a delay gear recorder, configured to record a highest delay gear currently corresponding to each delay sampling circuit;
in the process that the delay sampling circuit in the ith delay sampling circuit group carries out delay sampling on the clock signal of the memory device and the current test data block based on the current corresponding delay gear, the delay sampling circuit in the (i+1) mod (n+1) th delay sampling circuit group updates the current corresponding delay gear of the corresponding delay sampling circuit and the value of the delay gear recorder based on the value of the delay gear recorder.
Specifically, the highest delay gear currently corresponding to each delay sampling circuit is recorded in the delay gear recorder, and any delay sampling circuit can update the delay gear based on the value in the delay gear recorder and update the updated delay gear to the delay gear recorder in time. In the process that the delay sampling circuit in the ith delay sampling circuit group performs delay sampling on the clock signal of the memory device 160 and the current test data block based on the current corresponding delay gear, the delay sampling circuit in the (i+1) mod (n+1) th delay sampling circuit group may update the current corresponding delay gear of the corresponding delay sampling circuit and the value of the delay gear recorder based on the value of the delay gear recorder. Any delay sampling circuit in the (i+1) mod (n+1) th delay sampling circuit group can add a preset step length to the current value of the delay gear recorder to serve as the delay gear corresponding to the delay sampling circuit currently, and meanwhile, the delay gear is updated into the delay gear recorder.
Based on any of the above embodiments, the training circuit is further configured to:
when the data matching result is matching and the first delay boundary value is empty, recording the delay gear corresponding to the corresponding delay sampling circuit currently and assigning the delay gear to the first delay boundary value, and determining that the training result is not finished;
when the data matching result is not matched, the first delay boundary value is not null and the second delay boundary value is null, recording the delay gear corresponding to the corresponding delay sampling circuit currently, assigning the delay gear to the second delay boundary value, and determining that the training result is finished; and determining a stable delay gear based on the first delay boundary value and the second delay boundary value, selecting one delay sampling circuit from the plurality of delay sampling circuits to keep an on state, and pushing the stable delay gear to the delay sampling circuit kept in the on state.
Specifically, to obtain an optimal delay gear capable of phase matching the data signal transmitted by the memory device 160 and the clock signal of the memory device 160 to ensure the stability of reading and writing of the memory device, the training circuit 150 may obtain a gear range of an appropriate delay gear and determine the optimal delay gear within the gear range. When the data matching result corresponding to the delay sampling data output by a certain delay sampling circuit is matching and the current first delay boundary value is null (indicating that the proper delay gear is obtained for the first time in the training process), the corresponding delay sampling circuit (namely, the delay sampling circuit outputting the delay sampling data corresponding to the data matching result) is recorded and assigned to the first delay boundary value, and the training result is determined to be not finished. At this time, the proper delay gear is obtained for the first time in the training process, so that the delay gear is considered to be a marginal value and has a certain instability, the training process is not finished temporarily, and the first delay boundary value can be regarded as the lower boundary of the gear range of the proper delay gear.
And then, in the subsequent training process, if the data matching result is mismatch, the first delay boundary value is not null, and the second delay boundary value is null (indicating that an unsuitable delay gear appears for the first time after the suitable delay gear is obtained in the current training process), recording the delay gear currently corresponding to the corresponding delay sampling circuit, assigning the delay gear to the second delay boundary value, and determining that the training result is finished. The second delay boundary value obtained at this time may be regarded as the upper boundary of the range of the appropriate delay gear. Then, a stable delay gear is determined based on the first delay boundary value and the second delay boundary value. The average value of the first delay boundary value and the second delay boundary value can be selected as a stable delay gear. And selecting one delay sampling circuit from the delay sampling circuits to keep an on state, closing other delay sampling circuits, and pushing the stable delay gear to the delay sampling circuit kept in the on state so as to delay and sample the current clock signal and transmission data of the memory device in the subsequent normal data receiving and transmitting process of the memory device.
Based on any of the above embodiments, the data transmission circuit is specifically configured to write the test data into the memory device through a write command, and send a read command to a write address in the write command, so as to control the memory device to transmit the test data to the memory controller.
Specifically, the memory controller may prepare a long random test data in advance, write the test data into the memory by means of a write command through the data transmission circuit, and send a read command to a write address in the write command to control the memory device to transmit the test data to the memory controller.
The memory training method provided by the invention is described below, and the memory training method described below and the memory training circuit described above can be referred to correspondingly.
Based on any one of the above embodiments, fig. 2 is a schematic flow chart of a memory training method according to the present invention, where the method is based on the memory training circuit according to any one of the above embodiments, and as shown in fig. 2, the method includes:
step 210, using a data transmission circuit to control a memory device to transmit test data to a memory controller, partitioning the test data, and transmitting a current test data block to a delay sampling circuit and a comparison circuit;
step 220, performing delay sampling on the current clock signal and the current test data block of the memory device based on the current corresponding delay gear by using the delay sampling circuit to obtain delay sampling data; the delay gears corresponding to the different delay sampling circuits are different, and the delay gears corresponding to the same delay sampling circuit when carrying out delay sampling on different test data blocks are different;
step 230, comparing the delay sampling data with the current test data block by using a comparison circuit to obtain a data matching result;
and 240, determining a training result by using the training circuit based on the data matching result, controlling the data transmission circuit to transmit the next test data block when the training result is not finished, and recording the delay gear currently corresponding to the corresponding delay sampling circuit when the training result is finished.
According to the method provided by the embodiment of the invention, the memory device is controlled to transmit a section of longer test data to the memory controller at one time based on the data transmission circuit, then the longer test data is segmented and then sequentially transmitted to the delay sampling circuit and the comparison circuit under the control of the training circuit, so that the read-write times of the memory device are greatly reduced, and the time cost of the memory device in the training process is reduced; the delay sampling circuit performs delay sampling on a current clock signal and a current test data block of the memory device based on a current corresponding delay gear to obtain delay sampling data, and then judges whether a proper delay gear is obtained based on the comparison circuit and the training circuit so as to determine the time when training is finished; the test data block received at the same moment can be tested by adopting a plurality of delay gears at the same time, and whether the delay gears are proper delay gears or not is judged, so that the training speed of the memory is greatly improved; in addition, for the same delay sampling circuit, delay sampling can be carried out on test data blocks transmitted at different moments when training is not finished, and delay gears corresponding to the delay sampling are different when delay sampling is carried out on different test data blocks, so that the delay gear test range which can be born by test data transmitted by the memory device for one time is further widened, the training capacity of the test data transmitted by the memory device for one time is enhanced, the times that a read instruction is sent to the memory device by the memory controller is reduced, the response time of the memory controller waiting for the memory device is further reduced, and the efficiency of memory training is further improved.
Based on any one of the above embodiments, the plurality of delay sampling circuits are divided into N delay sampling circuit groups, where N is greater than or equal to 2, and each delay sampling group includes a plurality of delay sampling circuits;
if the delay sampling circuit currently performing delay sampling is the delay sampling circuit in the ith delay sampling circuit group, the training circuit is utilized to control the data transmission circuit to transmit the next test data block to the delay sampling circuit in the (i+1) th mod (n+1) th delay sampling circuit group when the training result is not finished, wherein 0<i is less than or equal to N.
Based on any one of the embodiments, in the process of performing delay sampling on the clock signal of the memory device and the current test data block based on the current corresponding delay gear by using the delay sampling circuit in the ith delay sampling circuit group, updating the current corresponding delay gear of the corresponding delay sampling circuit and the value of the delay gear recorder by using the delay sampling circuit in the (i+1) mod (n+1) th delay sampling circuit group based on the value of the delay gear recorder.
Based on any of the foregoing embodiments, as shown in fig. 3, the performing, by using the delay sampling circuit, delay sampling on the current clock signal and the current test data block of the memory device based on the current corresponding delay gear to obtain delay sampling data specifically includes:
step 310, delaying the current clock signal of the memory device based on the current corresponding delay gear by using the clock delayer of the delay sampling circuit to obtain a delay clock signal;
and 320, sampling the delayed clock signal output by the clock delayer in the same delayed sampling circuit and the current test data block by using the sampler of the delayed sampling circuit to obtain delayed sampling data.
Based on any of the foregoing embodiments, as shown in fig. 4, the performing, by using the delay sampling circuit, delay sampling on the current clock signal and the current test data block of the memory device based on the current corresponding delay gear to obtain delay sampling data specifically includes:
step 410, delaying the data signal corresponding to the current test data block based on the current corresponding delay gear by using the data signal delayer of the delay sampling circuit to obtain a delayed data signal;
and step 420, sampling the delayed data signal output by the data signal delayer in the same delayed sampling circuit and the current clock signal of the memory device by using the sampler of the delayed sampling circuit to obtain delayed sampling data.
Based on any of the above embodiments, as shown in fig. 5, the determining, by using a training circuit, a training result based on the data matching result, controlling the data transmission circuit to transmit a next test data block when the training result is not finished, and recording a delay gear currently corresponding to a corresponding delay sampling circuit when the training result is finished, where the method specifically includes:
step 510, when the data matching result is matching and the first delay boundary value is null, recording the delay gear currently corresponding to the corresponding delay sampling circuit and assigning the delay gear to the first delay boundary value, and determining that the training result is not finished;
step 520, when the data matching result is not matching, the first delay boundary value is not null, and the second delay boundary value is null, recording the delay gear currently corresponding to the corresponding delay sampling circuit and assigning the delay gear to the second delay boundary value, and determining that the training result is finished; and determining a stable delay gear based on the first delay boundary value and the second delay boundary value, selecting one delay sampling circuit from the plurality of delay sampling circuits to keep an on state, and pushing the stable delay gear to the delay sampling circuit kept in the on state.
Based on any one of the above embodiments, the controlling the memory device to transmit the test data to the memory controller by using the data transmission circuit specifically includes:
and writing the test data into the memory device through a write instruction, and sending a read instruction to a write address in the write instruction to control the memory device to transmit the test data to the memory controller.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A memory training circuit, the memory training circuit disposed in a memory controller, comprising:
the device comprises a data transmission circuit, a plurality of delay sampling circuits, a comparison circuit and a training circuit;
the data transmission circuit is used for controlling the memory device to transmit test data to the memory controller and transmitting the test data to the delay sampling circuit and the comparison circuit in blocks;
the delay sampling circuit is used for carrying out delay sampling on a current clock signal and a current test data block of the memory device based on a current corresponding delay gear to obtain delay sampling data; the delay gears corresponding to the different delay sampling circuits are different, and the delay gears corresponding to the same delay sampling circuit when carrying out delay sampling on different test data blocks are different;
the comparison circuit is used for comparing the delay sampling data with the current test data block and outputting a data matching result;
the training circuit is used for determining a training result based on the data matching result, controlling the data transmission circuit to transmit the next test data block when the training result is not finished, and recording the delay gear currently corresponding to the corresponding delay sampling circuit when the training result is finished.
2. The memory training circuit of claim 1, wherein the plurality of delay sampling circuits are divided into N delay sampling circuit groups, wherein N is greater than or equal to 2, and each delay sampling group comprises a plurality of delay sampling circuits;
if the delay sampling circuit currently performing delay sampling is the delay sampling circuit in the ith delay sampling circuit group, the training circuit controls the data transmission circuit to transmit the next test data block to the delay sampling circuit in the (i+1) mod (n+1) th delay sampling circuit group when the training result is not finished, wherein 0<i is less than or equal to N.
3. The memory training circuit of claim 2, further comprising a delay gear recorder for recording a highest delay gear currently corresponding to each delay sampling circuit;
in the process that the delay sampling circuit in the ith delay sampling circuit group carries out delay sampling on the clock signal of the memory device and the current test data block based on the current corresponding delay gear, the delay sampling circuit in the (i+1) mod (n+1) th delay sampling circuit group updates the current corresponding delay gear of the corresponding delay sampling circuit and the value of the delay gear recorder based on the value of the delay gear recorder.
4. The memory training circuit of claim 1, wherein the delay sampling circuit comprises a clock delay and a sampler;
the clock delayer is used for delaying the current clock signal of the memory device based on the current corresponding delay gear to obtain a delay clock signal; the sampler is used for sampling the delay clock signal output by the clock delayer in the same delay sampling circuit and the current test data block to obtain delay sampling data.
5. The memory training circuit of claim 1, wherein the delay sampling circuit comprises a data signal delay and a sampler;
the data signal delayer is used for delaying the data signal corresponding to the current test data block based on the current corresponding delay gear to obtain a delay data signal; the sampler is used for sampling a delay data signal output by the data signal delayer in the same delay sampling circuit and a current clock signal of the memory device to obtain delay sampling data.
6. The memory training circuit of any of claims 1 to 5, wherein the training circuit is further to:
when the data matching result is matching and the first delay boundary value is empty, recording the delay gear corresponding to the corresponding delay sampling circuit currently and assigning the delay gear to the first delay boundary value, and determining that the training result is not finished;
when the data matching result is not matched, the first delay boundary value is not null and the second delay boundary value is null, recording the delay gear corresponding to the corresponding delay sampling circuit currently, assigning the delay gear to the second delay boundary value, and determining that the training result is finished; and determining a stable delay gear based on the first delay boundary value and the second delay boundary value, selecting one delay sampling circuit from the plurality of delay sampling circuits to keep an on state, and pushing the stable delay gear to the delay sampling circuit kept in the on state.
7. The memory training circuit of any of claims 1 to 5, wherein the data transfer circuit is specifically configured to write the test data into the memory device via a write command and to send a read command to a write address in the write command, controlling the memory device to transfer the test data to the memory controller.
8. A memory training method based on the memory training circuit as claimed in one of claims 1 to 7, comprising:
the method comprises the steps of controlling a memory device to transmit test data to a memory controller by utilizing a data transmission circuit, dividing the test data into blocks, and transmitting a current test data block to a delay sampling circuit and a comparison circuit;
performing delay sampling on a current clock signal and a current test data block of the memory device based on a current corresponding delay gear by using the delay sampling circuit to obtain delay sampling data; the delay gears corresponding to the different delay sampling circuits are different, and the delay gears corresponding to the same delay sampling circuit when carrying out delay sampling on different test data blocks are different;
comparing the delay sampling data with the current test data block by using a comparison circuit to obtain a data matching result;
and determining a training result by using the training circuit based on the data matching result, controlling the data transmission circuit to transmit the next test data block when the training result is not finished, and recording the delay gear currently corresponding to the corresponding delay sampling circuit when the training result is finished.
9. The memory training method of claim 8, wherein the plurality of delay sampling circuits are divided into N delay sampling circuit groups, N being equal to or greater than 2, each delay sampling group including a plurality of delay sampling circuits;
if the delay sampling circuit currently performing delay sampling is the delay sampling circuit in the ith delay sampling circuit group, the training circuit is utilized to control the data transmission circuit to transmit the next test data block to the delay sampling circuit in the (i+1) th mod (n+1) th delay sampling circuit group when the training result is not finished, wherein 0<i is less than or equal to N.
10. The memory training method of claim 9, wherein in the process of using the delay sampling circuit in the ith delay sampling circuit group to delay sample the clock signal and the current test data block of the memory device based on the current corresponding delay gear, using the delay sampling circuit in the (i+1) mod (n+1) th delay sampling circuit group to update the current corresponding delay gear of the corresponding delay sampling circuit and the value of the delay gear recorder based on the value of the delay gear recorder.
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| CN110364202A (en) * | 2019-07-22 | 2019-10-22 | 上海兆芯集成电路有限公司 | Memory device |
| CN111831593A (en) * | 2019-04-22 | 2020-10-27 | 英特尔公司 | Apparatus, system, and method for generating link training signals |
| CN115113812A (en) * | 2022-05-20 | 2022-09-27 | 腾讯科技（深圳）有限公司 | Write data signal delay control method, apparatus, device, and medium |
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| CN111831593A (en) * | 2019-04-22 | 2020-10-27 | 英特尔公司 | Apparatus, system, and method for generating link training signals |
| CN110364202A (en) * | 2019-07-22 | 2019-10-22 | 上海兆芯集成电路有限公司 | Memory device |
| CN115113812A (en) * | 2022-05-20 | 2022-09-27 | 腾讯科技（深圳）有限公司 | Write data signal delay control method, apparatus, device, and medium |
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