CN103034572B - Method and system for debugging double data rate synchronous dynamic random access memory (DDR SDRAM) - Google Patents
Method and system for debugging double data rate synchronous dynamic random access memory (DDR SDRAM) Download PDFInfo
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- CN103034572B CN103034572B CN201210544684.2A CN201210544684A CN103034572B CN 103034572 B CN103034572 B CN 103034572B CN 201210544684 A CN201210544684 A CN 201210544684A CN 103034572 B CN103034572 B CN 103034572B
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Abstract
The invention provides a method for debugging a double data rate synchronous dynamic random access memory (DDR SDRAM). According to the method, a data stroke (DQS) phase is adjusted through gradually adjusting the value of a Buffer 1, a data (DQ) phase is adjusted through gradually adjusting the value of a Buffer 2, and an adjusting cycle of the DQS phase and an adjusting cycle of the DQ phase are constructed through analyzing the working condition of the DDR SDRAM after the value of the Buffer 1 and the value of the Buffer 2 are adjusted, and further, the best operating point of the DDR SDRAM is found out, so that a DQS signal and a DQ signal are harmonious, and the phenomenon that an error occurs when a read operation is performed on the DDR SDRAM by a micro control unit (MCU) is avoided. The invention also provides a system for debugging the DDR SDRAM.
Description
Technical field
The present invention relates to a kind of device debugging technique, particularly a kind of DDR adjustment method and system.
Background technology
DDR full name is: DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory, Double Data Rate synchronous DRAM).Because DDR read/write data speed is higher, also more and more higher to the requirement of sequential and signal, and on the other hand, because the requirement of cost, PCB (Printed Circuit Board, printed circuit board) size more and more less, also more and more higher to the requirement of PCB layout-design, be difficult to accomplish that all differential signal cablings are isometric, therefore equal difference time delay will be produced between signal, can cause when time delay acquires a certain degree occurring unsuccessfully to the read/write operation of DDR, thus cause the generation of deadlock, and this brings very large challenge to the use of this high speed device of DDR.
At present, a large amount of electronic product such as computer, TV, mobile phone, display all uses DDR to be used as memory device, carries out read/write operation to process a large amount of audio-video signals by MCU (Micro Control Unit, micro-control unit) to DDR.To the write operation of DDR, the instruction write, Clock, DQ (data) and sending of DQS (Data Strobe, data gate) are all controlled by MCU, are easy to harmonious between signal, therefore, and the problem of seldom making a fault; But read operation will difficulty how, the instruction of reading and Clock are sent by MCU, but DQ and DQS is sent by DDR, MCU need receive DQ signal according to DQS signal, is difficult to harmonious (being difficult to keep identical phase place), adds the signal difference that PCB layout-design causes between signal, once phase deviation is excessive, just data can be caused to misplace thus cause receiving the data of mistake or cause loss of data, and then causing bad operating result, time serious, even can cause deadlock.When such as we use computer, TV, mobile phone in daily life, often can run into and crash and the problems such as display is abnormal.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of DDR adjustment method, occurs mistake to avoid MCU (Micro Control Unit, micro-control unit) to the read operation of DDR.
In addition, also provide a kind of DDR debug system, occur mistake to avoid the read operation of MCU to DDR.
A kind of DDR adjustment method, the method comprising the steps of: A, undertaken cumulative adjust data gate DQS phase place by particular value by the value of first buffer register Buffer 1, and record add up after the value of Buffer 1; B, analyze the duty of the Double Data Rate synchronous DRAM DDR after the adjustment of DQS phase place each time, when the DDR after DQS phase place adjustment is each time working properly, proceed to step C, during DDR operation irregularity after the adjustment of DQS phase place, proceed to step D; The value of C, successive adjustment second buffer register Buffer 2 adjusts data DQ phase place until the operation irregularity of DDR after the adjustment of DQ phase place, and record the value of the Buffer 2 after adjustment each time, during the operation irregularity of DDR after the adjustment of DQ phase place, proceed to steps A; D, from record the value of Buffer 1 and the value of Buffer 2 find out optimum value to arrange DDR.
Further, also comprised before steps A: the value of Buffer 1 is reset.
Further, the value of described successive adjustment second buffer register Buffer 2 adjusts DQ phase place until the step of operation irregularity of DDR after the adjustment of DQ phase place comprises: E1, the value of Buffer 2 reset; E2, the value of Buffer 2 to be adjusted by particular value; The duty of the DDR after E3, the adjustment of analysis DQ phase place; When E4, DDR working properly after the adjustment of DQ phase place, return step e 2, during the operation irregularity of the DDR after the adjustment of DQ phase place, return steps A.
Further, the value of described successive adjustment second buffer register Buffer 2 adjusts DQ phase place until the step of operation irregularity of DDR after the adjustment of DQ phase place comprises: F1, the value of Buffer 2 reset; F2, the value of Buffer 2 is undertaken cumulative to adjust DQ phase place by particular value; The duty of the DDR after F3, the adjustment of analysis DQ phase place; When F4, DDR working properly after the adjustment of DQ phase place, return step F 2, during the operation irregularity of the DDR after the adjustment of DQ phase place, proceed to step F 5; F5, the value of Buffer 2 to be reset; F6, the value of Buffer 2 is undertaken successively decreasing to adjust DQ phase place by particular value; The duty of the DDR after F7, the adjustment of analysis DQ phase place; When F8, DDR working properly after the adjustment of DQ phase place, return step F 6, during the operation irregularity of the DDR after the adjustment of DQ phase place, return execution steps A.
Further, find out optimum value and comprise to the step adjusting DDR the described value of Buffer 1 from record and the value of Buffer 2: the phase place generating DQS and DQ according to the value of all Buffer 1 of record and the value of Buffer 2 adjusts bivariate table; Bivariate table according to generating finds out the optimum value of Buffer 1 and the optimum value of Buffer2; According to the optimum value of the Buffer 1 found out and the optimum value of Buffer 2, DDR is set.
A kind of DDR debug system, this system comprises: DQS phase adjusting module, adjusts DQS phase place, and record the value of the Buffer 1 after adjustment for the value adjusting Buffer 1 when debugging and starting; DQ phase adjusting module, during for the DDR after the adjustment of DQS phase place each time working properly, the value of successive adjustment Buffer 2 adjusts data DQ phase place until the operation irregularity of DDR after the adjustment of DQ phase place, and the value of Buffer 2 after record adjustment each time; DDR adjusting module, during for the operation irregularity of DDR after the adjustment of DQS phase place, finds out optimum value to adjust DDR from the value of Buffer 1 and the value of Buffer 2 of record; Described DQS phase adjusting module, time also for the operation irregularity of DDR after the adjustment of DQ phase place, the value of adjustment Buffer 1 adjusts DQS phase place, and the value of Buffer 1 after record adjustment.
Further, described DQS phase adjusting module is also for resetting the value of Buffer 1.
Further, the value of described DQ phase adjusting module successive adjustment Buffer 2 adjusts data DQ phase place until the step of operation irregularity of DDR after the adjustment of DQ phase place comprises: the value of Buffer 2 reset; The value of Buffer 2 is adjusted by particular value; Analyze the duty of the DDR after the adjustment of DQ phase place; During DDR working properly after the adjustment of DQ phase place, the value of Buffer 2 is adjusted by particular value.
Further, the value of described DQ phase adjusting module successive adjustment Buffer 2 adjusts data DQ phase place until the step of operation irregularity of DDR after the adjustment of DQ phase place comprises: F1, the value of Buffer 2 reset; F2, the value of Buffer 2 is undertaken cumulative to adjust DQ phase place by particular value; The duty of the DDR after F3, the adjustment of analysis DQ phase place; When F4, DDR working properly after the adjustment of DQ phase place, return step F 2, during the operation irregularity of the DDR after the adjustment of DQ phase place, proceed to step F 5; F5, the value of Buffer 2 to be reset; F6, the value of Buffer 2 is undertaken successively decreasing to adjust DQ phase place by particular value; The duty of the DDR after F7, the adjustment of analysis DQ phase place; When F8, DDR working properly after the adjustment of DQ phase place, return step F 6.
Further, described DDR adjusting module is used for: the phase place adjustment bivariate table generating DQS and DQ according to the value of all Buffer 1 of record and the value of Buffer 2; Bivariate table according to generating finds out the optimum value of Buffer 1 and the optimum value of Buffer 2; According to the optimum value of Buffer 1 found out and the optimum value of Buffer2, DDR is set.
Compare prior art, the present invention adjusts DQS phase place by the value of successive adjustment Buffer 1, and the value of successive adjustment Buffer 2 adjusts data DQ phase place, and circulated by the adjustment that the duty of the DDR after the value of analysis and regulation Buffer 1 and the value of Buffer 2 builds DQS phase place and DQ phase place, and then find out the best operating point of DDR, ensure that the harmonious of DQS signal and DQ signal, when avoiding the read operation of MCU to DDR, occur mistake.
Accompanying drawing explanation
Fig. 1 is that micro-control unit carries out read operation exemplary plot to DDR.
Fig. 2 is that micro-control unit carries out write operation exemplary plot to DDR.
Fig. 3 is the functional block diagram of DDR debug system of the present invention preferred embodiment.
Fig. 4 is the phase place adjustment two-dimensional representation illustration of DQS and DQ.
Fig. 5 is the concrete implementing procedure figure of DDR adjustment method of the present invention preferred embodiment.
The realization of the object of the invention, functional characteristics and advantage will in conjunction with the embodiments, are described further with reference to accompanying drawing.
Embodiment
Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
As depicted in figs. 1 and 2, MCU (Micro Control Unit, micro-control unit) comprise Buffer1 (buffer register 1) and Buffer 2 (buffer register 2), MCU realizes the read-write operation to DDR (Double Data Rate Synchronous Dynamic Random Access Memory, Double Data Rate synchronous DRAM) by Buffer 1 and Buffer 2.MCU adjusts the phase place of DQS (Data Strobe, data gate) by the value adjusting Buffer1, and described DQS is used for the read-write operation of control data.MCU adjusts the phase place of DQ (Data, data) by the value adjusting Buffer 2.
As shown in Figure 3, be the functional block diagram of DDR debug system of the present invention preferred embodiment.This DDR debug system 10 runs in MCU, and this DDR debug system 10 comprises DQS phase adjusting module 100, DQ phase adjusting module 101 and DDR adjusting module 102.
This DQS phase adjusting module 100, for the value of Buffer 1 being reset, is undertaken adjusting by particular value by the value of Buffer 1 and the value of Buffer 1 after record adjustment each time, and analyze DQS phase place each time adjust after the duty of DDR.In the present embodiment, described particular value is 1; In other embodiments of the invention, described particular value can also be other any suitable values.In the present embodiment, the adjustment of the value of this DQS phase adjusting module 100 couples of Buffer 1 is cumulative.
This DQ phase adjusting module 101, during for the DDR after the adjustment of DQS phase place each time working properly, the value of Buffer 2 is reset, and the value of Buffer 2 is carried out successive adjustment by particular value until the operation irregularity of DDR after the adjustment of DQ phase place, the value of the Buffer 2 after record adjustment each time, and analyze the duty of the DDR after DQ phase place adjustment each time.In the present embodiment, described particular value is 1; In other embodiments of the invention, described particular value can also be other any suitable values.In the present embodiment, the once complete adjustment of the value of this DQ phase adjusting module 101 couples of Buffer 2 comprises cumulative and successively decreases.
This DQS phase adjusting module 100, during operation irregularity also for the DDR after the adjustment of DQ phase place each time, the value of Buffer 1 is undertaken adjusting by particular value and the value of Buffer 1 after recording adjustment each time, and analyze the duty of the DDR after DQS phase place adjustment each time.
This DDR adjusting module 102, during for the operation irregularity of DDR after the adjustment of DQS phase place, from the value of all Buffer 1 and the value of Buffer 2 of record, find out the optimum value of Buffer 1 and the optimum value of Buffer 2, DDR is set according to the optimum value of the Buffer 1 found out and the optimum value of Buffer 2.
In the present embodiment, this DDR adjusting module 102, during for the operation irregularity of DDR after the adjustment of DQS phase place, generate the phase place adjustment bivariate table of DQS and DQ according to the value of all Buffer 1 of record and the value of Buffer 2, the bivariate table according to generating finds out the optimum value of Buffer 1 and the optimum value of Buffer 2.Such as shown in Fig. 4, " F " represents DDR operation irregularity, and it is working properly that " 0 " represents DDR; This DDR adjusting module 102 chooses the optimum value of value as DQS phase place (tDQSCK) of the Buffer 1 of DDR working range the widest (that is: comprising the row that " 0 " is maximum) automatically, and the optimum value that can obtain DQS phase place (tDQSCK) from Fig. 4 is 6; This DDR adjusting module 102 is according to the optimum value of DQS phase place, automatically the optimum value (that is: comprising the tDQSQ value that the mid point of " 0 " maximum row is corresponding) of DQ phase place (tDQSQ) is obtained again, namely during tDQSCK=6, the intermediate value of tDQSQ is 0, i.e. optimum value tDQSQ=0, the best operating point of the DDR then found out is: tDQSCK=6, tDQSQ=0.
As shown in Figure 5, be the concrete implementing procedure figure of DDR adjustment method of the present invention preferred embodiment.
It is emphasized that: process flow diagram shown in Fig. 5 is only a preferred embodiment, those skilled in the art is when knowing, any embodiment built around inventive concept should not depart from the scope contained in following technical scheme:
A, adjust the value of first buffer register Buffer 1 to adjust data gate DQS phase place when debugging and starting, and the value of Buffer 1 after record adjustment; And B, Double Data Rate synchronous DRAM DDR after the adjustment of DQS phase place each time working properly time, the value of successive adjustment second buffer register Buffer 2 adjusts data DQ phase place until the operation irregularity of DDR after the adjustment of DQ phase place, and record the value of the Buffer2 after adjustment each time, during the operation irregularity of DDR after the adjustment of DQ phase place, proceed to steps A; When C, the operation irregularity of DDR after the adjustment of DQS phase place, from the value of Buffer 1 and the value of Buffer2 of record, find out optimum value to arrange DDR.
It is below the debugging progressively realizing DDR in conjunction with this preferred embodiment.
Step S10, the value of Buffer 1 resets by this DQS phase adjusting module 100, i.e. tDQSCK (0)=0.
The value of described Buffer 1 and the phase value one_to_one corresponding of DQS, in present embodiment, carry out the value of corresponding adjustment DQS phase place by the value adjusting described Buffer 1.
Step S11, the value of Buffer 1 is undertaken cumulative to adjust DQS phase place by this DQS phase adjusting module 100 by particular value, and records the value tDQSCK (n) of the Buffer 1 after adding up.In the present embodiment, described particular value is 1.
Step S12, this DQS phase adjusting module 100 analyzes the duty of the DDR after the adjustment of DQS phase place.
During DDR working properly after the adjustment of DQS phase place, proceed to and perform following step S13, during the operation irregularity of the DDR after the adjustment of DQS phase place, proceed to and perform following step S20 and S21.
Step S13, the value of Buffer2 resets by this DQ phase adjusting module 101, i.e. tDQSQ (0)=0.
Step S15, the value of Buffer 2 is undertaken cumulative to adjust DQ phase place by this DQ phase adjusting module 101 by particular value, and records the value tDQSQ (n) of the Buffer2 after adding up.
Step S16, this DQ phase adjusting module 101 analyzes the duty of the DDR after the adjustment of DQ phase place.
During DDR working properly after the adjustment of DQ phase place, return and perform above-mentioned steps S15, during the operation irregularity of the DDR after the adjustment of DQ phase place, proceed to and perform following step S17.
Step S17, the value of Buffer 2 resets by this DQ phase adjusting module 101.
Step S18, the value of Buffer 2 is undertaken successively decreasing to adjust DQ phase place by particular value by this DQ phase adjusting module 101, and records the value tDQSQ (n) of the Buffer2 after successively decreasing.
Step S19, this DQ phase adjusting module 101 analyzes the duty of the DDR after the adjustment of DQ phase place.
During DDR working properly after the adjustment of DQ phase place, return and perform above-mentioned steps S18, during the operation irregularity of the DDR after the adjustment of DQ phase place, return and perform following step S11.
Step S20, this DDR adjusting module 102 finds out the optimum value of Buffer 1 and the optimum value of Buffer 2 from the value of all Buffer 1 and the value of Buffer 2 of record.
In the present embodiment, during the operation irregularity of DDR of this DDR adjusting module 102 after the adjustment of DQS phase place, generate the phase place adjustment bivariate table of DQS and DQ according to the value of all Buffer 1 of record and the value of Buffer 2, the bivariate table according to generating finds out the optimum value of Buffer 1 and the optimum value of Buffer 2.Such as shown in Fig. 4, " F " represents DDR operation irregularity, and it is working properly that " 0 " represents DDR; This DDR adjusting module 102 chooses the optimum value of value as DQS phase place (tDQSCK) of the Buffer1 of DDR working range the widest (that is: comprising the row that " 0 " is maximum) automatically, and the optimum value that can obtain DQS phase place (tDQSCK) from Fig. 4 is 6; This DDR adjusting module 102 is according to the optimum value of DQS phase place, automatically the optimum value (that is: comprising the tDQSQ value that the mid point of " 0 " maximum row is corresponding) of DQ phase place (tDQSQ) is obtained again, namely during tDQSCK=6, the intermediate value of tDQSQ is 0, i.e. optimum value tDQSQ=0, the best operating point of the DDR then found out is: tDQSCK=6, tDQSQ=0.
Step S21, this DDR adjusting module 102 arranges DDR according to the optimum value of the Buffer 1 found out and the optimum value of Buffer 2.
These are only the preferred embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every utilize instructions of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (10)
1. a DDR adjustment method, is characterized in that, the method comprising the steps of:
A, the value of first buffer register Buffer 1 is undertaken cumulative adjust data gate DQS phase place by particular value, and record add up after the value of Buffer 1;
B, analyze the duty of the Double Data Rate synchronous DRAM DDR after the adjustment of DQS phase place each time, when the DDR after DQS phase place adjustment is each time working properly, proceed to step C, during DDR operation irregularity after the adjustment of DQS phase place, proceed to step D;
The value of C, successive adjustment second buffer register Buffer 2 adjusts data DQ phase place until the operation irregularity of DDR after the adjustment of DQ phase place, and record the value of the Buffer 2 after adjustment each time, during the operation irregularity of DDR after the adjustment of DQ phase place, proceed to steps A;
D, from record the value of Buffer 1 and the value of Buffer 2 find out optimum value to arrange DDR.
2. DDR adjustment method as claimed in claim 1, is characterized in that, also comprised before steps A:
The value of Buffer 1 is reset.
3. DDR adjustment method as claimed in claim 1, is characterized in that, the value of described successive adjustment second buffer register Buffer 2 adjusts DQ phase place until the step of operation irregularity of DDR after the adjustment of DQ phase place comprises:
E1, the value of Buffer 2 to be reset;
E2, the value of Buffer 2 to be adjusted by particular value;
The duty of the DDR after E3, the adjustment of analysis DQ phase place;
When E4, DDR working properly after the adjustment of DQ phase place, return step e 2, during the operation irregularity of the DDR after the adjustment of DQ phase place, return steps A.
4. DDR adjustment method as claimed in claim 3, is characterized in that, the value of described successive adjustment second buffer register Buffer 2 adjusts DQ phase place until the step of operation irregularity of DDR after the adjustment of DQ phase place comprises:
F1, the value of Buffer 2 to be reset;
F2, the value of Buffer 2 is undertaken cumulative to adjust DQ phase place by particular value;
The duty of the DDR after F3, the adjustment of analysis DQ phase place;
When F4, DDR working properly after the adjustment of DQ phase place, return step F 2, during the operation irregularity of the DDR after the adjustment of DQ phase place, proceed to step F 5;
F5, the value of Buffer 2 to be reset;
F6, the value of Buffer 2 is undertaken successively decreasing to adjust DQ phase place by particular value;
The duty of the DDR after F7, the adjustment of analysis DQ phase place;
When F8, DDR working properly after the adjustment of DQ phase place, return step F 6, during the operation irregularity of the DDR after the adjustment of DQ phase place, return execution steps A.
5. the DDR adjustment method as described in claim as arbitrary in Claims 1-4, is characterized in that, finds out optimum value and comprises to the step adjusting DDR the described value of Buffer 1 from record and the value of Buffer 2:
The phase place adjustment bivariate table of DQS and DQ is generated according to the value of all Buffer 1 of record and the value of Buffer 2;
Bivariate table according to generating finds out the optimum value of Buffer 1 and the optimum value of Buffer 2;
According to the optimum value of the Buffer 1 found out and the optimum value of Buffer 2, DDR is set.
6. a DDR debug system, is characterized in that, this system comprises:
DQS phase adjusting module, adjusts DQS phase place for the value adjusting Buffer 1 when debugging and starting, and records the value of the Buffer 1 after adjustment;
DQ phase adjusting module, during for the DDR after the adjustment of DQS phase place each time working properly, the value of successive adjustment Buffer 2 adjusts data DQ phase place until the operation irregularity of DDR after the adjustment of DQ phase place, and the value of Buffer 2 after record adjustment each time;
DDR adjusting module, during for the operation irregularity of DDR after the adjustment of DQS phase place, finds out optimum value to arrange DDR from the value of Buffer 1 and the value of Buffer 2 of record;
Described DQS phase adjusting module, time also for the operation irregularity of DDR after the adjustment of DQ phase place, the value of adjustment Buffer 1 adjusts DQS phase place, and the value of Buffer 1 after record adjustment.
7. DDR debug system as claimed in claim 6, it is characterized in that, described DQS phase adjusting module is also for resetting the value of Buffer 1.
8. DDR debug system as claimed in claim 6, is characterized in that, the value of described DQ phase adjusting module successive adjustment Buffer 2 adjusts data DQ phase place until the step of operation irregularity of DDR after the adjustment of DQ phase place comprises:
The value of Buffer 2 is reset;
The value of Buffer 2 is adjusted by particular value;
Analyze the duty of the DDR after the adjustment of DQ phase place;
During DDR working properly after the adjustment of DQ phase place, the value of Buffer 2 is adjusted by particular value.
9. DDR debug system as claimed in claim 8, is characterized in that, the value of described DQ phase adjusting module successive adjustment Buffer 2 adjusts data DQ phase place until the step of operation irregularity of DDR after the adjustment of DQ phase place comprises:
F1, the value of Buffer 2 to be reset;
F2, the value of Buffer 2 is undertaken cumulative to adjust DQ phase place by particular value;
The duty of the DDR after F3, the adjustment of analysis DQ phase place;
When F4, DDR working properly after the adjustment of DQ phase place, return step F 2, during the operation irregularity of the DDR after the adjustment of DQ phase place, proceed to step F 5;
F5, the value of Buffer 2 to be reset;
F6, the value of Buffer 2 is undertaken successively decreasing to adjust DQ phase place by particular value;
The duty of the DDR after F7, the adjustment of analysis DQ phase place;
When F8, DDR working properly after the adjustment of DQ phase place, return step F 6.
10. the DDR debug system as described in claim as arbitrary in claim 6 to 9, is characterized in that, described DDR adjusting module is used for:
The phase place adjustment bivariate table of DQS and DQ is generated according to the value of all Buffer 1 of record and the value of Buffer 2;
Bivariate table according to generating finds out the optimum value of Buffer 1 and the optimum value of Buffer 2;
According to the optimum value of the Buffer 1 found out and the optimum value of Buffer 2, DDR is set.
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| CN105701042B (en) * | 2016-03-02 | 2018-08-14 | 珠海全志科技股份有限公司 | The optimization method and system of Memory control interface signal quality |
| CN107463475B (en) * | 2016-06-06 | 2020-07-31 | 深圳市中兴微电子技术有限公司 | Chip and method for acquiring chip debugging data |
| CN109101384A (en) * | 2018-08-10 | 2018-12-28 | 晶晨半导体（深圳）有限公司 | The adjustment method and system of DDR module |
| CN111026589B (en) * | 2019-10-29 | 2023-08-11 | 晶晨半导体（深圳）有限公司 | Method for testing DDR memory stability through SOC |
| CN111858195A (en) * | 2020-06-10 | 2020-10-30 | 瑞芯微电子股份有限公司 | Interface parameter adapting method for DRAM interface read check and storage medium |
| CN112328441B (en) * | 2020-11-26 | 2022-09-27 | 展讯通信（上海）有限公司 | DDR debugging method and system, readable storage medium and electronic device |
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