CN103034572A - Method and system for debugging double data rate synchronous dynamic random access memory (DDR SDRAM) - Google Patents
Method and system for debugging double data rate synchronous dynamic random access memory (DDR SDRAM) Download PDFInfo
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Abstract
The invention provides a method for debugging a double data rate synchronous dynamic random access memory (DDR SDRAM). According to the method, a data stroke (DQS) phase is adjusted through gradually adjusting the value of a Buffer 1, a data (DQ) phase is adjusted through gradually adjusting the value of a Buffer 2, and an adjusting cycle of the DQS phase and an adjusting cycle of the DQ phase are constructed through analyzing the working condition of the DDR SDRAM after the value of the Buffer 1 and the value of the Buffer 2 are adjusted, and further, the best operating point of the DDR SDRAM is found out, so that a DQS signal and a DQ signal are harmonious, and the phenomenon that an error occurs when a read operation is performed on the DDR SDRAM by a micro control unit (MCU) is avoided. The invention also provides a system for debugging the DDR SDRAM.
Description
Technical field
The present invention relates to a kind of device debugging technique, particularly a kind of DDR adjustment method and system.
Background technology
The DDR full name is: DDR SDRAM(Double Data Rate Synchronous Dynamic Random Access Memory, Double Data Rate synchronous DRAM).Because of DDR read/write data speed higher, requirement to sequential and signal is also more and more higher, and on the other hand, because the requirement of cost, PCB(Printed Circuit Board, printed circuit board) size is more and more less, requirement to the PCB layout-design is also more and more higher, be difficult to accomplish that all differential signal cablings are isometric, therefore will produce the equal difference time delay between the signal, when time delay acquires a certain degree, can cause the read/write operation of DDR is occurred unsuccessfully, thereby cause the generation of crashing, and this use to this high speed device of DDR has brought very large challenge.
At present, a large amount of electronic products such as computer, TV, mobile phone, display all use DDR to be used as memory device, by MCU(Micro Control Unit, micro-control unit) DDR is carried out read/write operation process a large amount of audio-video signals.To the write operation of DDR, the instruction of writing, Clock, DQ(data) and DQS(Data Strobe, the data gate) send all by MCU control, be easy between the signal harmonious, therefore, the problem of seldom making a fault; But read operation will difficulty how, the instruction of reading and Clock are sent by MCU, but DQ and DQS are sent by DDR, MCU needs to receive the DQ signal according to the DQS signal, is difficult to harmonious (being difficult to the identical phase place of maintenance) between the signal, adds the signal difference that the PCB layout-design causes, once phase deviation is excessive, thereby just can cause data dislocation to cause receiving wrong data or causing loss of data, and then cause bad operating result, when serious even can cause deadlock.When using in daily life computer, TV, mobile phone such as us, often can run into deadlock and show the problems such as unusual.
Summary of the invention
Fundamental purpose of the present invention provides a kind of DDR adjustment method, to avoid MCU(Micro Control Unit, micro-control unit) mistake is appearred in the read operation of DDR.
In addition, also provide a kind of DDR debug system, to avoid MCU mistake is appearred in the read operation of DDR.
A kind of DDR adjustment method, the method comprising the steps of: A, the value of adjusting first buffer register Buffer 1 in when beginning debugging are adjusted data gate DQS phase place, and the value of the Buffer 1 of record after adjusting; B, analyze the duty of the Double Data Rate synchronous DRAM DDR after DQS phase place is each time adjusted, DDR after each time DQS phase place adjustment changes step C over to when working properly, perhaps, change step D during the DDR operation irregularity after the adjustment of DQS phase place over to; The value of C, second buffer register Buffer 2 of successive adjustment adjusts data DQ phase place until the operation irregularity of the DDR after the adjustment of DQ phase place, and the value of the Buffer 2 after the each time adjustment of record, during the operation irregularity of the DDR after the DQ phase place is adjusted, change steps A over to; D, from the value of the value of Buffer 1 of record and Buffer 2, find out optimum value DDR is set.
Further, before steps A, also comprise: with the value zero clearing of Buffer 1.
Further, the value of second buffer register Buffer 2 of described successive adjustment is adjusted the DQ phase place until the step of the operation irregularity of the DDR after the adjustment of DQ phase place comprises: E1, with the value zero clearing of Buffer 2; E2, the value of Buffer 2 is adjusted by particular value; The duty of DDR after E3, analysis DQ phase place are adjusted; During E4, the DDR after the DQ phase place is adjusted working properly, return step e 2, perhaps, during the operation irregularity of the DDR after the DQ phase place is adjusted, return steps A.
Further, the value of second buffer register Buffer 2 of described successive adjustment is adjusted the DQ phase place until the step of the operation irregularity of the DDR after the adjustment of DQ phase place comprises: F1, with the value zero clearing of Buffer 2; F2, the value of Buffer 2 is added up to adjust the DQ phase place by particular value; The duty of DDR after F3, analysis DQ phase place are adjusted; During F4, the DDR after the DQ phase place is adjusted working properly, return step F 2, perhaps, during the operation irregularity of the DDR after the DQ phase place is adjusted, change step F 5 over to; F5, with the value zero clearing of Buffer 2; F6, the value of Buffer 2 is successively decreased to adjust the DQ phase place by particular value; The duty of DDR after F7, analysis DQ phase place are adjusted; During F8, the DDR after the DQ phase place is adjusted working properly, return step F 6, perhaps, during the operation irregularity of the DDR after the DQ phase place is adjusted, return execution in step A.
Further, described from record the value of Buffer 1 and the value of Buffer 2 find out optimum value and adjust the step of DDR and comprise: the phase place adjustment bivariate table that generates DQS and DQ according to the value of the value of all Buffer 1 of record and Buffer 2; Find out the optimum value of Buffer 1 and the optimum value of Buffer 2 according to the bivariate table that generates; According to the optimum value of the Buffer 1 that finds out and the optimum value of Buffer 2 DDR is set.
A kind of DDR debug system, this system comprises: the DQS phase adjusting module, the value that is used for adjustment Buffer 1 when the debugging beginning is adjusted the DQS phase place, and records the value of the Buffer 1 after adjusting; The DQ phase adjusting module, when being used for DDR working properly after the DQS phase place is adjusted each time, the value of successive adjustment Buffer 2 adjusts data DQ phase place until the operation irregularity of the DDR of DQ phase place after adjusting, and the value of the Buffer 2 of record after adjusting each time; The DDR adjusting module when being used for the operation irregularity of the DDR after the DQS phase place is adjusted, being found out optimum value and is adjusted DDR from the value of the value of the Buffer 1 of record and Buffer 2; Described DQS phase adjusting module when also being used for the operation irregularity of the DDR after the DQ phase place is adjusted, being adjusted the value of Buffer 1 and is adjusted the DQS phase place, and the value of the Buffer 1 after the record adjustment.
Further, described DQS phase adjusting module also is used for the value zero clearing with Buffer 1.
Further, the value of described DQ phase adjusting module successive adjustment Buffer 2 is adjusted data DQ phase place until the step of the operation irregularity of the DDR after the adjustment of DQ phase place comprises: with the value zero clearing of Buffer 2; The value of Buffer 2 is adjusted by particular value; Analyze the duty of the DDR after the DQ phase place is adjusted; During the DDR after the DQ phase place is adjusted working properly, the value of Buffer 2 is adjusted by particular value.
Further, the value of described DQ phase adjusting module successive adjustment Buffer 2 is adjusted data DQ phase place until the step of the operation irregularity of the DDR after the adjustment of DQ phase place comprises: F1, with the value zero clearing of Buffer 2; F2, the value of Buffer 2 is added up to adjust the DQ phase place by particular value; The duty of DDR after F3, analysis DQ phase place are adjusted; During F4, the DDR after the DQ phase place is adjusted working properly, return step F 2, perhaps, during the operation irregularity of the DDR after the DQ phase place is adjusted, change step F 5 over to; F5, with the value zero clearing of Buffer 2; F6, the value of Buffer 2 is successively decreased to adjust the DQ phase place by particular value; The duty of DDR after F7, analysis DQ phase place are adjusted; During F8, the DDR after the DQ phase place is adjusted working properly, return step F 6.
Further, described DDR adjusting module is used for: according to value and the value generation DQS of Buffer 2 and the phase place adjustment bivariate table of DQ of all Buffer 1 that record; Find out the optimum value of Buffer 1 and the optimum value of Buffer 2 according to the bivariate table that generates; According to the optimum value of the Buffer 1 that finds out and the optimum value of Buffer 2 DDR is set.
Compare prior art, the present invention adjusts the DQS phase place by the value of successive adjustment Buffer 1, and the value of successive adjustment Buffer 2 is adjusted data DQ phase place, and the duty of the DDR after the value of the value by analysis and regulation Buffer 1 and Buffer 2 makes up the adjustment circulation of DQS phase place and DQ phase place, and then find out the best operating point of DDR, guarantee the harmonious of DQS signal and DQ signal, occurred mistake when having avoided MCU to the read operation of DDR.
Description of drawings
Fig. 1 is that micro-control unit carries out the read operation exemplary plot to DDR.
Fig. 2 is that micro-control unit carries out the write operation exemplary plot to DDR.
Fig. 3 is the functional block diagram of DDR debug system of the present invention preferred embodiment.
Fig. 4 is that the phase place of DQS and DQ is adjusted the two-dimensional representation illustration.
Fig. 5 is the implementation process flow diagram of DDR adjustment method of the present invention preferred embodiment.
The realization of the object of the invention, functional characteristics and advantage are described further with reference to accompanying drawing in connection with embodiment.
Embodiment
Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
As depicted in figs. 1 and 2, MCU(Micro Control Unit, micro-control unit) comprise Buffer 1(buffer register 1) and Buffer 2(buffer register 2), MCU realizes DDR(Double Data Rate Synchronous Dynamic Random Access Memory, Double Data Rate synchronous DRAM by Buffer 1 and Buffer 2) read-write operation.MCU adjusts DQS(Data Strobe, the data gate by the value of adjusting Buffer 1) phase place, described DQS is used for the read-write operation of control data.MCU adjusts DQ(Data, data by the value of adjusting Buffer 2) phase place.
As shown in Figure 3, be the functional block diagram of DDR debug system of the present invention preferred embodiment.This DDR debug system 10 runs among the MCU, and this DDR debug system 10 comprises DQS phase adjusting module 100, DQ phase adjusting module 101 and DDR adjusting module 102.
This DQS phase adjusting module 100 is used for the value zero clearing with Buffer 1, and the value of Buffer 1 is adjusted and record the value of the Buffer 1 after adjusting each time by particular value, and analyzes the duty of the DDR after the each time DQS phase place adjustment.In the present embodiment, described particular value is 1; In other embodiments of the invention, described particular value can also be other any suitable values.In the present embodiment, the adjustment of the value of 100 couples of Buffer 1 of this DQS phase adjusting module is cumulative.
This DQ phase adjusting module 101, when being used for DDR working properly after the DQS phase place is adjusted each time, value zero clearing with Buffer 2, and the value of Buffer 2 carried out successive adjustment by particular value until the operation irregularity of the DDR of DQ phase place after adjusting, record the value of the Buffer 2 after adjusting each time, and analyze the duty of the DDR after the each time DQ phase place adjustment.In the present embodiment, described particular value is 1; In other embodiments of the invention, described particular value can also be other any suitable values.In the present embodiment, the once complete adjustment of the value of 101 couples of Buffer 2 of this DQ phase adjusting module comprises cumulative and successively decreases.
This DQS phase adjusting module 100, when also being used for the operation irregularity of the DDR after the DQ phase place is adjusted each time, the value of Buffer 1 is adjusted and record the value of the Buffer 1 after adjusting each time by particular value, and analyze the duty of the DDR after the each time DQS phase place adjustment.
This DDR adjusting module 102, when being used for the operation irregularity of the DDR after the DQS phase place is adjusted, from the value of the value of all Buffer 1 of record and Buffer 2, find out the optimum value of Buffer 1 and the optimum value of Buffer 2, according to the optimum value of the Buffer 1 that finds out and the optimum value of Buffer 2 DDR is set.
In the present embodiment, this DDR adjusting module 102, when being used for the operation irregularity of the DDR after the DQS phase place is adjusted, according to value and the value generation DQS of Buffer 2 and the phase place adjustment bivariate table of DQ of all Buffer 1 that record, find out the optimum value of Buffer 1 and the optimum value of Buffer 2 according to the bivariate table that generates.For example shown in Figure 4, " F " represents the DDR operation irregularity, and it is working properly that " 0 " represents DDR; This DDR adjusting module 102 is chosen the value of Buffer 1 of DDR working range the widest (that is: comprising " 0 " maximum row) automatically as the optimum value of DQS phase place (tDQSCK), and the optimum value that can get DQS phase place (tDQSCK) from Fig. 4 is 6; This DDR adjusting module 102 is according to the optimum value of DQS phase place, automatically obtain again the optimum value (that is: tDQSQ value corresponding to mid point that comprises " 0 " maximum row) of DQ phase place (tDQSQ), when being tDQSCK=6, the intermediate value of tDQSQ is 0, be optimum value tDQSQ=0, the best operating point of the DDR that then finds out is: tDQSCK=6, tDQSQ=0.
As shown in Figure 5, be the implementation process flow diagram of DDR adjustment method of the present invention preferred embodiment.
It is emphasized that: process flow diagram shown in Figure 5 only is a preferred embodiment, and those skilled in the art is when knowing, any embodiment that makes up around inventive concept should not break away from the scope that contains in following technical scheme:
A, the value of adjusting first buffer register Buffer 1 in when beginning debugging are adjusted data gate DQS phase place, and the value of the Buffer 1 of record after adjusting; And during B, the Double Data Rate synchronous DRAM DDR after DQS phase place is each time adjusted working properly, the value of second buffer register Buffer 2 of successive adjustment adjusts data DQ phase place until the operation irregularity of the DDR after the adjustment of DQ phase place, and the value of the Buffer 2 after the each time adjustment of record, during the operation irregularity of the DDR after the DQ phase place is adjusted, change steps A over to; Perhaps during the operation irregularity of C, the DDR after the DQS phase place is adjusted, from the value of the value of the Buffer 1 of record and Buffer 2, find out optimum value DDR is set.
Below be progressively to realize debugging to DDR in conjunction with this preferred embodiment.
Step S10, this DQS phase adjusting module 100 is the value zero clearing of Buffer 1, i.e. tDQSCK (0)=0.
The value of described Buffer 1 is corresponding one by one with the phase value of DQS, in the present embodiment, comes the value of corresponding adjustment DQS phase place by the value of adjusting described Buffer 1.
Step S11, this DQS phase adjusting module 100 adds up to adjust the DQS phase place with the value of Buffer 1 by particular value, and records the value tDQSCK (n) of the Buffer 1 after adding up.In the present embodiment, described particular value is 1.
Step S12, this DQS phase adjusting module 100 is analyzed the duty of the DDR after the DQS phase place is adjusted.
During the DDR after the DQS phase place is adjusted working properly, change over to and carry out following step S13, perhaps, during the operation irregularity of the DDR after the DQS phase place is adjusted, change over to and carry out following step S20 and S21.
Step S13, this DQ phase adjusting module 101 is the value zero clearing of Buffer 2, i.e. tDQSQ (0)=0.
Step S15, this DQ phase adjusting module 101 adds up to adjust the DQ phase place with the value of Buffer 2 by particular value, and records the value tDQSQ (n) of the Buffer 2 after adding up.
Step S16, this DQ phase adjusting module 101 is analyzed the duty of the DDR after the DQ phase place is adjusted.
During the DDR after the DQ phase place is adjusted working properly, return and carry out above-mentioned steps S15, perhaps, during the operation irregularity of the DDR after the DQ phase place is adjusted, change over to and carry out following step S17.
Step S17, this DQ phase adjusting module 101 is with the value zero clearing of Buffer 2.
Step S18, this DQ phase adjusting module 101 successively decreases to adjust the DQ phase place with the value of Buffer 2 by particular value, and records the value tDQSQ (n) of the Buffer 2 after successively decreasing.
Step S19, this DQ phase adjusting module 101 is analyzed the duty of the DDR after the DQ phase place is adjusted.
During the DDR after the DQ phase place is adjusted working properly, return and carry out above-mentioned steps S18, perhaps, during the operation irregularity of the DDR after the DQ phase place is adjusted, return and carry out following step S11.
Step S20, this DDR adjusting module 102 is found out the optimum value of Buffer 1 and the optimum value of Buffer 2 from the value of the value of all Buffer 1 of record and Buffer 2.
In the present embodiment, during the operation irregularity of the DDR of this DDR adjusting module 102 after the DQS phase place is adjusted, according to value and the value generation DQS of Buffer 2 and the phase place adjustment bivariate table of DQ of all Buffer 1 that record, find out the optimum value of Buffer 1 and the optimum value of Buffer 2 according to the bivariate table that generates.For example shown in Figure 4, " F " represents the DDR operation irregularity, and it is working properly that " 0 " represents DDR; This DDR adjusting module 102 is chosen the value of Buffer 1 of DDR working range the widest (that is: comprising " 0 " maximum row) automatically as the optimum value of DQS phase place (tDQSCK), and the optimum value that can get DQS phase place (tDQSCK) from Fig. 4 is 6; This DDR adjusting module 102 is according to the optimum value of DQS phase place, automatically obtain again the optimum value (that is: tDQSQ value corresponding to mid point that comprises " 0 " maximum row) of DQ phase place (tDQSQ), when being tDQSCK=6, the intermediate value of tDQSQ is 0, be optimum value tDQSQ=0, the best operating point of the DDR that then finds out is: tDQSCK=6, tDQSQ=0.
Step S21, this DDR adjusting module 102 arranges DDR according to the optimum value of the Buffer 1 that finds out and the optimum value of Buffer 2.
Below only be the preferred embodiments of the present invention; be not so limit claim of the present invention; every equivalent structure or equivalent flow process conversion that utilizes instructions of the present invention and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (10)
1. DDR adjustment method is characterized in that the method comprising the steps of:
A, the value of adjusting first buffer register Buffer 1 in when beginning debugging are adjusted data gate DQS phase place, and the value of the Buffer 1 of record after adjusting;
B, analyze the duty of the Double Data Rate synchronous DRAM DDR after DQS phase place is each time adjusted, DDR after each time DQS phase place adjustment changes step C over to when working properly, perhaps, change step D during the DDR operation irregularity after the adjustment of DQS phase place over to;
The value of C, second buffer register Buffer 2 of successive adjustment adjusts data DQ phase place until the operation irregularity of the DDR after the adjustment of DQ phase place, and the value of the Buffer 2 after the each time adjustment of record, during the operation irregularity of the DDR after the DQ phase place is adjusted, change steps A over to;
D, from the value of the value of Buffer 1 of record and Buffer 2, find out optimum value DDR is set.
2. DDR adjustment method as claimed in claim 1 is characterized in that, also comprises before steps A:
Value zero clearing with Buffer 1.
3. DDR adjustment method as claimed in claim 1 is characterized in that, the value of second buffer register Buffer 2 of described successive adjustment is adjusted the DQ phase place until the step of the operation irregularity of the DDR after the adjustment of DQ phase place comprises:
E1, with the value zero clearing of Buffer 2;
E2, the value of Buffer 2 is adjusted by particular value;
The duty of DDR after E3, analysis DQ phase place are adjusted;
During E4, the DDR after the DQ phase place is adjusted working properly, return step e 2, perhaps, during the operation irregularity of the DDR after the DQ phase place is adjusted, return steps A.
4. DDR adjustment method as claimed in claim 3 is characterized in that, the value of second buffer register Buffer 2 of described successive adjustment is adjusted the DQ phase place until the step of the operation irregularity of the DDR after the adjustment of DQ phase place comprises:
F1, with the value zero clearing of Buffer 2;
F2, the value of Buffer 2 is added up to adjust the DQ phase place by particular value;
The duty of DDR after F3, analysis DQ phase place are adjusted;
During F4, the DDR after the DQ phase place is adjusted working properly, return step F 2, perhaps, during the operation irregularity of the DDR after the DQ phase place is adjusted, change step F 5 over to;
F5, with the value zero clearing of Buffer 2;
F6, the value of Buffer 2 is successively decreased to adjust the DQ phase place by particular value;
The duty of DDR after F7, analysis DQ phase place are adjusted;
During F8, the DDR after the DQ phase place is adjusted working properly, return step F 6, perhaps, during the operation irregularity of the DDR after the DQ phase place is adjusted, return execution in step A.
5. such as the described DDR adjustment method of the arbitrary claim of claim 1 to 4, it is characterized in that, described from record the value of Buffer 1 and the value of Buffer 2 find out optimum value and adjust the step of DDR and comprise:
Value and the value generation DQS of Buffer 2 and the phase place adjustment bivariate table of DQ according to all Buffer 1 that record;
Find out the optimum value of Buffer 1 and the optimum value of Buffer 2 according to the bivariate table that generates;
According to the optimum value of the Buffer 1 that finds out and the optimum value of Buffer 2 DDR is set.
6. a DDR debug system is characterized in that, this system comprises:
The DQS phase adjusting module, the value that is used for adjustment Buffer 1 when the debugging beginning is adjusted the DQS phase place, and records the value of the Buffer 1 after adjusting;
The DQ phase adjusting module, when being used for DDR working properly after the DQS phase place is adjusted each time, the value of successive adjustment Buffer 2 adjusts data DQ phase place until the operation irregularity of the DDR of DQ phase place after adjusting, and the value of the Buffer 2 of record after adjusting each time;
The DDR adjusting module when being used for the operation irregularity of the DDR after the DQS phase place is adjusted, being found out optimum value DDR is set from the value of the value of the Buffer 1 of record and Buffer 2;
Described DQS phase adjusting module when also being used for the operation irregularity of the DDR after the DQ phase place is adjusted, being adjusted the value of Buffer 1 and is adjusted the DQS phase place, and the value of the Buffer 1 after the record adjustment.
7. DDR debug system as claimed in claim 6 is characterized in that, described DQS phase adjusting module also is used for the value zero clearing with Buffer 1.
8. DDR debug system as claimed in claim 6 is characterized in that, the value of described DQ phase adjusting module successive adjustment Buffer 2 is adjusted data DQ phase place until the step of the operation irregularity of the DDR after the adjustment of DQ phase place comprises:
Value zero clearing with Buffer 2;
The value of Buffer 2 is adjusted by particular value;
Analyze the duty of the DDR after the DQ phase place is adjusted;
During the DDR after the DQ phase place is adjusted working properly, the value of Buffer 2 is adjusted by particular value.
9. DDR debug system as claimed in claim 8 is characterized in that, the value of described DQ phase adjusting module successive adjustment Buffer 2 is adjusted data DQ phase place until the step of the operation irregularity of the DDR after the adjustment of DQ phase place comprises:
F1, with the value zero clearing of Buffer 2;
F2, the value of Buffer 2 is added up to adjust the DQ phase place by particular value;
The duty of DDR after F3, analysis DQ phase place are adjusted;
During F4, the DDR after the DQ phase place is adjusted working properly, return step F 2, perhaps, during the operation irregularity of the DDR after the DQ phase place is adjusted, change step F 5 over to;
F5, with the value zero clearing of Buffer 2;
F6, the value of Buffer 2 is successively decreased to adjust the DQ phase place by particular value;
The duty of DDR after F7, analysis DQ phase place are adjusted;
During F8, the DDR after the DQ phase place is adjusted working properly, return step F 6.
10. such as the described DDR debug system of the arbitrary claim of claim 6 to 9, it is characterized in that described DDR adjusting module is used for:
Value and the value generation DQS of Buffer 2 and the phase place adjustment bivariate table of DQ according to all Buffer 1 that record;
Find out the optimum value of Buffer 1 and the optimum value of Buffer 2 according to the bivariate table that generates;
According to the optimum value of the Buffer 1 that finds out and the optimum value of Buffer 2 DDR is set.
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| CN111026589B (en) * | 2019-10-29 | 2023-08-11 | 晶晨半导体（深圳）有限公司 | Method for testing DDR memory stability through SOC |
| CN111858195A (en) * | 2020-06-10 | 2020-10-30 | 瑞芯微电子股份有限公司 | Interface parameter adapting method for DRAM interface read check and storage medium |
| CN112328441A (en) * | 2020-11-26 | 2021-02-05 | 展讯通信（上海）有限公司 | DDR debugging method and system, readable storage medium and electronic device |
| CN112328441B (en) * | 2020-11-26 | 2022-09-27 | 展讯通信（上海）有限公司 | DDR debugging method and system, readable storage medium and electronic device |
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