CN108182169B

CN108182169B - Method for realizing high-efficiency FFT in MTD filter

Info

Publication number: CN108182169B
Application number: CN201711363764.7A
Authority: CN
Inventors: 张建军; 乐立鹏; 安印龙; 闫昕; 马杰
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2017-12-18
Filing date: 2017-12-18
Publication date: 2021-06-08
Anticipated expiration: 2037-12-18
Also published as: CN108182169A

Abstract

A method for realizing high-efficiency FFT in an MTD filter relates to the field of radar digital signal processing; the method comprises the following steps: performing FFT operation on received data by adopting an FFT arithmetic unit, and outputting the data after the FFT operation to an on-chip storage management unit; step two, the on-chip memory management unit writes the calculated data into the off-chip memory according to the address sequence which is generated by the jump of the counter and used for accessing the off-chip memory; and step three, the on-chip memory management unit reads back data from the off-chip memory according to the form of the read-back data written in as required and the address sequence generated by the jump of the counter and used for accessing the off-chip memory or the address sequence generated by the jump of the counter and inverted sequence and successfully arranged, and sends the data to the FFT arithmetic unit. The invention saves the on-chip SRAM memory with the capacity of 8 multiplied by 2Mb, greatly reduces the chip design scale and the power consumption, and improves the chip reliability.

Description

Method for realizing high-efficiency FFT in MTD filter

Technical Field

The invention relates to the field of radar digital signal processing, in particular to a high-efficiency FFT implementation method in an MTD filter.

Background

FFT (fast Fourier transform) is a very important processing means in radar digital signal processing, and in a Moving Target Detection (MTD) clutter suppression technology which is widely applied at present, FFT is a core operation unit for rapidly and successfully detecting a target.

The work block diagram of the conventional way that the FFT processes the data comprises an FFT IP core and a data interface. The FFT IP core in the traditional mode comprises an FFT operation module and a reverse order memory, wherein after FFT operation is completed on input natural (reverse) order data, the reverse order data is inverted by the reverse order memory and then is output to an off-chip memory through a data interface, and the data interface only has a data transmission function. Although the FFT IP core in the traditional mode has high operation efficiency, the defects are as follows: when each frame of 32 Kx 64bit radar signal data is processed, in order to realize the function of the inverted sequence, a 2Mb inverted sequence memory is required to be configured in the chip, and when 8 FFTs are adopted to simultaneously process data, the capacity of the inverted sequence memory is expanded to 16Mb, so that the scale and the power consumption of the chip are sharply increased, and the reliability of the chip is greatly reduced.

Disclosure of Invention

The invention aims to overcome the defects in the prior art, and provides a method for realizing high-efficiency FFT in an MTD filter, which saves an on-chip SRAM memory with the capacity of 8 multiplied by 2Mb, greatly reduces the design scale and power consumption of a chip, and improves the reliability of the chip.

The above purpose of the invention is realized by the following technical scheme:

a method for realizing high-efficiency FFT in an MTD filter comprises the following steps:

performing FFT operation on received data by adopting an FFT arithmetic unit, and outputting the data after the FFT operation to an on-chip storage management unit;

step two, the on-chip memory management unit writes the calculated data into the off-chip memory according to the address sequence which is generated by the jump of the counter and used for accessing the off-chip memory;

and step three, the on-chip memory management unit reads back data from the off-chip memory according to the form of the read-back data written in as required and the address sequence generated by the jump of the counter and used for accessing the off-chip memory or the address sequence generated by the jump of the counter and inverted sequence and successfully arranged, and sends the data to the FFT arithmetic unit.

In the above method for implementing high-efficiency FFT in an MTD filter, in the step (one), the data includes natural-order data and inverted-order data; when the FFT arithmetic unit receives the natural sequence data, the inverted sequence data is generated after the FFT arithmetic unit carries out operation; when the FFT arithmetic unit receives the inverted sequence data, the natural sequence data is generated after the FFT arithmetic unit carries out operation.

In the above method for implementing high-efficiency FFT in an MTD filter, in the step (one), the operation capability of the FFT operator is 32K × 64 bits.

In the above method for implementing high-efficiency FFT in an MTD filter, in the step (two), the counter is represented as a row address, a bank address and a col address from high order to low order.

In the above method for implementing high-efficiency FFT in an MTD filter, in the step (three),

when the on-chip memory management unit needs to read back data from the off-chip memory according to the writing sequence, the data is read back and sent to the FFT arithmetic unit according to the address sequence which is generated by the jump of the counter and accesses the off-chip memory;

when the on-chip memory management unit needs to read back data from the off-chip memory according to the inverted sequence mode, the data are read back and sent to the FFT arithmetic unit according to the address sequence generated by the jump of the counter and used for accessing the off-chip memory after inverted sequence power arrangement.

In the above method for implementing high-efficiency FFT in an MTD filter, in the step (three), the method for performing the inverted sequence power arrangement on the address sequence accessing the off-chip memory generated by the counter jump includes: and exchanging the high and low bits of the address sequence for accessing the off-chip memory generated by the jump of the counter.

In the above method for implementing high-efficiency FFT in an MTD filter, in the step (three), the exchanged address sequences are a col address, a bank address, and a row address from the high order to the low order.

Compared with the prior art, the invention has the following advantages:

(1) the invention cancels a reverse order memory required after the traditional FFT operation in the MTD filter, saves the on-chip SRAM memory with the capacity of 8 multiplied by 2Mb, greatly reduces the chip design scale and the power consumption, and improves the chip reliability.

Drawings

FIG. 1 is a flow chart of an efficient FFT implementation of the present invention;

fig. 2 is a schematic block diagram of an efficient FFT implementation of the present invention.

Detailed Description

The invention is described in further detail below with reference to the following figures and specific examples:

the invention overcomes the defects of the prior art and provides a high-efficiency FFT implementation method in an MTD filter, for a 32K-point FFT IP core used in a Moving Target Detection (MTD) filter bank, an on-chip storage management unit (MMU) high-efficiency read-write control mode is utilized, data after FFT operation is firstly written into an off-chip memory out of order/in sequence, and then the data is read out of order/out of order as required. By adopting the method, the inverted sequence SRAM with the capacity of 2Mb in a single 32K-point FFT IP core (the maximum supports 8 FFTs, the on-chip SRAM with the capacity of 16Mb can be saved) can be saved, and the design scale and the power consumption can be effectively reduced.

As shown in fig. 1, which is a flowchart of a method for implementing an efficient FFT, it can be known that a method for implementing an efficient FFT in an MTD filter includes the following steps:

step (one), as shown in fig. 2, which is a schematic block diagram for implementing high-efficiency FFT, it can be known that an FFT operator is used to perform FFT operation on received data, and the calculated data is output to an on-chip storage management unit; the data comprises natural-order data and inverted-order data; when the FFT arithmetic unit receives the natural sequence data, the inverted sequence data is generated after the FFT arithmetic unit carries out operation; when the FFT arithmetic unit receives the inverted sequence data, the natural sequence data is generated after the FFT arithmetic unit carries out operation; the FFT operator has an arithmetic capability of 32K × 64 bits.

Step two, the on-chip memory management unit writes the calculated data into the off-chip memory according to the address sequence which is generated by the jump of the counter and used for accessing the off-chip memory; the counters are represented from high order to low order as row address, bank address and col address, respectively.

The method for carrying out the inverted sequence power arrangement on the address sequence generated by the jump of the counter and used for accessing the off-chip memory comprises the following steps: and exchanging the high and low bits of the address sequence for accessing the off-chip memory generated by the jump of the counter. The exchanged address sequences are respectively a col address, a bank address and a row address from high order to low order.

Meanwhile, in order to solve the problem that the access conflict of activating the bank next time is caused by insufficient precharging time after the same bank access operation, high and low bits of a row address and a bank address are locally exchanged.

Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.

Claims

1. A method for realizing high-efficiency FFT in an MTD filter is characterized in that: the method comprises the following steps:

performing FFT operation on received data by adopting an FFT arithmetic unit, and outputting the data after the FFT operation to an on-chip storage management unit; the operation capacity of the FFT operator is 32 Kx 64 bits;

thirdly, the on-chip memory management unit reads back data from the off-chip memory and sends the data to the FFT arithmetic unit according to the form of the read-back data written in by the need and the address sequence generated by the jump of the counter and used for accessing the off-chip memory or the address sequence generated by the jump of the counter and inverted sequence order successfully arranged;

2. The method of claim 1, wherein the method comprises: in the step (one), the data includes natural order data and inverted order data; when the FFT arithmetic unit receives the natural sequence data, the inverted sequence data is generated after the FFT arithmetic unit carries out operation; when the FFT arithmetic unit receives the inverted sequence data, the natural sequence data is generated after the FFT arithmetic unit carries out operation.

3. The method of claim 2, wherein the method comprises: in the step (two), the counter is respectively expressed as a row address, a bank address and a col address from high order to low order.

4. The method of claim 3, wherein the method comprises: in the step (three), the method for performing the inverted sequence power arrangement on the address sequence generated by the jump of the counter and used for accessing the off-chip memory comprises the following steps: and exchanging the high and low bits of the address sequence for accessing the off-chip memory generated by the jump of the counter.

5. The method of claim 4, wherein the method comprises: in the step (three), the exchanged address sequences are respectively a col address, a bank address and a row address from high order to low order.