CN112328441B - DDR debugging method and system, readable storage medium and electronic device - Google Patents
DDR debugging method and system, readable storage medium and electronic device Download PDFInfo
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- CN112328441B CN112328441B CN202011349030.5A CN202011349030A CN112328441B CN 112328441 B CN112328441 B CN 112328441B CN 202011349030 A CN202011349030 A CN 202011349030A CN 112328441 B CN112328441 B CN 112328441B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Abstract
A DDR debugging method and system, a readable storage medium and an electronic device are provided. The DDR controller runs in a DDR controller of the system on chip and is directly connected with the DDR through a DDR physical layer interface of the system on chip; the method comprises at least one of the following: after a read operation debugging instruction is sent to the DDR, receiving a data signal and a data strobe signal output by the DDR for multiple times to obtain a DDR eye diagram corresponding to a read operation, and obtaining an optimal read operation reference voltage value and an optimal read operation phase value based on the DDR eye diagram corresponding to the read operation; after a write operation debugging instruction is sent to the DDR, a data signal and a data strobe signal are sent to the DDR for multiple times, a DDR eye diagram corresponding to write operation is obtained, and an optimal write operation reference voltage value and an optimal write operation phase value are obtained based on the DDR eye diagram corresponding to write operation. By applying the scheme, the debugging efficiency of the DDR can be improved.
Description
Technical Field
The invention relates to the technical field of random access memories, in particular to a DDR debugging method and system, a readable storage medium and electronic equipment.
Background
Existing portable devices typically include a System-on-a-chip (SoC). A so-called system-on-chip is a complete system integrated on a single chip.
On a system on chip, there are typically included: multiple memory clients embedded on a single chip substrate. The memory client may be: a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), and the like. Memory clients may read and write Data from external Dynamic Random Access Memory (DRAM) electrically coupled to the system on chip via a high speed bus, such as a Double Data Rate (DDR) bus. A Dynamic Random Access Memory (DDR SDRAM) for reading and writing Data through a Double Data Rate bus is called a DDR SDRAM.
In order to avoid an error in read operation or write operation of the DDR, before formal read operation or write operation is performed on the DDR, the DDR needs to be debugged to obtain related parameters for data transmission, and subsequently, when formal read operation or write operation is performed on the DDR, data transmission can be performed according to the related parameters obtained by debugging.
When the DDR is debugged, the DDR is debugged mostly in a hardware mode, and the debugging efficiency is low.
Disclosure of Invention
The invention aims to solve the problems that: how to improve the debugging efficiency of DDR.
In order to solve the above problem, an embodiment of the present invention provides a DDR debugging method, which runs in a DDR controller of a system on chip, where the DDR controller is directly connected to a DDR through a DDR physical layer interface of the system on chip; the method comprises at least one of the following: after a read operation debugging instruction is sent to the DDR, receiving a data signal and a data strobe signal output by the DDR for multiple times to obtain a DDR eye diagram corresponding to a read operation, and obtaining an optimal read operation reference voltage value and an optimal read operation phase value based on the DDR eye diagram corresponding to the read operation; after a write operation debugging instruction is sent to the DDR, a data signal and a data strobe signal are sent to the DDR for multiple times, a DDR eye diagram corresponding to write operation is obtained, and an optimal write operation reference voltage value and an optimal write operation phase value are obtained based on the DDR eye diagram corresponding to write operation.
Optionally, after receiving the data signal and the data strobe signal output by the DDR each time, obtaining a DDR eye diagram corresponding to the read operation by using the following method: based on the received data signal and the data strobe signal, obtaining a corresponding DDR read operation scanning result by utilizing a read operation reference voltage debugging value and a read operation phase debugging value which are obtained in advance under a preset scanning frequency point; and obtaining DDR read operation scanning results corresponding to the read operation phase debugging values of the preset scanning frequency points under different read operation reference voltage debugging values, and generating DDR eye diagrams corresponding to the read operations.
Optionally, the obtaining, based on the received data signal and the data strobe signal, a corresponding DDR read operation scanning result by using a read operation reference voltage debug value and a read operation phase debug value at a preset scanning frequency point, where the read operation reference voltage debug value and the read operation phase debug value are obtained in advance, includes: acquiring a read operation reference voltage debugging value and a read operation phase debugging value under the preset scanning frequency point; performing phase adjustment on at least one of a data signal and a data strobe signal output by the DDR based on the read operation phase debug value; and after the phase adjustment, performing DDR scanning based on the read operation reference voltage debugging value to obtain a corresponding DDR read operation scanning result.
Optionally, after the phase adjustment, performing DDR scanning based on the reference voltage debug value includes: sampling the data signal output by the DDR by using the data strobe signal after phase adjustment to obtain a first data sampling result signal, and comparing the first data sampling result signal with the read operation reference voltage debugging value to obtain a corresponding DDR scanning result; or, sampling the data signal after phase adjustment by using the data strobe signal output by the DDR to obtain a second data sampling result signal, and comparing the second data sampling result signal with the read operation reference voltage debugging value to obtain a corresponding DDR scanning result; or, sampling the data signal after phase adjustment by using the data strobe signal output by the DDR to obtain a second data sampling result signal, and comparing the second data sampling result signal with the read operation reference voltage debug value to obtain a corresponding DDR scanning result.
Optionally, after sending the data signal and the data strobe signal to the DDR each time, obtaining a DDR eye corresponding to the write operation by using the following method: sending a data signal and a data strobe signal to the DDR by using a write operation phase debugging value under a preset scanning frequency point which is acquired in advance; acquiring a data signal and a data strobe signal from the DDR, and obtaining a corresponding DDR read operation scanning result by using a write operation reference voltage debugging value under the preset scanning frequency point; and obtaining DDR write operation scanning results corresponding to the write operation phase debugging values of the preset scanning frequency points under different write operation reference voltage debugging values, and generating a DDR eye diagram corresponding to the write operation.
Optionally, the sending a data signal and a data strobe signal to the DDR by using a write operation phase debug value at a preset scanning frequency point obtained in advance includes: and performing phase adjustment on at least one of the data signal to be written and the data strobe signal based on the write operation phase debugging value, and then sending the data signal to the DDR.
Optionally, the receiving the data signal and the data strobe signal output by the DDR, and obtaining a corresponding DDR write operation scanning result by using the write operation reference voltage debug value at the preset scanning frequency point includes: and sampling the acquired data signal by using the acquired data strobe signal to obtain a fourth sampling result signal, and comparing the voltage of the fourth sampling result signal with the write operation reference voltage debugging value to obtain a corresponding DDR write operation scanning result.
An embodiment of the present invention provides a DDR debug system, including: the DDR controller is positioned in the system on chip and is directly connected with the DDR through a DDR physical layer interface of the system on chip; the DDR controller comprises at least one of: the read operation debugging unit is suitable for receiving the data signal and the data strobe signal output by the DDR for multiple times after sending a read operation debugging instruction to the DDR to obtain a DDR eye diagram corresponding to read operation, and obtaining an optimal read operation reference voltage value and an optimal read operation phase value based on the DDR eye diagram corresponding to the read operation; and the write operation debugging unit is suitable for sending a data signal and a data strobe signal to the DDR for multiple times after sending a write operation debugging instruction to the DDR to obtain a DDR eye pattern corresponding to write operation, and obtaining an optimal write operation reference voltage value and an optimal write operation phase value based on the DDR eye pattern corresponding to the write operation.
Optionally, the read operation debugging unit includes: the read operation scanning subunit is suitable for obtaining a corresponding DDR read operation scanning result by utilizing a read operation reference voltage debugging value and a read operation phase debugging value under a preset scanning frequency point which are obtained in advance based on the received data signal and the data strobe signal; and the read operation eye pattern generating subunit is suitable for acquiring DDR read operation scanning results corresponding to the read operation phase debugging values of the preset scanning frequency point under different read operation reference voltage debugging values, and generating a DDR eye pattern corresponding to the read operation.
Optionally, the read operation scanning subunit includes: the acquisition module is suitable for acquiring a read operation reference voltage debugging value and a read operation phase debugging value under the preset scanning frequency point; the phase adjusting module is suitable for adjusting the phase of at least one of the data signal and the data strobe signal output by the DDR based on the read operation phase debugging value; and the scanning module is suitable for performing DDR scanning based on the read operation reference voltage debugging value after phase adjustment to obtain a corresponding DDR read operation scanning result.
Optionally, the system further comprises: the first register is suitable for storing a plurality of read operation reference voltage debugging values under the preset scanning frequency point; and the second register is suitable for storing a plurality of read operation phase debugging values under the preset scanning frequency point.
Optionally, the scanning module is adapted to sample the data signal output by the DDR by using the data strobe signal after phase adjustment to obtain a first data sampling result signal, and compare the first data sampling result signal with the read operation reference voltage debug value to obtain a corresponding DDR scanning result; or, sampling the data signal after phase adjustment by using the data strobe signal output by the DDR to obtain a second data sampling result signal, and comparing the second data sampling result signal with the read operation reference voltage debugging value to obtain a corresponding DDR scanning result; or sampling the data signal after the phase adjustment by using the data strobe signal after the phase adjustment to obtain a third data sampling result signal, and comparing the third data sampling result signal with the read operation reference voltage debugging value to obtain a corresponding DDR scanning result.
Optionally, the write operation debugging unit includes:
the write operation scanning subunit is suitable for sending a data signal and a data strobe signal to the DDR by using a write operation phase debugging value under a preset scanning frequency point acquired in advance; receiving a data signal and a data strobe signal output by the DDR, and obtaining a corresponding DDR read operation scanning result by using a write operation reference voltage debugging value under the preset scanning frequency point;
and the write operation eye pattern generating subunit is suitable for acquiring DDR write operation scanning results corresponding to the write operation phase debugging values of the preset scanning frequency point under different write operation reference voltage debugging values, and generating the DDR eye pattern corresponding to the write operation.
Optionally, the write operation scanning subunit is adapted to perform phase adjustment on at least one of a data signal to be written and a data strobe signal based on the write operation phase debug value, and then send the data signal to the DDR.
Optionally, the write operation scanning subunit is adapted to sample the acquired data signal by using the acquired data strobe signal to obtain a fourth sampling result signal, and compare a voltage of the fourth sampling result signal with the write operation reference voltage debug value to obtain a corresponding DDR write operation scanning result.
Optionally, the system further comprises: the third register is suitable for storing a plurality of write operation reference voltage debugging values under the preset scanning frequency point; and the fourth register is suitable for storing a plurality of write operation phase debugging values under the preset scanning frequency point.
Embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the steps of any one of the methods described above.
An embodiment of the present invention further provides an electronic device, which includes a memory and a processor, where the memory stores a computer program capable of running on the processor, and the processor executes any of the steps of the method when running the computer program.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
by applying the scheme of the invention, the DDR controller is directly connected with the DDR through the DDR physical layer interface of the system on chip, and further, the read operation debugging and the write operation debugging can be carried out on the DDR in a software mode to obtain the corresponding eye pattern, the optimal parameter value can be obtained based on the eye pattern, and compared with the method of debugging the DDR in a hardware mode, a transfer board does not need to be welded between the DDR and the system on chip, so that the debugging efficiency can be improved. Moreover, because the DDR controller is connected with the DDR through the DDR physical layer interface of the system on chip, a signal received by the DDR controller is a signal after passing through the DDR physical layer interface of the system on chip, namely a signal actually received inside the system on chip, and therefore based on an eye diagram obtained by the DDR controller, the actual data transmission condition of the DDR and the system on chip can be reflected more truly, and the debugging accuracy is improved.
Drawings
FIG. 1 is a schematic structural diagram of a DDR debug system in an embodiment of the present invention;
FIG. 2 is a flowchart of a DDR debugging method in an embodiment of the invention;
FIG. 3 is a schematic diagram of a phase adjustment for a data strobe signal according to an embodiment of the present invention;
FIG. 4 is a timing diagram illustrating phase adjustment of data strobe signals according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a DDR eye for a read operation in an embodiment of the invention;
FIG. 6 is a diagram illustrating a DDR debug process according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a DDR controller according to an embodiment of the present invention.
Detailed Description
At present, DDR is debugged mostly in a hardware mode. Specifically, an adapter board (interposer) is provided, and a certain memory client of the system on chip is soldered to the adapter board, and pins of the memory client correspond to and are consistent with pins of the adapter board. And connecting the adapter plate with the DDR, and further measuring signals of corresponding pins of the adapter plate.
In the hardware testing mode, a great amount of time is required for preparing the adapter board, so that the debugging efficiency is low, and generally more than 2 hours are required for completing the debugging of the DDR. Moreover, the signal obtained by measuring the corresponding pin of the transfer board is the signal of the external input/output pin of the system on chip, and other interferences also exist when the signal of the external input/output pin of the system on chip is actually input into the system on chip, so that the test result of the signal of the external input/output pin of the system on chip cannot ensure that the signal received by the system on chip is correct, and only can reflect whether the signal input into the system on chip conforms to the protocol specification or not
In view of the above problems, an embodiment of the present invention provides a DDR debugging method, where the method is performed in a DDR controller of a system on chip, and the DDR controller is directly connected to a DDR through a DDR physical layer interface of the system on chip, and sends a corresponding debugging instruction to the DDR, so as to receive a signal output by the DDR or send a signal to the DDR, thereby implementing debugging of the DDR in a software manner, greatly shortening the time required for debugging the entire DDR, and improving the debugging efficiency. Moreover, the signal received by the DDR controller is a signal passing through a DDR physical layer interface of the system on chip, and the actual data transmission condition of the DDR and the system on chip can be accurately reflected.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1, an embodiment of the present invention provides a DDR debug system 10, where the DDR debug system 10 may include: the DDR controller 101. The DDR controller 101 is located in the system-on-chip 20. The system on chip 20 has a DDR physical layer interface 201. The DDR controller 101 is directly connected to the DDR30 through a DDR physical layer interface 201.
In an embodiment of the present invention, the system-on-chip 20 may be implemented in any of the following devices: personal computers, workstations, servers, laptops, game consoles, and Portable Computing Devices (PCDs) such as cellular phones, smart phones, Portable Digital Assistants (PDAs), portable game consoles, navigation devices, tablets, fitness computers, and wearable devices (e.g., sports watches, fitness tracking devices, etc.) or other battery-powered devices with wireless connections or links.
The system-on-chip 20 may include one or more memory clients such as a Central Processing Unit (CPU), a graphics processing unit, a digital signal processor, static random access memory, read only memory, and the like. For simplicity of illustration, in fig. 1, only the central processing unit 202 is shown. The DDR controller 101 is electrically coupled to the various memory clients of the system-on-chip 20 via the SoC bus 203 to debug the DDR30 prior to data transfers by the DDR30 with the various memory clients.
The system-on-chip 20 and the DDR30 transmit and receive data using the data strobe signal DQS and the data signal DQ. The signal receiving end samples the data signal DQ at the transition edge of the data strobe signal DQS, and then the actually transmitted data can be obtained. Wherein the transition edge of the data strobe signal DQS includes a rising edge and a falling edge.
As shown in fig. 2, the embodiment of the present invention provides a DDR debugging method, which runs in the DDR controller 101 (shown in fig. 1) of the system on chip 20. By the method, at least one of read operation debugging and write operation debugging can be performed on the DDR.
Specifically, when performing read operation debugging on the DDR, the method may include the following steps:
and step 21, after sending a read operation debugging instruction to the DDR, receiving the data signal and the data strobe signal output by the DDR for multiple times to obtain a DDR eye diagram corresponding to a read operation, and obtaining an optimal read operation reference voltage value and an optimal read operation phase value based on the DDR eye diagram corresponding to the read operation.
The following describes a specific read operation debugging with reference to fig. 1 and fig. 2:
as shown in fig. 1, the DDR controller 101 may send a read debug instruction to the DDR 30. The DDR30, upon receiving the read debug command, sends a data signal DQ and a data strobe signal DQs to the system on chip 20.
After receiving the data signal DQ and the data strobe signal DQs output by the DDR30 each time, the read operation reference voltage debug value and the read operation phase debug value at the preset scanning frequency point, which are obtained in advance, may be used to obtain the corresponding DDR read operation scanning result based on the received data signal DQ and the data strobe signal DQs. And generating a DDR eye diagram corresponding to the read operation by acquiring DDR read operation scanning results corresponding to the read operation phase debugging values of the preset scanning frequency points under different read operation reference voltage debugging values.
In an implementation, the DDR controller 101 may obtain the read operation reference voltage debug value and the read operation phase debug value in various ways, which is not limited herein.
In an embodiment of the invention, as shown in fig. 1, the DDR debug system 10 may include a first register 102 and a second register 103. The first register 102 is adapted to store a plurality of read operation reference voltage debug values at the preset scanning frequency point. The second register 103 is adapted to store a plurality of read operation phase debug values at the preset scanning frequency point.
After receiving the data signal DQ and the data strobe signal DQs output by the DDR30 each time, the DDR controller 101 may obtain a plurality of read operation reference voltage debug values at the preset scanning frequency point from the first register 102, and obtain a plurality of read operation phase debug values at the preset scanning frequency point from the second register 103.
It should be noted that, the first register 102 stores not only the read operation reference voltage debug value that enables the DDR30 to normally operate, but also the read operation reference voltage debug value that enables the DDR30 not to normally operate, so that the finally generated DDR eye diagram has a clearer edge. The number of the read operation reference voltage debugging values can be set according to actual requirements.
Similarly, the second register 103 stores not only the read phase debug value enabling the DDR30 to operate normally, but also the read phase debug value disabling the DDR30 to operate normally, so that the finally generated DDR eye diagram has a clearer edge. The number of the read operation phase debugging values can be set according to actual requirements.
And acquiring a read operation phase debugging value, and performing phase adjustment on at least one of a data signal DQ and a data strobe signal DQS output by the DDR.
In a specific implementation, the data strobe signal after the phase adjustment may be used to sample the data signal output by the DDR to obtain a first data sampling result signal, and the first data sampling result signal is compared with the read operation reference voltage debug value to obtain a corresponding DDR scanning result. The data strobe signal output by the DDR can also be used to sample the phase-adjusted data signal to obtain a second data sampling result signal, and the second data sampling result signal is compared with the read operation reference voltage debug value to obtain a corresponding DDR scanning result. The data strobe signal after phase adjustment can be used for sampling the data signal after phase adjustment to obtain a third data sampling result signal, and the third data sampling result signal is compared with the read operation reference voltage debugging value to obtain a corresponding DDR scanning result.
Taking the example of performing phase adjustment on the data strobe signal DQS instead of performing phase adjustment on the data signal DQ, referring to fig. 3, the system on chip generally includes a plurality of delays 203, and the delays 203 can perform different delay processes on the input digital signal to change the phase of the input digital signal. For example, referring to fig. 4, the data strobe signal DQS is processed with different delays to obtain the phase-adjusted data strobe signals DQS1 and DQS2, where a rising edge of the data strobe signal DQS1 corresponds to a position of the data signal DQ at time t1, and a rising edge of the data strobe signal DQS2 corresponds to a position of the data signal DQ at time t 2.
The DDR physical layer interface 201 may include a plurality of D flip-flops, such as D flip-flops 31 to 34. The D flip-flops 31 to 34 are coupled to each other. The data signal DQ from the DDR30 can be connected to the data terminal D of the D flip-flop 31. The data strobe signal DQS sent by the DDR30 may be connected to the control terminals of the D flip- flops 31 and 32 through the corresponding delay 203 under the control of the DDR controller, so as to implement phase adjustment.
The D flip- flops 31 and 32 sample the data signal DW under the control of the phase-adjusted data strobe signal, and output corresponding signals to the D flip- flops 33 and 34 at the output terminals Q. The D flip- flops 33 and 34 output the signal sampled by the output terminal Q to the DDR controller under the control of the Local clock signal clk.
Referring to fig. 1, after the phase adjustment, the DDR controller 101 performs DDR scanning based on the read operation reference voltage debug value to obtain a corresponding DDR read operation scanning result, that is, compares a signal output by the DDR physical layer interface 201 with the read operation reference voltage debug value to determine a read value. If the read value is equal to the actual written value, the DDR scan result appears as a small black dot in fig. 5, and if the read value is equal to the actual written non-value, the DDR scan result appears as a white dot in fig. 5.
The DDR scanning results are respectively in one-to-one correspondence with the read operation reference voltage debugging values and the read operation phase debugging values. That is, for any read operation reference voltage debug value, there are different DDR scan results at different read operation phase debug values. For any read operation phase debugging value, under different read operation reference voltage debugging values, different DDR scanning results are obtained. And superposing DDR scanning results corresponding to different read operation phase debugging values under different read operation reference voltage debugging values to obtain a final read operation DDR eye diagram, wherein the final read operation DDR eye diagram is shown in FIG. 5.
After obtaining a DDR eye pattern corresponding to a read operation, selecting a middle position at the widest position of a DDR reference voltage range, taking a read operation reference voltage debugging value corresponding to the middle position as an optimal read operation reference voltage value of the DDR, taking a read operation phase debugging value corresponding to the middle position as an optimal read operation phase value of the DDR, and executing subsequent read operations according to the optimal read operation reference voltage value and the optimal read operation phase value. In addition, the timing redundancy (margin) of the DDR can be determined based on the DDR eye diagram corresponding to the reading operation, and the voltage and temperature range of the system in stable operation can be judged based on the timing redundancy of the DDR.
Referring to fig. 2, when performing write operation debugging on a DDR by using the DDR debugging method in the embodiment of the present invention, the method may include the following steps:
and step 22, after sending a write operation debugging instruction to the DDR, sending a data signal and a data strobe signal to the DDR for multiple times to obtain a DDR eye diagram corresponding to a write operation, and obtaining an optimal write operation reference voltage value and an optimal write operation phase value based on the DDR eye diagram corresponding to the write operation.
The following describes a specific write operation debugging with reference to fig. 1 and fig. 2:
as shown in fig. 1, the DDR controller 101 may send a write debug instruction to the DDR 30. After receiving the write debug command, the DDR30 waits to receive the data signal DQ and the data strobe signal DQs sent by the system on chip 20.
After the DDR controller 101 sends a write operation debugging instruction to the DDR30, the DDR controller may send a data signal DQ and a data strobe signal DQs to the DDR by using a write operation phase debugging value at a preset scanning frequency point acquired in advance.
Specifically, the DDR controller 101 may perform phase adjustment on at least one of a data signal to be written and a data strobe signal based on the write operation phase debug value, and then send the adjusted data signal and the adjusted data strobe signal to the DDR. That is, at least one of the data signal DQ and the data strobe signal DQs transmitted to the DDR30 is transmitted after being phase-adjusted.
In a specific implementation, the data signal to be written may be phase-adjusted only and then sent to the DDR30 along with the data strobe signal DQS that is not phase-adjusted. The data strobe signal to be written may be phase-adjusted only and then transmitted to the DDR30 together with the data signal DQ that is not phase-adjusted. The data signal to be written and the data strobe signal may be phase-adjusted and then sent to the DDR 30.
In a specific implementation, the DDR controller 101 may control a signal that needs to be phase-adjusted, and output the signal to the DDR30 after the phase adjustment is performed by a corresponding delay.
The DDR30 receives signals sent by the system on chip 10 to implement data writing. After the data writing is completed, the DDR controller 101 reads the written data from the DDR30, that is, obtains a data signal and a data strobe signal, and further obtains a corresponding DDR read operation scanning result by using the write operation reference voltage debug value at the preset scanning frequency point.
Specifically, the obtained data strobe signal may be utilized to sample the obtained data signal to obtain a fourth sampling result signal, and a voltage of the fourth sampling result signal is compared with the write operation reference voltage debug value to obtain a corresponding DDR write operation scanning result.
When the read value after writing is not equal to the actually written value, the DDR write operation scan result appears white on the eye diagram.
Through obtaining DDR write operation scanning results corresponding to the write operation phase debugging values of the preset scanning frequency points under different write operation reference voltage debugging values, DDR eye diagrams corresponding to the write operations can be generated
And the DDR write operation scanning result corresponds to the write operation reference voltage debugging value and the write operation phase debugging value one to one respectively. That is, for any write operation reference voltage debug value, there is a different DDR write operation scan result at a different write operation phase debug value. For any write operation phase debugging value, under different write operation reference voltage debugging values, different DDR write operation scanning results are obtained. And overlapping DDR write operation scanning results corresponding to different write operation phase debugging values under different write operation reference voltage debugging values to obtain a final write operation DDR eye diagram.
After obtaining the DDR eye pattern corresponding to the write operation, selecting a middle position at the widest position of the DDR reference voltage range, taking a write operation reference voltage debugging value corresponding to the middle position as an optimal write operation reference voltage value of the DDR, taking a write operation phase debugging value corresponding to the middle position as an optimal read operation phase value of the DDR, and executing subsequent write operation according to the optimal write operation reference voltage value and the optimal write operation phase value.
In a specific implementation, referring to fig. 1, the DDR debug system 10 may further include: a third register 104 and a fourth register 105.
The third register 104 is adapted to store a plurality of write operation reference voltage debug values at a preset scanning frequency point. The fourth register 105 is adapted to store a plurality of write operation phase debugging values at a preset scanning frequency point. The DDR controller 101 may obtain the corresponding write operation reference voltage debug value and write operation phase debug value from the third register 104 and the fourth register 105.
It should be noted that, the third register 104 stores not only the write operation reference voltage debug value that enables the DDR30 to normally operate, but also the write operation reference voltage debug value that enables the DDR30 not to normally operate, so that the finally generated DDR eye diagram has a clearer edge. The number of the write operation reference voltage debugging values can be set according to actual requirements.
Similarly, the fourth register 105 stores not only the write phase debug value enabling the DDR30 to operate normally, but also the write phase debug value disabling the DDR30 to operate normally, so that the finally generated DDR eye diagram has a clearer edge. The number of the write operation phase debugging values can be set according to actual requirements.
Of course, the DDR controller 101 may also obtain the corresponding write operation reference voltage debug value and the write operation phase debug value by other methods.
It should be noted that, in a specific implementation, as shown in fig. 1, the execution sequence of steps 21 and 22 is not limited, that is, step 21, i.e., debugging the read operation of the DDR, may be executed first, and then step 22, i.e., debugging the write operation of the DDR is executed. Step 22 may be performed first, and then step 21 may be performed, which is not limited herein. No matter in which order steps 21 and 22 are performed, no limitation is made to the present invention and the present invention is within the scope of the present invention.
The DDR debug method can be implemented with reference to fig. 6. FIG. 6 is described in detail below:
referring to fig. 6, the DDR debug process may include the steps of:
and step 61, starting up initialization.
And the boot initialization is the boot initialization of the device where the system on chip is located.
Namely, the preset scanning frequency point is configured, and the preset scanning frequency point determines the period of the data signal DQ and the data strobe signal DQs. And controlling the frequency of data transmission between the DDR and the system on chip by configuring the preset scanning frequency point.
In a specific implementation, the DDR controller receives the scan operation configuration and further debugs the corresponding operation. The operation requiring scanning may be a read operation or a write operation.
And step 64, adjusting DDR parameters.
That is, the reference voltage debug value and the phase debug value corresponding to the preset scanning frequency point under the configured operation are obtained.
And step 65, debugging the DDR to obtain a DDR scanning result.
And debugging the DDR by using the acquired DDR parameters. The DDR parameters include: a reference voltage debug value and a phase debug value.
For example, when the scan operation is configured as a read operation, the DDR controller sends a read operation debug instruction and performs subsequent read operation debugging. When the scanning operation is configured to be the writing operation, the DDR controller sends a writing operation debugging instruction and conducts subsequent writing operation debugging.
For a specific DDR debug procedure, reference may be made to the above description regarding step 21 or step 22, and details are not described here.
And step 66, judging whether the DDR parameter adjustment is finished.
And when the DDR scanning results of different phase debugging values under the reference voltage debugging values are obtained, finishing DDR parameter adjustment, otherwise, not finishing DDR parameter adjustment.
And when the DDR parameter is adjusted, executing the step 67, otherwise, continuously executing the step 64, namely, adjusting the DDR parameter again until the DDR scanning results of the debugging values of different phases under the debugging values of the reference voltages are obtained.
And step 67, outputting the DDR eye pattern.
When all scan operations have been debugged, the debugging process is ended, otherwise steps 63 to 68 are performed again until all scan operations have been debugged.
For example, when a read operation is debugged first, if a write operation is not debugged, steps 63 to 68 are executed to debug the write operation of the DDR. When the write operation is debugged first, if the read operation is not debugged, steps 63 to 68 are executed to debug the read operation of the DDR.
As can be seen from the above, in the DDR debugging method in the embodiment of the present invention, different delay devices are used to continuously adjust the phases of the data strobe signal DQS and/or the data signal DQ under different reference voltages to scan the data of the data signal DQ sampled by the data strobe signal DQS, and finally, a complete eye diagram is superimposed, and the finally obtained eye diagram can reflect the time sequence redundancy of the system on chip and the DDR particles in the actual working state. The whole debugging process only needs to allow a corresponding program, the obtained eye diagram is a software eye diagram, and DDR scanning of the software eye diagram basically only needs a software engineer to participate. For different hardware, only relevant versions need to be downloaded, and the hardware can be directly used without being modified, so that the operation is simple, and the large-scale use can be realized.
The following detailed description of the system and computer-readable storage medium, corresponding methods, is provided to enable those skilled in the art to better understand and implement the present invention.
Referring to fig. 1, an embodiment of the present invention provides a DDR debugging system 10, where the DDR debugging system 10 may include a DDR controller 101, the DDR controller 101 is located in a system on chip, and the DDR controller 101 is directly connected to a DDR30 through a DDR physical layer interface 201 of the system on chip 20.
Fig. 7 is a schematic structural diagram of a DDR controller 101 according to an embodiment of the present invention. Referring to fig. 7, the DDR controller 101 may include at least one of a read operation debugging unit 71 and a write operation debugging unit 72. Wherein:
the read operation debugging unit 71 is adapted to receive the data signal and the data strobe signal output by the DDR for multiple times after sending the read operation debugging instruction to the DDR, obtain a DDR eye diagram corresponding to a read operation, and obtain an optimal read operation reference voltage value and an optimal read operation phase value based on the DDR eye diagram corresponding to the read operation;
the write operation debugging unit 72 is adapted to send a data signal and a data strobe signal to the DDR for multiple times after sending a write operation debugging instruction to the DDR, obtain a DDR eye diagram corresponding to a write operation, and obtain an optimal write operation reference voltage value and an optimal write operation phase value based on the DDR eye diagram corresponding to the write operation.
In an embodiment of the present invention, the read operation debugging unit 71 may include: a read operation scanning subunit 711 and a read operation eye pattern generating subunit 712. Wherein:
the read operation scanning subunit 711 is adapted to obtain a corresponding DDR read operation scanning result by using a read operation reference voltage debugging value and a read operation phase debugging value at a preset scanning frequency point, which are obtained in advance, based on the received data signal and the data strobe signal;
the read operation eye pattern generating subunit 712 is adapted to obtain DDR read operation scanning results corresponding to the read operation phase debugging values of the preset scanning frequency point under different read operation reference voltage debugging values, and generate a DDR eye pattern corresponding to the read operation.
In an embodiment of the present invention, the read operation scanning subunit 711 may include: an acquisition module 711a, a phase adjustment module 711b, and a scanning module 711 c. Wherein:
the obtaining module 711a is adapted to obtain a read operation reference voltage debugging value and a read operation phase debugging value at the preset scanning frequency point;
the phase adjustment module 711b is adapted to perform phase adjustment on at least one of a data signal and a data strobe signal output by the DDR based on the read operation phase debug value;
the scanning module 711c is adapted to perform DDR scanning based on the read operation reference voltage debug value after phase adjustment, so as to obtain a corresponding DDR read operation scanning result.
In an embodiment of the present invention, the scanning module 711c is adapted to sample the data signal output by the DDR by using the data strobe signal after phase adjustment to obtain a first data sampling result signal, and compare the first data sampling result signal with the read operation reference voltage debug value to obtain a corresponding DDR scanning result; or, sampling the data signal after phase adjustment by using the data strobe signal output by the DDR to obtain a second data sampling result signal, and comparing the second data sampling result signal with the read operation reference voltage debugging value to obtain a corresponding DDR scanning result; or sampling the data signal after the phase adjustment by using the data strobe signal after the phase adjustment to obtain a third data sampling result signal, and comparing the third data sampling result signal with the read operation reference voltage debugging value to obtain a corresponding DDR scanning result.
In an embodiment of the present invention, the write operation debugging unit 72 may include: a write operation scanning subunit 721 and a write operation eye diagram generating subunit 722. Wherein:
the write operation scanning subunit 721 is adapted to send a data signal and a data strobe signal to the DDR by using a write operation phase debug value at a preset scanning frequency point obtained in advance; receiving a data signal and a data strobe signal output by the DDR, and obtaining a corresponding DDR read operation scanning result by using a write operation reference voltage debugging value under the preset scanning frequency point;
the write operation eye pattern generating subunit 722 is adapted to obtain a DDR write operation scanning result corresponding to each write operation phase debugging value of the preset scanning frequency point under different write operation reference voltage debugging values, and generate a DDR eye pattern corresponding to the write operation.
In an embodiment of the invention, the write operation scanning subunit 721 is adapted to perform phase adjustment on at least one of a data signal to be written and a data strobe signal based on the write operation phase debug value, and then send the adjusted data signal to the DDR.
In an embodiment of the present invention, the write operation scanning subunit 721 is adapted to sample the acquired data signal by using the acquired data strobe signal to obtain a fourth sampling result signal, and compare a voltage of the fourth sampling result signal with the write operation reference voltage debug value to obtain a corresponding DDR write operation scanning result.
In an embodiment of the present invention, referring to fig. 1, the DDR debug system 10 may further include:
the first register 102 is suitable for storing a plurality of read operation reference voltage debugging values under the preset scanning frequency point;
and the second register 103 is adapted to store a plurality of read operation phase debugging values at the preset scanning frequency point.
In an embodiment of the present invention, referring to fig. 1, the DDR debug system 10 may further include:
a third register 104 adapted to store a plurality of write operation reference voltage debug values at a preset scanning frequency point;
and a fourth register 105 adapted to store a plurality of write operation phase debugging values at the preset scanning frequency point.
For each functional module in the DDR debug system 10, the description of the corresponding method may be specifically referred to for implementation, and is not repeated here.
The embodiment of the present invention further provides another computer-readable storage medium, where a computer instruction is stored, and when the computer instruction runs, any step of the DDR debugging method in the foregoing embodiments is executed, which is not described in detail again.
In particular implementations, the computer-readable storage medium may include: ROM, RAM, magnetic or optical disks, and the like.
An embodiment of the present invention further provides an electronic device, where the electronic device may include a memory and a processor, where the memory stores a computer program capable of running on the processor, and the processor executes the steps of the method in the foregoing embodiments when running the computer program.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A DDR debugging method is characterized in that a DDR controller running in a system on chip is directly connected with a DDR through a DDR physical layer interface of the system on chip; the method comprises at least one of the following:
after a read operation debugging instruction is sent to the DDR, receiving a data signal and a data strobe signal output by the DDR for multiple times to obtain a DDR eye diagram corresponding to a read operation, and obtaining an optimal read operation reference voltage value and an optimal read operation phase value based on the DDR eye diagram corresponding to the read operation;
after a write operation debugging instruction is sent to the DDR, a data signal and a data strobe signal are sent to the DDR for multiple times to obtain a DDR eye diagram corresponding to write operation, and an optimal write operation reference voltage value and an optimal write operation phase value are obtained based on the DDR eye diagram corresponding to write operation;
after receiving the data signal and the data strobe signal output by the DDR every time, obtaining a DDR eye pattern corresponding to the read operation by adopting the following method: based on the received data signal and the data strobe signal, obtaining a corresponding DDR read operation scanning result by utilizing a read operation reference voltage debugging value and a read operation phase debugging value which are obtained in advance under a preset scanning frequency point; obtaining DDR read operation scanning results corresponding to the read operation phase debugging values of the preset scanning frequency points under different read operation reference voltage debugging values, and generating DDR eye diagrams corresponding to the read operations;
after a data signal and a data strobe signal are sent to the DDR every time, a DDR eye pattern corresponding to the write operation is obtained by adopting the following method: sending a data signal and a data strobe signal to the DDR by using a write operation phase debugging value under a preset scanning frequency point which is acquired in advance; acquiring a data signal and a data strobe signal from the DDR, and obtaining a corresponding DDR write operation scanning result by using the write operation reference voltage debugging value under the preset scanning frequency point; and obtaining DDR write operation scanning results corresponding to the write operation phase debugging values of the preset scanning frequency points under different write operation reference voltage debugging values, and generating a DDR eye diagram corresponding to the write operation.
2. The DDR debugging method of claim 1, wherein the obtaining of the corresponding DDR read scan result based on the received data signal and data strobe signal using a read reference voltage debug value and a read phase debug value at a preset scan frequency point obtained in advance comprises:
acquiring a read operation reference voltage debugging value and a read operation phase debugging value under the preset scanning frequency point;
performing phase adjustment on at least one of a data signal and a data strobe signal output by the DDR based on the read operation phase debugging value;
and after phase adjustment, performing DDR scanning based on the read operation reference voltage debugging value to obtain a corresponding DDR read operation scanning result.
3. The DDR debug method of claim 2, wherein performing DDR scanning based on said reference voltage debug value after said phase adjustment comprises:
sampling the data signal output by the DDR by using the data strobe signal after phase adjustment to obtain a first data sampling result signal, and comparing the first data sampling result signal with the read operation reference voltage debugging value to obtain a corresponding DDR scanning result;
or, sampling the data signal after phase adjustment by using the data strobe signal output by the DDR to obtain a second data sampling result signal, and comparing the second data sampling result signal with the read operation reference voltage debugging value to obtain a corresponding DDR scanning result;
or sampling the data signal after the phase adjustment by using the data strobe signal after the phase adjustment to obtain a third data sampling result signal, and comparing the third data sampling result signal with the read operation reference voltage debugging value to obtain a corresponding DDR scanning result.
4. The DDR debugging method of claim 1, wherein the sending of the data signal and the data strobe signal to the DDR with the pre-obtained write operation phase debugging value at the preset scanning frequency point comprises:
and performing phase adjustment on at least one of the data signal to be written and the data strobe signal based on the write operation phase debugging value, and then sending the data signal to the DDR.
5. The DDR debugging method of claim 1, wherein the receiving the data signal and the data strobe signal output by the DDR, and obtaining the corresponding DDR write operation scan result using the write operation reference voltage debug value at the preset scanning frequency point comprises:
and sampling the acquired data signal by using the acquired data strobe signal to obtain a fourth sampling result signal, and comparing the voltage of the fourth sampling result signal with the write operation reference voltage debugging value to obtain a corresponding DDR write operation scanning result.
6. A DDR debug system, comprising: the DDR controller is positioned in a system on chip and is characterized in that the DDR controller is directly connected with a DDR through a DDR physical layer interface of the system on chip; the DDR controller comprises at least one of:
the read operation debugging unit is suitable for receiving the data signal and the data strobe signal output by the DDR for multiple times after sending a read operation debugging instruction to the DDR to obtain a DDR eye diagram corresponding to read operation, and obtaining an optimal read operation reference voltage value and an optimal read operation phase value based on the DDR eye diagram corresponding to the read operation;
the write operation debugging unit is suitable for sending a data signal and a data strobe signal to the DDR for multiple times after sending a write operation debugging instruction to the DDR to obtain a DDR eye diagram corresponding to write operation, and obtaining an optimal write operation reference voltage value and an optimal write operation phase value based on the DDR eye diagram corresponding to write operation;
the read operation debugging unit includes: the read operation scanning subunit is suitable for obtaining a corresponding DDR read operation scanning result by utilizing a read operation reference voltage debugging value and a read operation phase debugging value under a preset scanning frequency point which are obtained in advance based on the received data signal and the data strobe signal; the read operation eye pattern generating subunit is suitable for acquiring DDR read operation scanning results corresponding to read operation phase debugging values of the preset scanning frequency point under different read operation reference voltage debugging values, and generating a DDR eye pattern corresponding to the read operation;
the write operation debugging unit includes: the write operation scanning subunit is suitable for sending a data signal and a data gating signal to the DDR by using a write operation phase debugging value under a preset scanning frequency point which is acquired in advance; receiving a data signal and a data strobe signal output by the DDR, and obtaining a corresponding DDR write operation scanning result by using a write operation reference voltage debugging value under the preset scanning frequency point; and the write operation eye pattern generating subunit is suitable for acquiring DDR write operation scanning results corresponding to the write operation phase debugging values of the preset scanning frequency point under different write operation reference voltage debugging values, and generating the DDR eye pattern corresponding to the write operation.
7. The DDR debug system of claim 6, wherein the read operation scan subunit comprises:
the acquisition module is suitable for acquiring a read operation reference voltage debugging value and a read operation phase debugging value under the preset scanning frequency point;
the phase adjusting module is suitable for adjusting the phase of at least one of the data signal and the data strobe signal output by the DDR based on the read operation phase debugging value;
and the scanning module is suitable for performing DDR scanning based on the read operation reference voltage debugging value after phase adjustment to obtain a corresponding DDR read operation scanning result.
8. The DDR debug system of claim 7, further comprising:
the first register is suitable for storing a plurality of read operation reference voltage debugging values under the preset scanning frequency point;
and the second register is suitable for storing a plurality of read operation phase debugging values under the preset scanning frequency point.
9. The DDR debug system of claim 7, wherein the scan module is adapted to sample the data signals output by the DDR with the phase-adjusted data strobe signals to obtain first data sampling result signals, and compare the first data sampling result signals with the read operation reference voltage debug value to obtain corresponding DDR scan results; or, sampling the data signal after phase adjustment by using the data strobe signal output by the DDR to obtain a second data sampling result signal, and comparing the second data sampling result signal with the read operation reference voltage debugging value to obtain a corresponding DDR scanning result; or sampling the data signal after the phase adjustment by using the data strobe signal after the phase adjustment to obtain a third data sampling result signal, and comparing the third data sampling result signal with the read operation reference voltage debugging value to obtain a corresponding DDR scanning result.
10. The DDR debug system of claim 6 wherein the write operation scan subunit is adapted to phase adjust at least one of a data signal and a data strobe signal to be written to the DDR based on the write operation phase debug value.
11. The DDR debugging system of claim 6, wherein the write scan subunit is adapted to sample the obtained data signal with the obtained data strobe signal to obtain a fourth sampling result signal, and compare a voltage of the fourth sampling result signal with the write reference voltage debugging value to obtain a corresponding DDR write scan result.
12. The DDR debug system of claim 6, further comprising:
the third register is suitable for storing a plurality of write operation reference voltage debugging values under the preset scanning frequency point;
and the fourth register is suitable for storing a plurality of write operation phase debugging values under the preset scanning frequency point.
13. A computer-readable storage medium, on which a computer program is stored, which computer program is executable by a processor for carrying out the steps of the method according to any one of claims 1 to 5.
14. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program operable on the processor, wherein the processor, when executing the computer program, performs the steps of the method of any of claims 1 to 5.
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| CN114530185B (en) * | 2022-01-18 | 2023-04-07 | 深圳市晶存科技有限公司 | Eye pattern testing method, system, equipment and medium |
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