JP5919918B2 - Memory control apparatus and mask timing control method - Google Patents

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to source-synchronous data reception, and in particular, a read data reception circuit for a memory circuit such as a DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random Access Memory) (hereinafter referred to as DDR-SDRAM). And a mask timing control method for a mask signal for controlling a strobe signal for fetching read data of a memory circuit.

  The DDR-SDRAM performs a write operation and a read operation using a bidirectional data bus and a strobe signal. During the read operation, the strobe signal is output from a high impedance state (hereinafter referred to as Hi-Z state) through a state called a preamble, and a plurality of necessary sets of strobe edges (rising and falling) are output as necessary, Finally, the state returns to Hi-Z through a state called postamble. The read data receiving circuit needs to detect the preamble state and capture the edge of the strobe signal necessary for data reception as a clock.

  For example, Patent Document 1 provides a snapshot data training method for determining the optimum timing of the DQS enable signal in a single read operation. Here, the gray code count sequence is first written to the memory and then read out in a single burst. The controller samples the read burst at regular intervals from the time when the command is issued, and determines the circulation delay. A simple truth table search determines the optimal DQS enable timing for normal reading. During a normal read operation, the first positive edge of the enabled DQS signal is preferably used to sample the enabled counter each time a command is issued. If the counter sample changes, this indicates that a timing variation has occurred, but the DQS enable signal can be adjusted to correct the variation and keep it in the center of the DQS preamble.

  Further, in Patent Document 2, a dummy read command for delay adjustment is issued to the memory for the purpose of determining the timing for taking in the strobe signal, and a preamble period using the data signal and data strobe signal output from the memory. A circuit configuration for adjusting the timing of detecting data and taking in data is disclosed.

  However, the conventional means for capturing the strobe signal is assumed to be performed during the initialization sequence of the memory, and the preamble period is affected by the voltage / temperature change caused by the operation of the device. When it fluctuates, there is a problem that the strobe signal cannot be captured in the read period.

  Also in Patent Document 2, when the preamble period fluctuates due to the voltage / temperature change generated by the operation of the device, the problem of capturing the strobe signal in the read period cannot be solved.

  An object of the present invention is to solve the above problems, and a memory control device that can capture a strobe signal during a memory read period even when a preamble period detected during memory initialization fluctuates during memory operation, and It is an object to provide a mask timing control method for a mask signal for controlling a strobe signal.

A memory control device according to a first aspect of the present invention is a synchronous memory control for controlling so that data read from a memory circuit is received in synchronization with a strobe signal generated from the memory circuit during a period other than the memory read period. In the device
A mask signal generating circuit for generating a mask signal; and a plurality of delay elements connected in cascade with each other, the mask signal being sequentially delayed by the plurality of delay elements, and a delay corresponding to the number of stages of the plurality of delay elements A mask generating circuit for generating a mask signal having a plurality of timings of an amount;
A timing measurement circuit for detecting the mask signal at a plurality of predetermined timings using a signal obtained by ANDing the strobe signal with the mask signal, and outputting data composed of the detected plurality of detection data When,
During operation of the memory circuit, data indicating the data output from the upper Symbol timing measurement circuit, each comparison result is compared with a predetermined expected value of the predetermined expected value and H period the L period of the mask signal A comparison circuit that outputs
And a correction control circuit for correcting the change timing of the mask signal based on data from the comparison circuit during the operation of the memory circuit .

According to a second aspect of the present invention, there is provided a mask timing control method for a memory control device, wherein data read from a memory circuit is received in synchronization with a strobe signal generated from the memory circuit other than a memory read period. In a mask timing control method for a synchronous memory control device to be controlled,
The memory control device
A mask signal generating circuit for generating a mask signal; and a plurality of delay elements connected in cascade with each other, the mask signal being sequentially delayed by the plurality of delay elements, and a delay corresponding to the number of stages of the plurality of delay elements A mask generating circuit for generating a mask signal having a plurality of timings of an amount;
A timing measurement circuit for detecting the mask signal at a plurality of predetermined timings using a signal obtained by ANDing the strobe signal with the mask signal, and outputting data composed of the detected plurality of detection data And
The mask timing control method is as follows:
During the operation of the memory circuit, data output from the timing measurement circuit is compared with a predetermined expected value for the L period and a predetermined expected value for the H period of the mask signal, and data indicating each comparison result is obtained. Output step;
And correcting the change timing of the mask signal based on the data indicating the comparison results during the operation of the memory circuit .

  Therefore, according to the present invention, the fluctuation of the preamble period during the memory operation is detected and the timing for capturing the strobe signal is corrected. Therefore, even if the preamble period detected at the time of memory initialization changes during the memory operation, A strobe signal can be captured only during the period.

1 is a block diagram showing a configuration of a memory control system including a memory control device 1 according to an embodiment of the present invention. 3 is a timing chart showing timing for taking in a strobe signal DQS in the memory control device 1 of FIG. 1. FIG. 2 is a circuit diagram showing a configuration of a timing measurement circuit 13 in FIG. 1. 4 is a timing chart of each signal showing the operation of the timing measurement circuit 13 of FIG. 3. FIG. 2 is a circuit diagram illustrating a configuration of a mask generation circuit 11 in FIG. 1. FIG. 2 is a diagram for explaining operations of an L period comparator 18 and an H period comparator 17 in FIG. 1. 3 is a timing chart of each signal showing the operation of the correction control circuit 19 of FIG. 1. It is a block diagram which shows the structure of the correction control circuit 19 which concerns on a modification.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  FIG. 1 is a block diagram showing a configuration of a memory control system including a memory control device 1 according to an embodiment of the present invention. The memory control device 1 includes a timing correction circuit 10, and the timing correction circuit 10 always monitors the L period of the preamble and the H period after the preamble during the memory read period in the process of capturing the strobe signal in the memory read period, A flag is set when the ratio between the low level bell period (hereinafter referred to as L period) and the high level period (hereinafter referred to as H period) exceeds a predetermined value, and a strobe signal is captured during a period when no memory read occurs. It is characterized by correcting and changing the timing.

  In FIG. 1, the memory control device 1 writes data to the SDRAM 2 together with a command control circuit 20 that generates a clock and other memory control signals for a DDR-SDRAM (hereinafter referred to as SDRAM) 2 in a source synchronous manner. Alternatively, it controls the reading of data from the SDRAM 2. The internal clock CLK is input to the command control circuit 20 and the memory control device 1, and a control signal from, for example, a CPU (not shown; may be an internal controller) of an external controller is used as the command control circuit 20 and the memory control device 1. It is input to the mask generation circuit 11 and the like. When the command control circuit 20 issues a read command for reading data based on the control signal from the CPU, the command control circuit 20 supplies the mask generation circuit 11 with a timing corresponding to a specific latency (corresponding to the CL value of the SDRAM 2). On the other hand, a trigger signal TRI for generating the mask signal MSK is generated and output to the mask generating circuit 11. The command control circuit 20 generates a memory clock and outputs it to the SDRAM 2, and generates other memory control signals and outputs them to the SDRAM 2.

  The strobe signals DQS and DQSB from the SDRAM 2 become only the strobe signal DQS via the signal buffer 15 and are input to the first edge detection circuit 14 and the read data control circuit 21 via the mask AND gate 12. The AND gate 12 masks the input strobe signal DQS based on the mask signal MSK, generates a post-mask strobe signal dqs_msk, and outputs it to the read data control circuit 10 and the first edge detection circuit 14. The read data control circuit 10 is a known circuit and controls to latch and read data DQ from the SDRAM 2 at the timing of the strobe signal DQS. Reference numeral 16 denotes a signal buffer for an output signal to the SDRAM 2.

  In FIG. 1, a mask generation circuit 11 operates based on a clock CLK, and masks other than the read period while correcting a read strobe signal DQS based on delay correction number data delay_num from a correction control circuit 19 described later. A mask signal mask_n is generated and output to the timing measurement circuit 13 and also output to the first edge detection circuit 14 and the read data control circuit 21 via the AND gate 12. The timing measurement circuit 13 measures the assert timing of the mask signal mask_n based on the mask edge signal dqs_msk_edge from the first edge detection circuit 14 and uses the measurement result data as memory control data, for example, a CPU (not shown). Output to. The first edge detection circuit 14 detects the first rising edge of the read strobe signal dqs_msk masked by the mask signal mask_n, generates a mask edge signal dqs_msk_edge indicating the detection timing, and outputs the mask edge signal dqs_msk_edge to the timing measurement circuit 13. The L period comparator 18 measures the length of the L period from the memory control data from the timing measurement circuit 13 and outputs comparison result data l_cmp_out indicating the measurement result to the correction control circuit 19. The H period comparator 17 measures the length of the H period from the memory control data from the timing measurement circuit 13 and outputs comparison result data h_cmp_out indicating the measurement result to the correction control circuit 19. The correction control circuit 19 determines a mask signal correction amount based on the data l_cmp_out from the L period comparator 18 and the data h_cmp_out from the H period comparator 17, and generates delay correction number data delay_num indicating the correction amount as a mask. Output to the circuit 11. In response to this, the correction control circuit 19 receives a control signal at the timing of issuing a write or refresh from the command control circuit 20 of the memory and updates the correction amount.

  FIG. 2 is a timing chart showing the timing for taking in the strobe signal DQS in the memory control device 1 of FIG. As is apparent from FIG. 1, the mask signal dqs_msk is a signal obtained by ANDing the read strobe signal DQS with the mask signal mask_n by the AND gate 12. The mask signal mask_n changes from the low level (L) to the high level (H) during the preamble period of the strobe signal DQS, and changes to the low level (L) at the falling edge of the last pulse in the read period. By doing so, the high impedance period of the strobe signal DQS is not taken into the circuit.

  FIG. 3 is a circuit diagram showing a configuration of the timing measurement circuit 13 of FIG. In FIG. 3, the timing measurement circuit 13 includes a plurality of N delay elements 41-0 to 41-(N−1) cascaded to each other, and before and after each delay element 41-0 to 41-(N−1). A plurality of (N + 1) delay flip-flops 42-0 to 42-N that take in data from the terminals at the timing of the mask edge signal dqs_msk_edge and output data Q0 to QN, and a signal buffer that buffers the mask edge signal dqs_msk_edge 43 and a multiplier 44 that multiplies the mask signal msk_n by a predetermined multiplication number and outputs it as a clock to each of the delay elements 41-0 to 41- (N-1). Here, the mask edge signal dqs_msk_edge is a signal that changes from the low level (L) to the high level (H) at the first rising edge of the mask signal dqs_msk.

  FIG. 4 is a timing chart of each signal showing the operation of the timing measurement circuit 13 of FIG. In FIG. 4, the mask signal mask_n is delayed by a predetermined delay time by each delay element 41-0 to 41- (N-1) operating based on the clock from the multiplier 44, and the rising edge of the mask edge signal dqs_msk_edge In each flip-flop 42-0 to 42-N. Here, output data from the flip-flops 42-0 to 42-N are Q0 to QN. In this embodiment, a plurality of delay elements 41-0 to 41- (N-1) are used. However, if possible, the mask signal mask_n may be captured by a high-speed clock whose phase is shifted.

  FIG. 5 is a circuit diagram showing a configuration of the mask generation circuit 11 of FIG. In FIG. 5, the mask generation circuit 11 includes a mask signal generation circuit 51, a plurality of N delay elements 52-1 to 52-N connected in cascade, the mask signal generation circuit 51, and the delay elements 52-1 to 52-1. The multiplexer 53 is configured to select one of the output signals from 52-N based on the delay correction number data delay_num and output the selected signal as a mask signal mask_n. Here, the mask signal generation circuit 51 generates a mask signal at the read timing of the memory and delays it by the delay elements 52-1 to 52-N. Further, one of the plurality of output signals is selected based on the delay correction number data delay_num and is output as a mask signal mask_n.

  FIG. 6 is a diagram for explaining the operation of the L period comparator 18 and the H period comparator 17 of FIG. The memory control data from the timing measurement circuit 13 indicates at what timing the mask signal mask_n has transitioned from the low level (L) to the high level (H). The H comparator 17 gives a period during which the memory control data from the timing measurement circuit 13 is expected to be at a high level (H) as an H comparison parameter (data). As shown in FIG. Compared with the comparison parameter, the number of 0s in the expected period indicated by the H comparison parameter is output as the comparison result data h_cmp_out. If the comparison result data h_cmp_out is 0, the mask signal mask_n is at the high level (H) in the expected period. It shows that it was. The L comparator 18 gives a period during which the memory control data from the timing measurement circuit 13 is expected to be at a low level (L) as an L comparison parameter (data). As shown in FIG. 6, the memory control data Are compared with the L comparison parameter, and one of the expected periods indicated by the L comparison parameter is output as comparison result data l_cmp_out. If the comparison result data l_cmp_out is 0, it indicates that the mask signal mask_n was at the low level (L) in the expected period. In FIG. 6, since the comparison result data l_cmp_out = 2, the mask signal mask_n is changed to the high level (H) earlier than expected. If the two comparison result data h_cmp_out and l_cmp_out are both 0, the timing correction of the mask signal is unnecessary. Otherwise, the timing correction is necessary.

  FIG. 7 is a timing chart of each signal showing the operation of the correction control circuit 19 of FIG. In FIG. 7, wr_com_trg is a signal indicating the timing at which the memory control circuit 1 issues a write command, and is generated by the command control circuit 20. When the comparison result data l_cmp_out changes from 0 to 2, it is detected that the delay amount of the mask signal mask_n needs to be increased. Since it is desirable that the delay amount update timing is not in the middle of reading, the delay correction number data delay_num indicating the correction amount is updated at the write command issuance timing in FIG.

  In the embodiment of FIG. 7 described above, the update is performed at the write command issuance timing, but the update may be performed at another command issuance timing other than the read such as refresh.

  FIG. 8 is a block diagram showing a configuration of the correction control circuit 19 according to the modification. The modification of FIG. 8 is characterized in that the correction control circuit 19 is provided with a temperature sensor input terminal and mask signal correction control is performed based on temperature information from the temperature sensor 61.

  As described with reference to FIG. 7, when the method of adjusting the delay correction number data delay_num is used when a command other than read is issued, the idle temperature continues for a while after the delay correction number data delay_num is updated, and the temperature of the device decreases. There is a possibility that the value of the delay correction number data delay_num is not appropriate. Therefore, the temperature sensor 61 is mounted, and at the time of reading, a correction value table is created using the temperature information from the temperature sensor 61 and the comparison result data of the comparators 17 and 18, and stored in the correction value table memory 60m. Keep it. At the time of operation, based on the temperature information from the temperature sensor 61, the table value (corresponding to the temperature information) registered in the correction value table memory 60m registered at the time of reading is selected, and the delay correction number data delay_num is updated. To do. In this way, even when the idle state continues for a long time, it can be corrected to an appropriate value. In addition to the temperature sensor 61, a voltage sensor may be used in order to take into account delay variation due to changes in the power supply voltage. That is, the delay correction number data delay_num can be corrected based on delay variation parameters such as temperature information and a change in power supply voltage.

  In the above embodiment, the present invention is applied to the DDR-SDRAM. However, the present invention is not limited to this and can be provided to other types of memory circuits.

  As described above in detail, according to the present invention, since the fluctuation of the preamble period during the memory operation is detected and the timing for taking in the strobe signal is corrected, the preamble period detected at the time of memory initialization varies during the memory operation. Even in this case, the strobe signal can be captured only during the read period.

1 ... Memory control device,
2. DDR-SDRAM (SDRAM),
10: Timing correction circuit,
11 ... Mask generation circuit,
12 ... Andgate,
13 ... Timing measurement circuit,
14: First edge detection circuit,
15, 16 ... signal buffer,
20 ... Command control circuit,
21: Read data control circuit,
41-0 to 41- (N-1) ... delay elements,
42-0 to 42-N ... delay type flip-flops,
43 ... Signal buffer,
51. Mask signal generation circuit,
52-1 to 52-N ... delay elements,
53 ... Multiplexer,
60 ... Controller,
60m ... correction value table memory,
61 ... Temperature sensor.

JP-T 2009-541868 JP 2010-122842 A

Claims (5)

In a synchronous memory control device that controls to read data read from a memory circuit in synchronization with a strobe signal generated from the memory circuit other than the memory read period,
A mask signal generating circuit for generating a mask signal; and a plurality of first delay elements connected in cascade to each other, the mask signal being sequentially delayed by the plurality of first delay elements, and the plurality of first delay elements A mask generation circuit for generating a mask signal having a plurality of timings of delay amounts corresponding to the number of stages of the delay elements;
A timing measurement circuit for detecting the mask signal at a plurality of predetermined timings using a signal obtained by ANDing the strobe signal with the mask signal, and outputting data composed of the detected plurality of detection data When,
During operation of the memory circuit, data indicating the data output from the upper Symbol timing measurement circuit, each comparison result is compared with a predetermined expected value of the predetermined expected value and H period L period of the mask signal A comparison circuit that outputs
A memory control circuit comprising: a correction control circuit that corrects a change timing of the mask signal based on data from the comparison circuit during operation of the memory circuit. The timing measurement circuit
(1) The mask signal is input to a plurality of second delay elements that are cascade-connected to each other and driven by a clock obtained by multiplying the mask signal.
(2) Detection is performed by detecting the mask signal at the plurality of timings using the plurality of second delay elements at the timing of the signal obtained by ANDing the strobe signal with the mask signal. the memory control circuit according to claim 1, wherein the outputting the data comprising a plurality of detection data. The correction control circuit includes storage means for preliminarily storing correction value data for correcting the change timing of the mask signal. Based on the value of a predetermined delay variation parameter, the correction control circuit receives the predetermined correction value data from the storage means. 3. The memory control circuit according to claim 1, wherein the memory control circuit is selected and the change timing of the mask signal is corrected based on the correction value data. 4. The memory control circuit according to claim 3 , wherein the delay variation parameter includes temperature information of a temperature sensor. In a mask timing control method for a synchronous memory control device for controlling to read data read from a memory circuit in synchronization with a strobe signal generated from the memory circuit other than the memory read period,
The memory control device
A mask signal generating circuit for generating a mask signal; and a plurality of delay elements connected in cascade with each other, the mask signal being sequentially delayed by the plurality of delay elements, and a delay corresponding to the number of stages of the plurality of delay elements A mask generating circuit for generating a mask signal having a plurality of timings of an amount;
A timing measurement circuit for detecting the mask signal at a plurality of predetermined timings using a signal obtained by ANDing the strobe signal with the mask signal, and outputting data composed of the detected plurality of detection data And
The mask timing control method is as follows:
During the operation of the memory circuit, data output from the timing measurement circuit is compared with a predetermined expected value for the L period and a predetermined expected value for the H period of the mask signal, and data indicating each comparison result is obtained. Output step;
A mask timing control method for the memory control circuit, comprising: correcting the change timing of the mask signal based on data indicating each comparison result during the operation of the memory circuit .

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