CN116846381B - Differential circuit, phase shifter, attenuator and radio frequency microwave system - Google Patents
Differential circuit, phase shifter, attenuator and radio frequency microwave system Download PDFInfo
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Abstract
The invention relates to the technical field of wireless communication, in particular to a differential circuit, a phase shifter, an attenuator and a radio frequency microwave system, which aim to solve the problem of how to simultaneously consider high performance and small size of a radio frequency microwave device. To this end, a differential circuit of the present invention includes: a differential input port, a differential output port and a plurality of switch dies; a switch tube core is connected between each positive and negative electrode interface of the differential input port and the differential output port; when the power supply voltage of the switch tube core between the homopolar interfaces of the differential input port and the differential output port is V and V is positive voltage, the power supply voltage of the other switch tube cores is-V, and the homopolar interfaces of the differential input port and the differential output port are conducted; the switch die is configured to adjust the insertion loss and isolation of the differential circuit based on size and resistance of each pole.
Description
Technical Field
The invention relates to the technical field of wireless communication, and particularly provides a differential circuit, a phase shifter, an attenuator and a radio frequency microwave system.
Background
Modern communication systems have high requirements for radio frequency microwave devices, for example, a digital control attenuator needs to have low in-band insertion loss and high attenuation precision, and a digital control shifter needs to have low in-band insertion loss and high shifting precision and also needs to have small size. The implementation mode of the existing radio frequency microwave device cannot be compatible with the requirements of the device, namely, the loss is low, and the size is small.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks, the present invention is directed to a differential circuit, a phase shifter, an attenuator, and a radio frequency microwave system that solve the technical problems of how to simultaneously consider high performance and small size of a radio frequency microwave device.
In a first aspect, the present invention provides a differential circuit comprising: a differential input port, a differential output port and a plurality of switch dies;
a switch tube core is connected between each positive and negative electrode interface of the differential input port and the differential output port;
when the power supply voltage of the switch tube core between the homopolar interfaces of the differential input port and the differential output port is V and V is positive voltage, the power supply voltage of the other switch tube cores is-V, and the homopolar interfaces of the differential input port and the differential output port are conducted;
The switch die is configured to adjust the insertion loss and isolation of the differential circuit based on size and resistance of each pole.
In one aspect of the above differential circuit,
the differential input port comprises a first input port comprising an interface i1+ and an interface I1-; the differential output port comprises a first output port, and the first output port comprises an interface O1+ and an interface O1-; the switch die includes: a first switch die, a second switch die, a third switch die, and a fourth switch Guan Guanxin;
the input end of the first switch tube core is coupled with the input end of the third switch tube core and is commonly connected to an interface I < 1+ >;
the input end of the second switch tube core is coupled with the input end of the fourth switch tube core and is commonly connected to an interface I1-;
the output end of the first switch tube core is coupled with the output end of the second switch tube core and is commonly connected to an interface O < 1+ >;
the output end of the third switch tube core is coupled with the output end of the fourth switch tube core and is commonly connected to an interface O1-;
the power supply voltage of the first switch tube core and the fourth switch tube core is V1, and the power supply voltage of the second switch tube core and the third switch tube core is-V1;
When V1 is positive voltage, the interface I1 < + > is conducted to the interface O1 < + >, and the interface I1 < - > -is conducted to the interface O1 < - >;
when V1 is a negative voltage, the interface I1 < + > is conducted to the interface O1 < - >, and the interface I1 < - > -is conducted to the interface O1 < + >;
the first, second, third, and fourth switch dies are configured to adjust insertion loss of the differential circuit according to size and pole resistances.
In one aspect of the above differential circuit,
v1 is positive voltage, interface I < 1+ > is conducted to interface O < 1+ >, and interface I < 1 > -is conducted to interface O < 1 >; the first switch die includes a first resistor and a first parasitic capacitance in parallel with the first resistor; the second switch die includes a second capacitance; the third switch die includes a third capacitance; the fourth switching die includes a second resistor and a fourth parasitic capacitance in parallel with the second circuit;
one ends of the first parasitic capacitor and the third capacitor are coupled and commonly connected to an interface I1+;
one ends of the second capacitor and the fourth parasitic capacitor are coupled and commonly connected to an interface I1-;
the other end of the first parasitic capacitor is coupled with the other end of the second capacitor and is commonly connected to an interface O1+;
the other end of the third capacitor is coupled with the other end of the fourth parasitic capacitor and is commonly connected to an interface O1-;
The second capacitance is configured to cancel the first parasitic capacitance and the third capacitance is configured to cancel the fourth parasitic capacitance.
In one technical scheme of the differential circuit, the differential input port comprises a second input port, the second input port comprises an interface I2+ and an interface I2-, the differential output port comprises a second output port and a third output port, and the second output port comprises an interface O2+ and an interface O2-; the third output port comprises an interface O3+ and an interface O3-; the switch die includes: fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth switch dies Guan Guanxin, guan Guanxin, guan Guanxin;
the input ends of the fifth switch die, the eighth switch Guan Guanxin, the ninth switch die and the twelfth switch die are coupled and commonly connected to the interface I2+;
the input ends of the sixth opening Guan Guanxin, the seventh opening Guan Guanxin, the tenth switch die and the eleventh switch die are coupled and commonly connected to an interface I2-;
the output ends of the fifth switch tube core and the sixth switch tube core are coupled and commonly connected to an interface O < 2+ >;
The output ends of the seventh switch Guan Guanxin and the eighth switch tube core are coupled and commonly connected to an interface O2-;
the output ends of the ninth switch tube core and the tenth switch tube core are coupled and commonly connected to an interface O < 3+ >;
the output ends of the eleventh switch tube core and the twelfth switch tube core are coupled and commonly connected to an interface O3-;
the fifth, seventh, ninth, and eleventh switch die are configured to adjust insertion loss of the differential circuit according to size and resistance of each pole; the sixth opening Guan Guanxin, eighth opening Guan Guanxin, tenth switch die, and twelfth switch die are configured to adjust the isolation of the differential circuit according to size.
In one aspect of the above differential circuit,
the power supply voltages of the fifth switch tube core and the seventh switch tube core are V2, and the power supply voltages of the sixth switch Guan Guanxin, the eighth switch Guan Guanxin, the ninth switch tube core, the tenth switch tube core, the eleventh switch tube core and the twelfth switch tube core are-V2;
when V2 is positive voltage, the interface I2 < + > is conducted to the interface O2 < + >, the interface I2 < - > -is conducted to the interface O2 < - >, the interface I2 < + > -is turned off to the interface O3 < + >, and the interface I2 < - > -is turned off to the interface O3 < - >;
or alternatively, the first and second heat exchangers may be,
The power supply voltages of the ninth switch die and the eleventh switch die are V2, and the power supply voltages of the fifth switch die, the sixth switch Guan Guanxin, the seventh switch Guan Guanxin, the eighth switch Guan Guanxin, the tenth switch die and the twelfth switch die are-V2;
when V2 is positive voltage, interface I2+ is conducted to interface O3+, interface I2-is conducted to interface O3-, interface I2+ is turned off to interface O2+, and interface I2-is turned off to interface O2-.
In one aspect of the above differential circuit,
the differential input port comprises a third input port and a fourth input port, the third input port comprises an interface I < 3+ > and an interface I < 3 >, and the fourth input port comprises an interface I < 4+ > and an interface I < 4 >; the differential output port comprises a fourth output port and a fifth output port, the fourth output port comprises an interface O4+ and an interface O4-, and the fifth output port comprises an interface O5+ and an interface O5-; the switch die includes: thirteenth, fourteenth, fifteenth, sixteenth, eighteenth, nineteenth, twentieth, twenty first, twenty second, twenty third, twenty fourth, twenty fifth, twenty sixth, twenty seventh, and twenty eighth switches Guan Guanxin;
The input ends of the thirteenth switch tube core, the sixteenth switch tube core, the seventeenth switch tube core and the twentieth switch tube core are coupled and commonly connected to the interface I3+;
the input ends of the fourteenth, fifteenth, eighteenth and nineteenth switch dies are coupled and commonly connected to interface I3-;
the input ends of the twenty-first switch tube core, the twenty-fourth switch tube core Guan Guanxin, the twenty-fifth switch tube core and the twenty-eighth switch tube core are coupled and commonly connected to the interface I4+;
the input ends of the twenty-second switch tube core, the twenty-third switch tube core, the twenty-sixth switch Guan Guanxin and the twenty-seventh switch tube core are coupled and commonly connected to an interface I4-;
the output ends of the thirteenth switch tube core, the fourteenth switch tube core, the twenty first switch tube core and the twenty second switch tube core are coupled and commonly connected to an interface O4+;
the output ends of the fifteenth switch tube core, the sixteenth switch tube core, the twenty third switch tube core and the twenty fourth switch tube core are coupled and connected to an interface O4-;
the output ends of the seventeenth, eighteenth, twenty-fifth and twenty-sixth switch dies are coupled and commonly connected to the interface O5+;
The output ends of the nineteenth, twentieth, seventeenth and twenty eighth switch dies are coupled and commonly connected to an interface O5-;
the thirteenth, fifteenth, seventeenth, nineteenth, twenty first, twenty third, twenty fifth, and twenty seventh switch dies are configured to adjust insertion loss of the differential circuit according to size and pole resistance; the fourteenth, sixteenth, eighteenth, twentieth, twenty-second, twenty-fourth, twenty-sixth, and twenty-eighth switch dies are configured to adjust the isolation of the differential circuit according to size.
In one aspect of the above differential circuit,
the power supply voltage of the thirteenth, fifteenth, twenty-fifth and twenty-seventh switch tube cores is V3, and the power supply voltage of the fourteenth, sixteenth and twenty-fourth switch tube cores to Guan Guanxin, guan Guanxin and twenty-eighth switch tube cores is-V3;
When V3 is positive voltage, the interface I3+ is conducted to the interface O4+, the interface I3-is conducted to the interface O4-, the interface I4+ is conducted to the interface O5+, the interface I4-is conducted to the interface O5-, the interface I3+ is turned off to the interface O5+, the interface I3-is turned off to the interface O5-, the interface I4+ is turned off to the interface O4+, and the interface I4-is turned off to the interface O4-;
or alternatively, the first and second heat exchangers may be,
the supply voltage of the seventeenth, nineteenth, twenty first and twenty third switch dies is V3, and the supply voltage of the fourteenth, fifteenth, sixteenth, eighteenth, twentieth, twenty second, twenty fourth, guan Guanxin to twenty eighth switch dies is-V3;
when V3 is positive voltage, interface I3+ is conducted to interface O5+, interface I3-is conducted to interface O5-, interface I4+ is conducted to interface O4+, interface I4-is conducted to interface O4-, interface I3+ is turned off to interface O4+, interface I3-is turned off to interface O4-, interface I4+ is turned off to interface O5+, and interface I4-is turned off to interface O5-.
In one aspect of the above differential circuit,
the circuit also comprises a matching circuit, wherein the matching circuit comprises an input matching circuit and an output matching circuit;
the input matching circuit is connected with the differential input port based on the coupling line matching;
The output matching circuit is connected with the differential output port based on the coupling line matching;
the coupled line is configured to adjust return loss of the differential input port and the differential output port according to one or more of even mode impedance, odd mode impedance, or electrical length.
In a second aspect, the invention provides a phase shifter comprising a differential circuit as claimed in any one of the first aspects.
In a third aspect, the invention provides an attenuator comprising a differential circuit as claimed in any one of the first aspects.
In a fourth aspect, the present invention provides a radio frequency microwave system comprising a differential circuit as claimed in any one of the first aspects.
The technical scheme provided by the invention has at least one or more of the following beneficial effects:
in the technical scheme of implementing the invention, based on the differential circuit architecture of the switch tube core design connected between each positive and negative electrode interface of the input port and the output port, the insertion loss of the applied radio frequency microwave device can be reduced, the anti-interference capability of the device is enhanced, and the requirements of high performance and small size of the device can be met through the configuration of the switch tube core, namely, the device can realize high isolation, and meanwhile, the size and the insertion loss of the device are reduced.
Drawings
The present disclosure will become more readily understood with reference to the accompanying drawings. As will be readily appreciated by those skilled in the art: the drawings are for illustrative purposes only and are not intended to limit the scope of the present invention. Moreover, like numerals in the figures are used to designate like parts, wherein:
FIG. 1 is an equivalent circuit schematic diagram of a differential circuit of the present invention;
FIG. 2 is a schematic diagram of a differential circuit (SPST) according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of an equivalent circuit of the differential circuit (SPST) of the present invention;
fig. 4 is a schematic diagram of an input-output matching circuit structure of a differential circuit (SPST) of the present invention;
FIG. 5 is a schematic diagram of the differential circuit (SPST) simulation results (Idiff+ to odiff+ on, idiff-to Odiff-on) of the present invention;
FIG. 6 is a schematic diagram of the differential circuit (SPST) simulation results (Idiff+ to Odiff-on, idiff-to odiff+ on) of the present invention;
FIG. 7 is a schematic diagram of a differential circuit (SPDT) of a second embodiment of the present invention;
FIG. 8 is a schematic diagram of an input-output matching circuit of the differential circuit (SPDT) of the present invention;
FIG. 9 is a schematic diagram of the differential circuit (SPDT) simulation results of the present invention (Idiff 1 through Odiff2 on, idiff2 through Odiff3 off);
Fig. 10 is a schematic diagram of a differential circuit (DPDT) according to a third embodiment of the present invention;
FIG. 11 is a schematic diagram of the simulation results of the differential circuit (SPDT) of the present invention (I3 to O4 on, I4 to O5 on, I3 to O5 off);
FIG. 12 is a schematic diagram of a digitally controlled phase shifter circuit according to a fourth embodiment of the present invention;
FIG. 13 is a diagram showing simulation results of a numerical control phase shifter 354.375 degrees according to a fourth embodiment of the present invention;
FIG. 14 is a diagram showing simulation results of a numerical control attenuator according to a fifth embodiment of the present invention;
FIG. 15 is a schematic diagram of an application of a radio frequency/microwave transmission system of the present invention;
fig. 16 is a schematic diagram of an rf/microwave receiving system application of the present invention.
Detailed Description
Some embodiments of the invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are merely for explaining the technical principles of the present invention, and are not intended to limit the scope of the present invention.
As described in the background art, the digitally controlled phase shifter and the digitally controlled attenuator are radio frequency microwave devices widely used in the field of wireless communication, the digitally controlled phase shifter modulates the phase of a transmitted or received signal, and the digitally controlled attenuator modulates the amplitude of the transmitted or received signal. For example, in modern communication systems such as 5G MIMO communication and low-orbit satellite communication, the attenuation range of a digitally controlled attenuator directly affects the dynamic range of a wireless communication signal, and the shift range of a digitally controlled phase shifter directly affects the phase modulation accuracy of the wireless communication signal.
Existing digitally controlled phase shifter implementations generally include two types: the first mode is to use a single-ended switch to switch a transmission line to move to a unit network, and the numerical control phase shifter of the form has obvious performance deterioration at high frequency (the frequency is more than 8 GHz), mainly comprises the conditions that the switching insertion loss is larger and the switching insertion loss is larger when the frequency is increased (especially in the millimeter wave frequency range) and the phase is 180 DEG; the second is to use an inductor to realize a shift function, which is also difficult to realize under high frequency conditions, mainly because with the increase of frequency (especially in millimeter wave frequency band), the inductance loss increases, and the parasitic capacitance has a significant influence on the performance.
The existing numerical control attenuator implementation mode is generally as follows: the digital control attenuator in the form of the single-ended switch is used for switching the resistance attenuation network, and the performance degradation of the digital control attenuator in the form of the digital control attenuator is obvious at high frequency (the frequency is more than 8 GHz), mainly because the switching insertion loss is larger along with the increase of the frequency (especially in the millimeter wave frequency band), when a large attenuation value (such as 16dB attenuation) is encountered, the channel needs to be gated by increasing the number of switches stack, the channel needs to be realized in a larger size, and the switching insertion loss is also increased again.
For the realization mode of the existing numerical control phase shifter and numerical control attenuator, the requirements of a modern communication system on the two devices cannot be simultaneously met, and based on the realization mode, the invention provides a differential circuit which can be high in performance and small in size.
Specifically, as shown in fig. 1, the embodiment of the present invention provides a differential circuit, which includes: a differential input port 1, a differential output port 2 and a plurality of switch tube cores; a switch tube core is connected between each positive and negative electrode interface of the differential input port 1 and the differential output port 2, namely, a switch tube core is arranged between the cross connection of the positive and negative electrode interfaces of the differential input port 1 and the differential output port 2, and it is noted that the differential input port 1 and the differential output port 2 are not limited to only one group of positive and negative electrode ports, a plurality of positive and negative electrode ports can exist at the same time, the positive electrode or the negative electrode in each differential input port 1 is respectively connected with each interface in the differential output port 2, and a switch tube core is arranged between the positive and negative electrode ports, and the number of the ports is not limited;
based on the circuit arrangement and the connection relation, in the invention, when the power supply voltage of the switch tube core between the homopolar interfaces of the differential input port 1 and the differential output port 2 is V and V is positive voltage and the power supply voltage of the other switch tube cores is-V, the homopolar interfaces of the differential input port 1 and the differential output port 2 are conducted; for example, a switch tube core between the positive electrode interface of the differential input port 1 and the positive electrode interface of the differential output port 2 realizes conduction between the two interfaces when the power supply voltage is a positive voltage and the rest switch tube cores are negative voltages;
Based on the above relationship, the switch die is configured to adjust the insertion loss and isolation of the differential circuit according to the size and the resistances of the respective poles. Adjusting the die size of the switch, i.e. adjusting R of the switch in the on condition on Value (on-resistance of switch); after the switch tube core is conducted, the insertion loss of the switch tube core is represented by R on Value sum R ds The (drain-to-source resistance) value is commonly determined, i.e. R on Parallel R ds ；R gs (Gate-to-Source resistance) affects the switching field effectThe voltage of the response tube, namely, the insertion loss of the switch is different under different voltages; therefore, the size of the switch tube core and the resistance of each electrode can be adjusted, the problems of insertion loss and device size are solved, and meanwhile, the smaller the switch off capacitance is, the smaller the size is, the better the isolation degree is, and the isolation degree of the differential circuit can be adjusted by adjusting the size of the switch tube core. Preferably, in the embodiment of the present invention, the switch dies all use dies with a size of 1stack 0.7mm, i.e. the die sizes are as identical as possible.
It should be noted that the present invention does not limit the specific size of the switch die, and in the actual use process, the appropriate size is selected according to the user's requirement, and the technical scheme after the modification or replacement of the die size falls within the protection scope of the present invention without deviating from the circuit architecture of the present invention.
In order to more clearly illustrate the differential circuit of the present invention, a detailed description is provided below in connection with specific embodiments.
Example 1
As shown in fig. 2, the differential circuit (SPST circuit) of the present embodiment includes a differential input port, a differential output port, and a plurality of switch dies, the differential input port includes a first input port, the first input port includes an interface i1+ and an interface I1-; the differential output port comprises a first output port, and the first output port comprises an interface O1+ and an interface O1-; the switch die includes: a first switch die T1, a second switch die T2, a third switch die T3, and a fourth switch Guan Guanxin T4;
the input of the first switching die T1 and the input of the third switching die T3 are coupled and commonly connected to the interface i1+; an input of the second switch die T2 and an input of the fourth switch Guan Guanxin T4 are coupled and commonly connected to interface I1-; the output of the first switching die T1 and the output of the second switching die T2 are coupled and commonly connected to the interface o1+; the output of the third switching die T3 and the output of the fourth switch Guan Guanxin T4 are coupled and commonly connected to interface O1-; the power supply voltage of the first switch tube core T1 and the fourth switch tube core Guan Guanxin T4 is V1, and the power supply voltage of the second switch tube core T2 and the third switch tube core T3 is-V1;
When V1 is positive voltage, i.e. V1 > Vth (gate threshold voltage), interface I1+ to interface O1+ are turned on, interface I1-to interface O1-are turned on; when V1 is a negative voltage, namely-V1 > Vth, the interface I1 < + > is conducted to the interface O1 < - >, and the interface I1 < + > is conducted to the interface O1 < + >; under the condition that a 180-degree phase line is not needed, the two states can be switched by 180-degree phase conveniently, the size of the device is reduced, and meanwhile, the insertion loss of the device is also reduced.
By adjusting the dimensions of the first switching die T1 and fourth switch Guan Guanxin T4, R ds (drain-to-source resistance), R gs The (gate-to-source resistance) adjusts the insertion loss of the differential circuit, and the second and third switch dies T2, T3 are sized to adjust the isolation of the differential circuit.
In one embodiment, as shown in fig. 3, the SPST circuit in fig. 2 is equivalent to the circuit shown in fig. 3, the interfaces i1+ to o1+ are turned on, when the interfaces I1 to O1 are turned on, the first switch die T1 is equivalent to a resistor R1 parallel capacitor C1 (C1 is a parasitic capacitor), the second switch die T2 is equivalent to a capacitor C2, the fourth switch die Guan Guanxin T4 is equivalent to a resistor R2 parallel capacitor C4 (C4 is a parasitic capacitor), and the third switch die T3 is equivalent to a capacitor C3; the capacitor C2 can offset the capacitor C1, the capacitor C3 can offset the capacitor C4, so that the application requirement of the millimeter wave frequency band is met, the millimeter wave circuit frequency is relatively high, the capacitor shows low capacitance resistance characteristics under the millimeter wave frequency band, for example, the 100fF capacitor has low capacitance resistance characteristics at the 30GHz position; the millimeter wave is in a conducting state, so that the insertion loss of the switch is increased, and the isolation function cannot be realized; as described in the present invention, it is critical to remove the capacitor C1 from the millimeter wave band, and for the capacitor C2, which has the same value as the capacitor C1 but 180 ° phase difference, the two are connected in parallel, which is represented by c1+c2 and c2= -C1, so that the two capacitors cancel each other out, and the switch, in the on state, exhibits a simple resistance characteristic (R on Very small); the switch also exhibits a resistance characteristic (R off Large) and thus high isolation is easily achieved without increasing the number of switches stack, while reducing device size and device insertion loss.
In one embodiment, as shown in fig. 4, the SPST circuit of fig. 2 is equivalently processed and added to a matching circuit that includes a matching network IMN and an output matching network OMN. The IMN is realized through a coupling line transmission line and can be characterized by an even mode impedance Ze1, an odd mode impedance Zo1 and an electric length LE 1; OMN is implemented by a coupled line transmission line and can be characterized by an even mode impedance Ze2, an odd mode impedance Zo2, and an electrical length LE 2. In the invention, the return loss of a differential input port (Idiff+, idiff-) is regulated by optimizing the values of even mode impedance Ze1, odd mode impedance Zo1 and electrical length LE 1; the differential output port (odiff+, odiff-) return loss is adjusted by optimizing the values of the even mode impedance Ze2, the odd mode impedance Zo2, and the electrical length LE 2. The even mode impedance and the odd mode impedance are regulated, the differential impedance of the port is regulated, the port impedance influences the return loss, and therefore the effect of regulating the return loss can be achieved; the electric length LE shows different impedance under radio frequency and microwave frequency, and the effect of adjusting the port impedance is achieved by changing the electric length.
It should be noted that the matching network of the present invention is not limited to the SPST circuit in the first embodiment, and is also applicable to other differential circuits, such as the SPDT circuit, the DPDT circuit, and the like in the following embodiments.
Based on the SPST circuit and the matching circuit, simulation experiments are carried out on the switching performance of the SPST circuit, when Idiff+ is conducted to odiff+ is conducted, idiff-is conducted to Odiff-and the result is shown in figure 5, figure 5 (a) shows the insertion loss from a differential input end (port Idiff, shown as S1 in the figure) to a differential output end (port Odiff, shown as S2 in the figure), and the SPST circuit can still keep lower insertion loss at high frequency (millimeter wave frequency band, for example, the frequency of a sampling point m1 is 30 Ghz), is-0.42 dB, the absolute value is smaller than 0.5dB, and the requirements of low insertion loss and small size of a radio frequency microwave device at high frequency (especially millimeter wave frequency band) are met; FIG. 5 (b) shows the return loss of the differential input and differential output, between-15 dB and-35 dB, with high matching of the coupled line-based matching circuit; fig. 5 (c) shows a signal phase diagram of the differential output terminal output with respect to the differential input terminal;
when Idiff+ to Odiff-on, idiff-to odiff+ on, as shown in FIG. 6, FIG. 6 (a) shows the insertion loss from differential input to differential output, FIG. 5 (b) shows the return loss of differential input and differential output, FIG. 5 (c) shows the signal phase diagram of differential output to differential input, and comparing FIG. 5 and FIG. 6, it can be seen that the differential SPST circuit can realize 180 degree phase difference, for example, sampling point m5, at the same frequency (20 GHz), the phase is changed from-43.789 degrees to 136.211 degrees.
Example two
As shown in fig. 7, the differential circuit (SPDT circuit) of the present embodiment includes a differential input port including a second input port including an interface i2+ and an interface I2-, a differential output port including a second output port and a third output port, and a plurality of switch dies; the third output port comprises an interface O3+ and an interface O3-; the switch die includes: fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth switch dies T5, guan Guanxin T6, guan Guanxin T7, guan Guanxin T8, T9, T10, T11, and T12;
the fifth, eighth, ninth, and twelfth switch dies T5, guan Guanxin T8, T9, T12 are coupled at their inputs and commonly connected to the interface i2+; the inputs of the sixth opening Guan Guanxin T6, seventh opening Guan Guanxin T7, tenth switch die T10, eleventh switch die T11 are coupled and commonly connected to interface I2-; the output terminals of the fifth switch die T5, the sixth switch Guan Guanxin T6 are coupled and commonly connected to the interface o2+; the output ends of the seventh opening Guan Guanxin T7 and the eighth opening Guan Guanxin T8 are coupled and commonly connected to an interface O2-; the output ends of the ninth and tenth switch dies T9 and T10 are coupled and commonly connected to the interface O3+; the output ends of the eleventh switch die T11 and the twelfth switch die T12 are coupled and commonly connected to the interface O3-;
In the circuit, when the supply voltages of the fifth switch die T5 and the seventh switch Guan Guanxin T7 are selected to be V2, the supply voltages of the sixth switch Guan Guanxin T6, the eighth switch Guan Guanxin T8, the ninth switch die T9, the tenth switch die T10, the eleventh switch die T11 and the twelfth switch die T12 are selected to be-V2; then, when V2 is positive voltage (V2 > Vth), interface I2+ is turned on to interface O2+, interface I2-is turned on to interface O2-, interface I2+ is turned off to interface O3+, and interface I2-is turned off to interface O3-;
when the power supply voltages of the ninth switch tube core T9 and the eleventh switch tube core T11 are V2, the power supply voltages of the fifth switch tube core T5, the sixth switch tube core Guan Guanxin T6, the seventh switch Guan Guanxin T7, the eighth switch Guan Guanxin T8, the tenth switch tube core T10 and the twelfth switch tube core T12 are-V2; then when V2 is positive voltage (V2 > Vth), interface I2+ is turned on to interface O3+, interface I2-is turned on to interface O3-, interface I2+ is turned off to interface O2+, and interface I2-is turned off to interface O2-.
By adjusting the dimensions, R, of the fifth, seventh, ninth and eleventh switch dies T5, guan Guanxin T7, T9, T11 ds (drain-to-source resistance), R gs (gate-to-source resistance) to adjust the insertion loss of the differential switch; adjusting the dimensions of the sixth opening Guan Guanxin T6, eighth opening Guan Guanxin T8, tenth switch die T10, and twelfth switch die T12 adjusts the isolation of the differential switches.
In one embodiment, as shown in fig. 8, the SPDT circuit with the matching circuit adjusts the differential input port (idif1+, idif1-) return loss by optimizing the values of the even mode impedance Ze3, the odd mode impedance Zo3, and the electrical length LE3, the output matching circuit adjusts the differential output port (odif2+, odiff 2-) return loss by optimizing the values of the even mode impedance Ze4, the odd mode impedance Zo4, and the electrical length LE4, and adjusts the differential output port (odif3+, odif3-) return loss by optimizing the values of Ze5, zo5, and LE5, the adjustment principle being as in the matching circuit of example one, and not described in detail herein.
Selecting the power supply voltages of the fifth switch die T5 and the seventh switch die Guan Guanxin T7 to be V2 based on the SPDT circuit and the matching circuit, and then the power supply voltages of the sixth switch Guan Guanxin T6, the eighth switch Guan Guanxin T8, the ninth switch die T9, the tenth switch die T10, the eleventh switch die T11, and the twelfth switch die T12 to be-V2; then, when V2 is a positive voltage, ports Idiff1 to Odiff2 are turned on, and Idiff1 to Odiff3 are turned off, the switching performance of the differential SPDT circuit is shown in fig. 9, fig. 9 (a) shows the insertion loss from the differential input end (port Idiff1, S1 in the drawing) to the differential output end (port Odiff2, S2 in the drawing), and it can be seen that the SPDT circuit maintains a low insertion loss at high frequency (millimeter wave frequency band, less than 30 GHz), is-0.64 dB, has an absolute value less than 0.7dB, and meets the requirement of low insertion loss and small size of the radio frequency microwave device at high frequency (especially millimeter wave frequency band); FIG. 9 (b) shows the return loss from the differential input end (port Idiff 1) to the differential output end (Odiff 2), within 30GHz, between-15 dB and-30 dB, and shows that the matching circuit based on the coupling line has higher matching degree in the high frequency band; fig. 9 (c) shows the isolation between the differential input end (port Idiff 1) and the differential output end (port Odiff3, shown schematically as S3), and it can be seen that Idiff1 and Odiff3 are isolated within DC-40 GHz and less than-400 dB, so that the differential attenuator is very suitable for being used as a digital control attenuator and a digital control phase shifter.
Example III
As shown in fig. 10, the differential circuit (DPDT circuit) of the present embodiment includes a differential input port, a differential output port and a plurality of switch dies, the differential input port includes a third input port and a fourth input port, the third input port includes an interface i3+ and an interface I3-, and the fourth input port includes an interface i4+ and an interface I4-; the differential output port comprises a fourth output port and a fifth output port, the fourth output port comprises an interface O4+ and an interface O4-, and the fifth output port comprises an interface O5+ and an interface O5-; the switch die includes: thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, eighteenth, nineteenth, and twentieth switching dies T13, T14, T15, T16, T17, T18, T19, T20 a twenty-first switch die T21, a twenty-second switch die T22, a twenty-third switch die T23, a twenty-fourth switch die Guan Guanxin T24, a twenty-fifth switch die T25, a twenty-sixth switch Guan Guanxin T26, a twenty-seventh switch Guan Guanxin T27, and a twenty-eighth switch Guan Guanxin T28;
the thirteenth, sixteenth, seventeenth, and twentieth switching dies T13, T16, T17, T20 are coupled at their inputs and commonly connected to the interface i3+; the fourteenth, fifteenth, eighteenth, nineteenth, and nineteenth switching dies T14, T15, T18, T19 are coupled at their inputs and commonly connected to interface I3-; the input ends of the twenty-first switch die T21, the twenty-fourth switch die Guan Guanxin T24, the twenty-fifth switch die T25 and the twenty-eighth switch die Guan Guanxin T28 are coupled and commonly connected to the interface I4+; the twenty-second switch die T22, the twenty-third switch die T23, the twenty-sixth switch Guan Guanxin T26, the twenty-seventh switch Guan Guanxin T27 are coupled at their inputs and commonly connected to interface I4-; the thirteenth, fourteenth, twenty-first, and twenty-second switching dies T13, T14, T21, T22 are coupled at their outputs and commonly connected to the interface o4+; the output ends of the fifteenth switch die T15, the sixteenth switch die T16, the twenty third switch die T23 and the twenty fourth switch die Guan Guanxin T24 are coupled and connected to the interface O4-; the seventeenth, eighteenth, twenty-fifth, and twenty-sixth switch dies T17, T18, T25, guan Guanxin T26 are coupled at their outputs and commonly connected to the interface o5+; the output terminals of the nineteenth, twentieth, twenty-seventh, and twenty-eighth switch dies T19, T20, guan Guanxin, T27, guan Guanxin, T28 are coupled and commonly connected to interface O5-;
In the circuit, when the supply voltages of the thirteenth switch die T13, the fifteenth switch die T15, the twenty-fifth switch die T25 and the twenty-seventh switch die Guan Guanxin T27 are selected to be V3, the supply voltages of the fourteenth switch die T14, the sixteenth switch die T16 to the twenty-fourth switch Guan Guanxin T24, the twenty-sixth switch Guan Guanxin T26 and the twenty-eighth switch Guan Guanxin T28 are selected to be-V3; then, when V3 is a positive voltage (V3 > Vth), interface I3+ is turned on to interface O4+, interface I3-is turned on to interface O4-, interface I4+ is turned on to interface O5+, interface I4-is turned on to interface O5-, interface I3+ is turned off to interface O5+, interface I3-is turned off to interface O5-, interface I4+ is turned off to interface O4-, and interface I4-is turned off to interface O4-;
selecting a seventeenth switch die T17, a nineteenth switch die T19, a twenty-first switch die T21 and a twenty-third switch die T23 to have a supply voltage of V3, and then selecting a fourteenth switch die T14, a fifteenth switch die T15, a sixteenth switch die T16, an eighteenth switch die T18, a twentieth switch die T20, a twenty-second switch die T22, a twenty-fourth switch die Guan Guanxin T24 to a twenty-eighth switch Guan Guanxin T28 to have a supply voltage of-V3; then, when V3 is a positive voltage (V3 > Vth), interface I3+ is turned on to interface O5+, interface I3-is turned on to interface O5-, interface I4+ is turned on to interface O4+, interface I4-is turned on to interface O4-, interface I3+ is turned off to interface O4+, interface I3-is turned off to interface O4-, interface I4+ is turned off to interface O5+, and interface I4-is turned off to interface O5-.
By adjusting the dimensions, R, of the thirteenth, fifteenth, seventeenth, nineteenth, twenty first, twenty third, twenty fifth, and twenty seventh switch dies T13, T15, T17, T19, T21, T23, T25, and Guan Guanxin T27 ds (drain-to-source resistance), R gs (gate-to-source resistance) to adjust the insertion loss of the differential circuit; adjusting the size of the fourteenth, sixteenth, eighteenth, twentieth, twenty-second, twenty-fourth, twenty-sixth, and twenty-eighth switch dies T14, T16, T18, T20, T22, guan Guanxin T24, guan Guanxin T26, guan Guanxin T28 adjusts the isolation of the differential circuit.
Based on a DPDT circuit, interface I < 3+ > to interface O < 4+ > is selected to be conducted, interface I < 3 > -to interface O < 4 > -is conducted, interface I < 4+ > to interface O < 5+ > is conducted, interface I < 4 > -to interface O < 5 > -is conducted, interface I < 3 > -to interface O < 5 > -is turned off, interface I < 4 > -to interface O < 4 > -is turned off, namely, port I < 3 > -to port O < 4 > -is conducted, port I < 4 > -to port O < 5 > -is conducted, the switching performance of the differential DPDT circuit is shown as shown in fig. 11, fig. 11 (a) shows the insertion loss from a differential input end (port I < 3 > -S1 >) to a differential output end (port O < 4 > -S3 >) respectively, the DPDT circuit can be seen to keep lower insertion loss at high frequency (millimeter wave frequency band, the insertion loss is less than 30GHz, the absolute value is less than 0.8dB, the requirement of low insertion loss of a radio frequency microwave device at high frequency (especially in frequency band) is satisfied, and the double-pole-throw switch is realized at the same time; FIG. 11 (b) shows the return loss from the differential input end (port I3) to the differential output end (port O4), within 30GHz, between-15 dB and-30 dB, and shows that the matching degree is higher in the high frequency band if the matching circuit based on the coupling line is adopted; fig. 11 (c) shows the isolation between the differential input end (port I3) and the differential output end (port O5, schematically indicated as S4), and it can be seen that the isolation between the port I3 and the port O5 is within DC-40 GHz, which is less than-300 dB, and is suitable for use as a digitally controlled attenuator and a digitally controlled phase shifter.
Example IV
Based on the embodiment, a 6-bit numerical control phase shifter with 0 GHz-35 GHz is designed, the numerical control phase shifter comprises an SPST circuit switch, two SPDT circuit switches and 4 DPDT circuit switches, and according to the specific reference, as shown in FIG. 12, 354.375-degree performance simulation is carried out on the numerical control phase shifter, and as shown in FIG. 13, the result is that the insertion loss between the input end and the output end of the phase shifter is shown in FIG. 13 (a), the insertion loss is kept low at-4.147 dB under the millimeter wave frequency band and is kept to be smaller than 30GHz, the absolute value is smaller than 4.5dB, and the requirements of the phase shifter on low insertion loss and small size under the high frequency (especially millimeter wave frequency band) are met; fig. 13 (b) shows a 354.375 ° phase diagram of the phase shifter, the total length of the phase lines being 174.375 ° +180 °, and the 180 ° phase implementation principle being obtained using the differential circuit itself having 180 ° phase conversion characteristics as described in the first embodiment; fig. 13 (c) shows the return loss from the input end to the output end in this state, and the return loss is between-12 dB dB and-25 dB when the return loss is between 20GHz and 30GHz, and the circuit matching is high.
It should be noted that, the differential circuit form and the combination adopted by the numerical control phase shifter are only used for effect display, the specific structure of the phase shifter is not limited, and any phase shifter designed based on the differential circuit form of the invention is within the protection scope of the invention.
Example five
Based on the embodiment, a 6-bit numerical control attenuator with 10 GHz-40 GHz is designed, an attenuation state of 0.5dB is added on the basis of the fourth embodiment, and performance simulation is carried out on the numerical control attenuator, and as shown in a result of FIG. 14, FIG. 14 (a) shows insertion loss in the state of 0.5dB, insertion loss of the numerical control attenuator in the non-attenuation state is more than-5 dB, and the insertion loss is far smaller than that of the same type of product; fig. 14 (b) shows that the return loss from the input end to the output end in this state is less than-12 dB at 10 to 40ghz, and the circuit matching performance is high between-12 dB to-40 dB.
It should be noted that, the specific structure of the attenuator is not limited in the present invention, and any attenuator designed based on the differential circuit form of the present invention should be within the protection scope of the present invention.
Based on the embodiment, the numerical control attenuator and the numerical control phase shifter realized based on the differential circuit architecture can reduce the insertion loss of the device and enhance the anti-interference capability of the device; for the numerical control phase shifter, the differential SPST circuit can conveniently realize 180-degree phase switching under the condition of not needing 180-degree phase lines, so that the size of a device is reduced, and meanwhile, the insertion loss of the device is also reduced; for the digital control attenuator, the differential switching circuit of the invention has the advantages that the input and the output are connected with the switch tube cores (such as the switch tube core T2 and the switch tube core T4 in the differential SPST switch) which are always in the off state, so that the parasitic capacitance of the on switch can be counteracted, the high isolation degree can be realized easily under the condition that the number of the switches stack is not increased, the device size and the device insertion loss are reduced, and the digital control attenuator and the digital control phase shifter which use the differential circuit architecture can obtain good performance in the millimeter wave frequency band easily due to the fact that the parasitic capacitance of the on switch can be counteracted. Furthermore, the invention realizes the matching of the input and output circuits by using the mode of the coupling line transmission line, thereby greatly reducing the optimization difficulty of the matching circuit, reducing the size of the matching circuit and increasing the integration level of devices.
Further, the application also provides a radio frequency microwave system, which comprises one or more of the differential circuit, the phase shifter or the attenuator in the embodiment.
In one embodiment, as shown in fig. 15 and 16, the rf microwave device designed based on the differential circuit of the above embodiment, such as a phase shifter or attenuation, is applied in an rf microwave system, fig. 15 is an rf/microwave transmitting system, and fig. 16 is an rf/microwave receiving system. For convenience of explanation, only the parts related to the embodiments of the present application are shown, and specific technical details are not disclosed, please refer to the differential circuit part of the embodiments of the present application.
The terms "first," "second," and the like, herein, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order, and should not be taken to indicate or imply relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more. Furthermore, unless explicitly stated and limited otherwise, the terms "connected," "connected," and "connected" are to be construed broadly, and may be, for example, directly connected or indirectly connected through intervening media, or may be in communication between two elements. The specific meaning of the above terms in the present application can be understood by those skilled in the art according to the specific circumstances.
The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus/apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus/apparatus.
Thus far, the technical solution of the present invention has been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of protection of the present invention is not limited to these specific embodiments. Equivalent modifications and substitutions for related technical features may be made by those skilled in the art without departing from the principles of the present invention, and such modifications and substitutions will fall within the scope of the present invention.
Claims (7)
1. A differential circuit for use in a phase shifter or attenuator, comprising: a differential input port, a differential output port and a plurality of switch dies;
a switch tube core is connected between each positive and negative electrode interface of the differential input port and the differential output port;
when the power supply voltage of the switch tube core between the homopolar interfaces of the differential input port and the differential output port is V and V is positive voltage, the power supply voltage of the other switch tube cores is-V, and the homopolar interfaces of the differential input port and the differential output port are conducted;
The switch tube core is configured to adjust the insertion loss and isolation of the differential circuit according to the size and the resistance of each pole;
the differential input port comprises a first input port comprising an interface i1+ and an interface I1-; the differential output port comprises a first output port, and the first output port comprises an interface O1+ and an interface O1-; the switch die includes: a first switch die, a second switch die, a third switch die, and a fourth switch Guan Guanxin;
the input end of the first switch tube core is coupled with the input end of the third switch tube core and is commonly connected to an interface I < 1+ >;
the input end of the second switch tube core is coupled with the input end of the fourth switch tube core and is commonly connected to an interface I1-;
the output end of the first switch tube core is coupled with the output end of the second switch tube core and is commonly connected to an interface O < 1+ >;
the output end of the third switch tube core is coupled with the output end of the fourth switch tube core and is commonly connected to an interface O1-;
the power supply voltage of the first switch tube core and the fourth switch tube core is V1, and the power supply voltage of the second switch tube core and the third switch tube core is-V1;
when V1 is positive voltage, the interface I1 < + > is conducted to the interface O1 < + >, and the interface I1 < - > -is conducted to the interface O1 < - >;
When V1 is a negative voltage, the interface I1 < + > is conducted to the interface O1 < - >, and the interface I1 < - > -is conducted to the interface O1 < + >;
the first, second, third and fourth switch die are configured to adjust insertion loss of the differential circuit according to size and resistance of each pole;
v1 is positive voltage, interface I < 1+ > is conducted to interface O < 1+ >, and interface I < 1 > -is conducted to interface O < 1 >; the first switch tube core is equivalent to a first resistor and a first parasitic capacitor connected with the first resistor in parallel; the second switch tube core is equivalent to a second capacitor; the third switch tube core is equivalent to a third capacitor; the fourth switch Guan Guanxin is equivalently a second resistor and a fourth parasitic capacitor connected in parallel with the second resistor;
one ends of the first parasitic capacitor and the third capacitor are coupled and commonly connected to an interface I1+;
one ends of the second capacitor and the fourth parasitic capacitor are coupled and commonly connected to an interface I1-;
the other end of the first parasitic capacitor is coupled with the other end of the second capacitor and is commonly connected to an interface O1+;
the other end of the third capacitor is coupled with the other end of the fourth parasitic capacitor and is commonly connected to an interface O1-;
the second capacitance is configured to cancel the first parasitic capacitance, the third capacitance is configured to cancel the fourth parasitic capacitance, the value of the second capacitance is equal to the value of the first parasitic capacitance, and the value of the third capacitance is equal to the value of the fourth parasitic capacitance.
2. The differential circuit of claim 1, wherein the differential input port comprises a second input port comprising an interface i2+ and an interface I2-, the differential output port comprises a second output port and a third output port, the second output port comprises an interface o2+ and an interface O2-; the third output port comprises an interface O3+ and an interface O3-; the switch die includes: fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth switch dies Guan Guanxin, guan Guanxin, guan Guanxin;
the input ends of the fifth switch die, the eighth switch Guan Guanxin, the ninth switch die and the twelfth switch die are coupled and commonly connected to the interface I2+;
the input ends of the sixth opening Guan Guanxin, the seventh opening Guan Guanxin, the tenth switch die and the eleventh switch die are coupled and commonly connected to an interface I2-;
the output ends of the fifth switch tube core and the sixth switch tube core are coupled and commonly connected to an interface O < 2+ >;
the output ends of the seventh switch Guan Guanxin and the eighth switch tube core are coupled and commonly connected to an interface O2-;
The output ends of the ninth switch tube core and the tenth switch tube core are coupled and commonly connected to an interface O < 3+ >;
the output ends of the eleventh switch tube core and the twelfth switch tube core are coupled and commonly connected to an interface O3-;
the fifth, seventh, ninth, and eleventh switch die are configured to adjust insertion loss of the differential circuit according to size and resistance of each pole; the sixth opening Guan Guanxin, eighth opening Guan Guanxin, tenth switch die, and twelfth switch die are configured to adjust the isolation of the differential circuit according to size.
3. The differential circuit according to claim 2, wherein,
the power supply voltages of the fifth switch tube core and the seventh switch tube core are V2, and the power supply voltages of the sixth switch Guan Guanxin, the eighth switch Guan Guanxin, the ninth switch tube core, the tenth switch tube core, the eleventh switch tube core and the twelfth switch tube core are-V2;
when V2 is positive voltage, the interface I2 < + > is conducted to the interface O2 < + >, the interface I2 < - > -is conducted to the interface O2 < - >, the interface I2 < + > -is turned off to the interface O3 < + >, and the interface I2 < - > -is turned off to the interface O3 < - >;
or alternatively, the first and second heat exchangers may be,
the power supply voltages of the ninth switch die and the eleventh switch die are V2, and the power supply voltages of the fifth switch die, the sixth switch Guan Guanxin, the seventh switch Guan Guanxin, the eighth switch Guan Guanxin, the tenth switch die and the twelfth switch die are-V2;
When V2 is positive voltage, interface I2+ is conducted to interface O3+, interface I2-is conducted to interface O3-, interface I2+ is turned off to interface O2+, and interface I2-is turned off to interface O2-.
4. The differential circuit of claim 1, wherein the differential input ports comprise a third input port and a fourth input port, the third input port comprising interface i3+ and interface I3-, the fourth input port comprising interface i4+ and interface I4-; the differential output port comprises a fourth output port and a fifth output port, the fourth output port comprises an interface O4+ and an interface O4-, and the fifth output port comprises an interface O5+ and an interface O5-; the switch die includes: thirteenth, fourteenth, fifteenth, sixteenth, eighteenth, nineteenth, twentieth, twenty first, twenty second, twenty third, twenty fourth, twenty fifth, twenty sixth, twenty seventh, and twenty eighth switches Guan Guanxin;
the input ends of the thirteenth switch tube core, the sixteenth switch tube core, the seventeenth switch tube core and the twentieth switch tube core are coupled and commonly connected to the interface I3+;
The input ends of the fourteenth, fifteenth, eighteenth and nineteenth switch dies are coupled and commonly connected to interface I3-;
the input ends of the twenty-first switch tube core, the twenty-fourth switch tube core Guan Guanxin, the twenty-fifth switch tube core and the twenty-eighth switch tube core are coupled and commonly connected to the interface I4+;
the input ends of the twenty-second switch tube core, the twenty-third switch tube core, the twenty-sixth switch Guan Guanxin and the twenty-seventh switch tube core are coupled and commonly connected to an interface I4-;
the output ends of the thirteenth switch tube core, the fourteenth switch tube core, the twenty first switch tube core and the twenty second switch tube core are coupled and commonly connected to an interface O4+;
the output ends of the fifteenth switch tube core, the sixteenth switch tube core, the twenty third switch tube core and the twenty fourth switch tube core are coupled and connected to an interface O4-;
the output ends of the seventeenth, eighteenth, twenty-fifth and twenty-sixth switch dies are coupled and commonly connected to the interface O5+;
the output ends of the nineteenth, twentieth, seventeenth and twenty eighth switch dies are coupled and commonly connected to an interface O5-;
The thirteenth, fifteenth, seventeenth, nineteenth, twenty first, twenty third, twenty fifth, and twenty seventh switch dies are configured to adjust insertion loss of the differential circuit according to size and pole resistance; the fourteenth, sixteenth, eighteenth, twentieth, twenty-second, twenty-fourth, twenty-sixth, and twenty-eighth switch dies are configured to adjust the isolation of the differential circuit according to size.
5. The differential circuit according to claim 4, wherein,
the power supply voltage of the thirteenth, fifteenth, twenty-fifth and twenty-seventh switch tube cores is V3, and the power supply voltage of the fourteenth, sixteenth and twenty-fourth switch tube cores to Guan Guanxin, guan Guanxin and twenty-eighth switch tube cores is-V3;
when V3 is positive voltage, the interface I3+ is conducted to the interface O4+, the interface I3-is conducted to the interface O4-, the interface I4+ is conducted to the interface O5+, the interface I4-is conducted to the interface O5-, the interface I3+ is turned off to the interface O5+, the interface I3-is turned off to the interface O5-, the interface I4+ is turned off to the interface O4+, and the interface I4-is turned off to the interface O4-;
Or alternatively, the first and second heat exchangers may be,
the supply voltage of the seventeenth, nineteenth, twenty first and twenty third switch dies is V3, and the supply voltage of the fourteenth, fifteenth, sixteenth, eighteenth, twentieth, twenty second, twenty fourth, guan Guanxin to twenty eighth switch dies is-V3;
when V3 is positive voltage, interface I3+ is conducted to interface O5+, interface I3-is conducted to interface O5-, interface I4+ is conducted to interface O4+, interface I4-is conducted to interface O4-, interface I3+ is turned off to interface O4+, interface I3-is turned off to interface O4-, interface I4+ is turned off to interface O5+, and interface I4-is turned off to interface O5-.
6. The differential circuit according to any one of claims 1-5, further comprising a matching circuit comprising an input matching circuit and an output matching circuit;
the input matching circuit is connected with the differential input port based on the coupling line matching;
the output matching circuit is connected with the differential output port based on the coupling line matching;
the coupled line is configured to adjust return loss of the differential input port and the differential output port according to one or more of even mode impedance, odd mode impedance, or electrical length.
7. A radio frequency microwave system comprising a differential circuit as claimed in any one of claims 1 to 6.
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