CN116318074A - Second-order nonlinear correction circuit of 25% duty cycle mixer - Google Patents
Second-order nonlinear correction circuit of 25% duty cycle mixer Download PDFInfo
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- CN116318074A CN116318074A CN202310301219.4A CN202310301219A CN116318074A CN 116318074 A CN116318074 A CN 116318074A CN 202310301219 A CN202310301219 A CN 202310301219A CN 116318074 A CN116318074 A CN 116318074A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
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Abstract
The invention provides a second-order nonlinear correction circuit of a 25% duty cycle mixer, comprising: a first mixer circuit; the first mixing circuit is electrically connected with the differential signal source and mixes the differential signal into a first phase signal; the first mixing circuit is provided with a first bias voltage source and a second bias voltage source which are adjustable; the second mixing circuit is electrically connected with the differential signal source and mixes the differential signal into a second phase signal; the second mixing circuit is provided with a third/fourth bias voltage source which is adjustable; the delay adjustment modules are electrically connected with the phase signal input interfaces of the first frequency mixing circuit and the second frequency mixing circuit; the delay adjustment modules are provided with adjustable voltage sources and/or inverters with adjustable numbers, and the delay adjustment modules and the first bias voltage source, the second bias voltage source, the third bias voltage source and the fourth bias voltage source are used for adjusting the first mixing circuit and the second mixing circuit together. The invention can realize the second-order linear correction of the 25% duty cycle mixer.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to a second-order nonlinear correction circuit of a 25% duty cycle mixer.
Background
Nonlinearity is a phenomenon that must exist in a circuit, and for second-order nonlinearity, the most common approach is to use a differential circuit. However, the degree of suppression depends on the symmetry of the differential circuit, the greater the circuit mismatch, the greater the second order nonlinearity. For a high-performance receiver, the second-order nonlinearity of the differential circuit is difficult to meet the system requirement based on layout optimization, so that the second-order nonlinearity needs to be additionally corrected.
The prior correction technology mainly aims at a traditional receiver of a 50% duty cycle local oscillator, and the generation reasons of second-order nonlinearity mainly aim at the following two aspects: first, the mixer switch is not matched with the duty ratio of the local oscillator p/n, and second, the intermediate frequency filter is not matched. Therefore, the correction method mainly applies different bias voltages to the pair of tubes of the mixer to correct the circuit mismatch caused by the reasons, and the traditional method only aims at the correction of I paths or Q paths and does not relate to the correction among the I paths and the Q paths. However, for the receiver (gain is 3dB greater than that of the conventional receiver) of the local oscillator with the currently-used 25% duty ratio, the I/Q phase mismatch of the local oscillator can lead to simultaneous conduction of the two paths of I/Q in a short time, and the second-order nonlinearity of the I path can be fed through to the Q path, and vice versa. The traditional correction method is difficult to correct second-order nonlinearity caused by I/Q phase mismatch.
Disclosure of Invention
The second-order nonlinear correction circuit of the 25% duty cycle mixer provided by the invention can effectively control the local oscillation delay time, and realize the second-order nonlinear correction of the 25% duty cycle mixer.
The invention provides a second-order nonlinear correction circuit of a 25% duty cycle mixer, comprising:
a first mixer circuit; the first mixing circuit is electrically connected with the differential signal source and is used for mixing the differential signal sent by the differential signal source into a first output signal; the first mixing circuit is provided with an adjustable first bias voltage source and an adjustable second bias voltage source;
the second mixing circuit is electrically connected with the differential signal source and is used for mixing the differential signal sent by the differential signal source into a second output signal; the second mixing circuit is provided with an adjustable third bias voltage source and an adjustable fourth bias voltage source;
the delay adjustment modules are respectively and electrically connected with the phase signal input interfaces of the first frequency mixing circuit and the second frequency mixing circuit; wherein the plurality of delay adjustment modules have adjustable voltage sources and/or an adjustable number of inverters; the adjustable voltage source and/or the number of the inverters are used for adjusting the first frequency mixing circuit and the second frequency mixing circuit together with the first bias voltage source, the second bias voltage source, the third bias voltage source and the fourth bias voltage source.
Optionally, the plurality of delay adjustment modules includes:
the first delay module comprises two inverters which are connected in parallel, wherein the two inverters are electrically connected with a first voltage source and are used for outputting a first clock signal to a first phase signal input interface of a first mixing circuit after twice inversion;
the second delay module comprises two inverters which are connected in parallel, wherein the two inverters are electrically connected with the first voltage source and are used for outputting a second clock signal to a second phase signal input interface of the first mixing circuit after twice inversion;
the third delay module comprises two inverters which are connected in parallel, wherein the two inverters are electrically connected with a second voltage source and are used for outputting a third clock signal to a first phase signal input interface of a second mixing circuit after twice inversion;
the fourth delay module comprises two inverters which are connected in parallel, wherein the two inverters are electrically connected with a second voltage source, and the two inverters are used for outputting a fourth clock signal to a second phase signal input interface of the second mixing circuit after twice inversion.
Optionally, the plurality of delay adjustment modules are connected to the same third voltage source, each delay adjustment module comprising:
the plurality of parallel inverters are electrically connected with the third voltage source, the plurality of inverters are used for outputting an input signal to the phase signal input interfaces of the first frequency mixing circuit and the second frequency mixing circuit after multiple times of inversion, at least one of the plurality of parallel inverters is provided with an adjusting switch, and the adjusting switch is used for controlling the on-off of the corresponding inverter.
Optionally, the inverter with the adjusting switch includes a plurality of inverting units, at least one of the plurality of inverting units has the adjusting switch, and the inverting unit with the adjusting switch includes:
the first end of the first MOS tube is electrically connected with a third voltage source, and the grid electrode of the first MOS tube is electrically connected with an input signal;
the first end of the first adjusting switch is electrically connected with the second end of the first MOS tube;
the first end of the second adjusting switch is electrically connected with the second end of the first adjusting switch, and the first end of the second adjusting switch is electrically connected with the output signal;
the first end of the second MOS tube is electrically connected with the second end of the second adjusting switch, and the second end of the second MOS tube is grounded; and the grid electrode of the second MOS tube is electrically connected with an input signal.
Optionally, the first mixing circuit includes:
the input interface of the first mixer is electrically connected with the differential pair signal, and the first mixer is controlled by a first phase signal and a second phase signal;
the input interface of the first intermediate frequency amplifier is electrically connected with the output interface of the first mixer.
Optionally, the first mixer includes:
the first end of the first switching tube is connected with a first signal of the differential pair signal, the grid electrode of the first switching tube is electrically connected with a first phase signal through a first capacitor, and the grid electrode of the first switching tube is also electrically connected with a first bias voltage through a first resistor;
the first end of the second switching tube is connected with the first signal of the differential pair signal, and the grid electrode of the second switching tube is electrically connected with a second bias voltage through a second resistor;
the first end of the third switching tube is electrically connected with the second signal of the differential pair signal, the grid electrode of the third switching tube is electrically connected with the grid electrode of the second switching tube through a second capacitor and a third capacitor which are connected in series, the second end of the third switching tube is electrically connected with the second end of the first switching tube, and the grid electrode of the third switching tube is also electrically connected with the first bias voltage through a third resistor;
and the first end of the fourth switching tube is electrically connected with the second signal of the differential pair signal, the grid electrode of the fourth switching tube is electrically connected with the second phase signal through a fourth capacitor, and the grid electrode of the fourth switching tube is also electrically connected with the second bias voltage through a fourth resistor.
Optionally, a first input interface of the first intermediate frequency amplifier is electrically connected with a first output interface of the first mixer, and a second input interface of the first intermediate frequency amplifier is electrically connected with a second output interface of the first mixer;
the first input end of the first intermediate frequency amplifier is electrically connected with the first end of the fifth capacitor, and the first input end of the first intermediate frequency amplifier is also electrically connected with the first end of the sixth capacitor;
the second input end of the first intermediate frequency amplifier is electrically connected with the second end of the fifth capacitor, and the second input end of the first intermediate frequency amplifier is also electrically connected with the second end of the sixth capacitor;
the first output end of the first intermediate frequency amplifier is electrically connected with the first output end of the first mixer through a fifth resistor;
the second output end of the first intermediate frequency amplifier is electrically connected with the second output end of the first mixer through a sixth resistor.
Optionally, the second mixing circuit includes:
the input interface of the second mixer is electrically connected with the differential pair signal, and the second mixer is controlled by a third phase signal and a fourth phase signal;
and the input interface of the second intermediate frequency amplifier is electrically connected with the output interface of the second mixer.
Optionally, the second mixer includes:
the first end of the fifth switching tube is connected with the first signal of the differential pair signal, the grid electrode of the fifth switching tube is electrically connected with a third phase signal through a seventh capacitor, and the grid electrode of the fifth switching tube is also electrically connected with a third bias voltage through a seventh resistor;
the first end of the sixth switching tube is connected with the first signal of the differential pair signal, and the grid electrode of the sixth switching tube is electrically connected with the fourth bias voltage through an eighth resistor;
a seventh switching tube, wherein a first end of the seventh switching tube is electrically connected with a second signal of the differential pair signal, a grid electrode of the third switching tube is electrically connected with a grid electrode of the sixth switching tube through an eighth capacitor and a ninth capacitor which are connected in series, a second end of the seventh switching tube is electrically connected with a second end of the fifth switching tube, and the grid electrode of the seventh switching tube is also electrically connected with a third bias voltage through an eighth resistor;
and the first end of the eighth switching tube is electrically connected with the second signal of the differential pair signal, the grid electrode of the eighth switching tube is electrically connected with the fourth phase signal through a tenth capacitor, and the grid electrode of the eighth switching tube is also electrically connected with the fourth bias voltage through a tenth resistor.
Optionally, the first input interface of the second intermediate frequency amplifier is electrically connected with the first output interface of the second mixer, and the second input interface of the second intermediate frequency amplifier is electrically connected with the second output interface of the second mixer;
the first input end of the second intermediate frequency amplifier is electrically connected with the first end of the eleventh capacitor, and the first input end of the second intermediate frequency amplifier is also electrically connected with the first end of the twelfth capacitor;
the second input end of the second intermediate frequency amplifier is electrically connected with the second end of the eleventh capacitor, and the second input end of the second intermediate frequency amplifier is also electrically connected with the second end of the twelfth capacitor;
the first output end of the second intermediate frequency amplifier is electrically connected with the first output end of the second mixer through an eleventh resistor;
and a second output end of the second intermediate frequency amplifier is electrically connected with a second output end of the second mixer through a twelfth resistor.
In a second aspect, the invention provides a chip comprising a second order nonlinear correction circuit of a 25% duty cycle mixer as defined in any one of the preceding claims.
In a third aspect, the present invention provides a communication terminal comprising a chip as claimed in any one of the preceding claims.
In the technical scheme provided by the invention, the delay of each phase signal of the 25% duty cycle mixer is controlled through each delay module, so that the simultaneous conduction of two paths of I/Q of the local oscillator is effectively avoided, and the second-order nonlinearity of the 25% duty cycle mixer is corrected.
Drawings
FIG. 1 is a schematic diagram of a second order nonlinear correction circuit of a 25% duty cycle mixer according to an embodiment of the invention;
FIG. 2 is a schematic diagram of the principle of a 25% duty cycle mixer to produce nonlinearities;
FIG. 3 is a schematic diagram of a delay adjustment module of a second order nonlinear correction circuit of a 25% duty cycle mixer according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a delay adjustment module of a second order nonlinear correction circuit of a 25% duty cycle mixer according to another embodiment of the present invention;
FIG. 5 is a schematic diagram of a delay adjustment module of a second order nonlinear correction circuit of a 25% duty cycle mixer according to another embodiment of the present invention;
fig. 6 is a schematic diagram of a mixer and an intermediate frequency amplifier in a second order nonlinear correction circuit of a 25% duty cycle mixer according to another embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
An embodiment of the present invention provides a second-order nonlinear correction circuit of a 25% duty cycle mixer, as shown in fig. 1, including:
a first mixer circuit; the first mixing circuit is electrically connected with the differential signal source and is used for mixing the differential signal sent by the differential signal source into a first output signal; the first mixing circuit is provided with an adjustable first bias voltage source and an adjustable second bias voltage source;
the second mixing circuit is electrically connected with the differential signal source and is used for mixing the differential signal sent by the differential signal source into a second output signal; the second mixing circuit is provided with an adjustable third bias voltage source and an adjustable fourth bias voltage source;
the delay adjustment modules are respectively and electrically connected with the phase signal input interfaces of the first frequency mixing circuit and the second frequency mixing circuit; wherein the plurality of delay adjustment modules have adjustable voltage sources and/or an adjustable number of inverters; the adjustable voltage source and/or the number of the inverters are used for adjusting the first frequency mixing circuit and the second frequency mixing circuit together with the first bias voltage source, the second bias voltage source, the third bias voltage source and the fourth bias voltage source.
As shown in fig. 2, a single balanced circuit is taken as an example, when the 0 ° phase of the local oscillator and the 90 ° phase of the local oscillator are simultaneously conducted, a second-order nonlinear current component IM2 generated by the I-path of the first mixer circuit flows into the I-path intermediate frequency amplifier, and a part of the second-order nonlinear current component IM2 flows into the Q-path intermediate frequency amplifier of the second mixer circuit, and the ratio of the two paths of the split currents depends on the parasitic degree and the mismatch degree of the two paths of the I/Q. When this new second order non-linearity cause occurs in the circuit, the circuit correction needs to be improved. In the technical scheme provided by the embodiment of the invention, the delay of each phase signal of the 25% duty cycle mixer is controlled through each delay module, so that the simultaneous conduction of two paths of I/Q of the local oscillator is effectively avoided, and the second-order nonlinearity of the 25% duty cycle mixer is corrected. In the technical scheme provided by the embodiment of the invention, the correction of the local oscillation phase is introduced, the controllable delay is introduced on the I/Q path local oscillation drive, and the condition that the I path and the Q path are simultaneously conducted is eliminated by changing the delay during correction.
As an alternative embodiment, as shown in fig. 3, the plurality of delay adjustment modules include:
the first delay module comprises two inverters which are connected in parallel, wherein the two inverters are electrically connected with a first voltage source and are used for outputting a first clock signal to a first phase signal input interface of a first mixing circuit after twice inversion;
the second delay module comprises two inverters which are connected in parallel, wherein the two inverters are electrically connected with the first voltage source and are used for outputting a second clock signal to a second phase signal input interface of the first mixing circuit after twice inversion;
the third delay module comprises two inverters which are connected in parallel, wherein the two inverters are electrically connected with a second voltage source and are used for outputting a third clock signal to a first phase signal input interface of a second mixing circuit after twice inversion;
the fourth delay module comprises two inverters which are connected in parallel, wherein the two inverters are electrically connected with a second voltage source, and the two inverters are used for outputting a fourth clock signal to a second phase signal input interface of the second mixing circuit after twice inversion.
In some embodiments, by controlling the local oscillator driven power supply, the I/Q two-way local oscillator phase is made to have different delays, as shown in fig. 3, where the first voltage source voltage VDD1 and the second voltage source voltage VDD2 are both from a linear voltage regulator, which is adjustable in voltage, and thus the delay is adjustable.
As an alternative embodiment, as shown in fig. 4, the plurality of delay adjustment modules are connected to the same third voltage source, and each delay adjustment module includes:
the plurality of parallel inverters are electrically connected with the third voltage source, the plurality of inverters are used for outputting an input signal to the phase signal input interfaces of the first frequency mixing circuit and the second frequency mixing circuit after multiple times of inversion, at least one of the plurality of parallel inverters is provided with an adjusting switch, and the adjusting switch is used for controlling the on-off of the corresponding inverter. As shown in fig. 4, the inverter with the diagonal arrow is an inverter with an adjustment switch.
As an alternative embodiment, as shown in fig. 5, an inverter with an adjustment switch includes a plurality of inverting units, at least one of which has an adjustment switch, the inverting unit with an adjustment switch including:
the first end of the first MOS tube is electrically connected with a third voltage source, and the grid electrode of the first MOS tube is electrically connected with an input signal;
the first end of the first adjusting switch is electrically connected with the second end of the first MOS tube;
the first end of the second adjusting switch is electrically connected with the second end of the first adjusting switch, and the first end of the second adjusting switch is electrically connected with the output signal;
the first end of the second MOS tube is electrically connected with the second end of the second adjusting switch, and the second end of the second MOS tube is grounded; and the grid electrode of the second MOS tube is electrically connected with an input signal.
In some embodiments, as shown in fig. 5, at least one of the inversion units has a switch control, and the equivalent MOS transistor size in the local oscillation drive is changed by opening and closing the corresponding switch, so that the delay can be effectively adjusted.
As an alternative embodiment, as shown in fig. 6, the first mixing circuit includes:
the input interface of the first mixer is electrically connected with the differential pair signal, and the first mixer is controlled by a first phase signal and a second phase signal;
the input interface of the first intermediate frequency amplifier is electrically connected with the output interface of the first mixer.
As an alternative embodiment, continuing to refer to fig. 6, the first mixer includes:
the first end of the first switching tube is connected with a first signal of the differential pair signal, the grid electrode of the first switching tube is electrically connected with a first phase signal through a first capacitor, and the grid electrode of the first switching tube is also electrically connected with a first bias voltage through a first resistor;
the first end of the second switching tube is connected with the first signal of the differential pair signal, and the grid electrode of the second switching tube is electrically connected with a second bias voltage through a second resistor;
the first end of the third switching tube is electrically connected with the second signal of the differential pair signal, the grid electrode of the third switching tube is electrically connected with the grid electrode of the second switching tube through a second capacitor and a third capacitor which are connected in series, the second end of the third switching tube is electrically connected with the second end of the first switching tube, and the grid electrode of the third switching tube is also electrically connected with the first bias voltage through a third resistor;
and the first end of the fourth switching tube is electrically connected with the second signal of the differential pair signal, the grid electrode of the fourth switching tube is electrically connected with the second phase signal through a fourth capacitor, and the grid electrode of the fourth switching tube is also electrically connected with the second bias voltage through a fourth resistor.
As an alternative embodiment, continuing to refer to fig. 6, the first input interface of the first intermediate frequency amplifier is electrically connected to the first output interface of the first mixer, and the second input interface of the first intermediate frequency amplifier is electrically connected to the second output interface of the first mixer;
the first input end of the first intermediate frequency amplifier is electrically connected with the first end of the fifth capacitor, and the first input end of the first intermediate frequency amplifier is also electrically connected with the first end of the sixth capacitor;
the second input end of the first intermediate frequency amplifier is electrically connected with the second end of the fifth capacitor, and the second input end of the first intermediate frequency amplifier is also electrically connected with the second end of the sixth capacitor;
the first output end of the first intermediate frequency amplifier is electrically connected with the first output end of the first mixer through a fifth resistor;
the second output end of the first intermediate frequency amplifier is electrically connected with the second output end of the first mixer through a sixth resistor.
As an alternative embodiment, continuing to refer to fig. 6, the second mixing circuit includes:
the input interface of the second mixer is electrically connected with the differential pair signal, and the second mixer is controlled by a third phase signal and a fourth phase signal;
and the input interface of the second intermediate frequency amplifier is electrically connected with the output interface of the second mixer.
As an alternative embodiment, continuing to refer to fig. 6, the second mixer includes:
the first end of the fifth switching tube is connected with the first signal of the differential pair signal, the grid electrode of the fifth switching tube is electrically connected with a third phase signal through a seventh capacitor, and the grid electrode of the fifth switching tube is also electrically connected with a third bias voltage through a seventh resistor;
the first end of the sixth switching tube is connected with the first signal of the differential pair signal, and the grid electrode of the sixth switching tube is electrically connected with the fourth bias voltage through an eighth resistor;
a seventh switching tube, wherein a first end of the seventh switching tube is electrically connected with a second signal of the differential pair signal, a grid electrode of the third switching tube is electrically connected with a grid electrode of the sixth switching tube through an eighth capacitor and a ninth capacitor which are connected in series, a second end of the seventh switching tube is electrically connected with a second end of the fifth switching tube, and the grid electrode of the seventh switching tube is also electrically connected with a third bias voltage through an eighth resistor;
and the first end of the eighth switching tube is electrically connected with the second signal of the differential pair signal, the grid electrode of the eighth switching tube is electrically connected with the fourth phase signal through a tenth capacitor, and the grid electrode of the eighth switching tube is also electrically connected with the fourth bias voltage through a tenth resistor.
As an alternative embodiment, as further shown in fig. 6, the first input interface of the second intermediate frequency amplifier is electrically connected to the first output interface of the second mixer, and the second input interface of the second intermediate frequency amplifier is electrically connected to the second output interface of the second mixer;
the first input end of the second intermediate frequency amplifier is electrically connected with the first end of the eleventh capacitor, and the first input end of the second intermediate frequency amplifier is also electrically connected with the first end of the twelfth capacitor;
the second input end of the second intermediate frequency amplifier is electrically connected with the second end of the eleventh capacitor, and the second input end of the second intermediate frequency amplifier is also electrically connected with the second end of the twelfth capacitor;
the first output end of the second intermediate frequency amplifier is electrically connected with the first output end of the second mixer through an eleventh resistor;
and a second output end of the second intermediate frequency amplifier is electrically connected with a second output end of the second mixer through a twelfth resistor.
The embodiment of the invention also provides a chip, which comprises the second-order nonlinear correction circuit of the 25% duty cycle mixer.
The embodiment of the invention also provides a communication terminal, which comprises the chip.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (12)
1. A second order nonlinear correction circuit of a 25% duty cycle mixer, comprising:
a first mixer circuit; the first mixing circuit is electrically connected with the differential signal source and is used for mixing the differential signal sent by the differential signal source into a first output signal; the first mixing circuit is provided with an adjustable first bias voltage source and an adjustable second bias voltage source;
the second mixing circuit is electrically connected with the differential signal source and is used for mixing the differential signal sent by the differential signal source into a second output signal; the second mixing circuit is provided with an adjustable third bias voltage source and an adjustable fourth bias voltage source;
the delay adjustment modules are respectively and electrically connected with the phase signal input interfaces of the first frequency mixing circuit and the second frequency mixing circuit; wherein the plurality of delay adjustment modules have adjustable voltage sources and/or an adjustable number of inverters; the adjustable voltage source and/or the number of the inverters are used for adjusting the first frequency mixing circuit and the second frequency mixing circuit together with the first bias voltage source, the second bias voltage source, the third bias voltage source and the fourth bias voltage source.
2. The circuit of claim 1, wherein the plurality of delay adjustment modules comprises:
the first delay module comprises two inverters which are connected in parallel, wherein the two inverters are electrically connected with a first voltage source and are used for outputting a first clock signal to a first phase signal input interface of a first mixing circuit after twice inversion;
the second delay module comprises two inverters which are connected in parallel, wherein the two inverters are electrically connected with the first voltage source and are used for outputting a second clock signal to a second phase signal input interface of the first mixing circuit after twice inversion;
the third delay module comprises two inverters which are connected in parallel, wherein the two inverters are electrically connected with a second voltage source and are used for outputting a third clock signal to a first phase signal input interface of a second mixing circuit after twice inversion;
the fourth delay module comprises two inverters which are connected in parallel, wherein the two inverters are electrically connected with a second voltage source, and the two inverters are used for outputting a fourth clock signal to a second phase signal input interface of the second mixing circuit after twice inversion.
3. The circuit of claim 1, wherein the plurality of delay adjustment modules are connected to the same third voltage source, each delay adjustment module comprising:
the plurality of parallel inverters are electrically connected with the third voltage source, the plurality of inverters are used for outputting an input signal to the phase signal input interfaces of the first frequency mixing circuit and the second frequency mixing circuit after multiple times of inversion, at least one of the plurality of parallel inverters is provided with an adjusting switch, and the adjusting switch is used for controlling the on-off of the corresponding inverter.
4. A circuit according to claim 3, wherein the inverter with the adjustment switch comprises a plurality of inverting units, at least one of the plurality of inverting units having the adjustment switch, the inverting unit having the adjustment switch comprising:
the first end of the first MOS tube is electrically connected with a third voltage source, and the grid electrode of the first MOS tube is electrically connected with an input signal;
the first end of the first adjusting switch is electrically connected with the second end of the first MOS tube;
the first end of the second adjusting switch is electrically connected with the second end of the first adjusting switch, and the first end of the second adjusting switch is electrically connected with the output signal;
the first end of the second MOS tube is electrically connected with the second end of the second adjusting switch, and the second end of the second MOS tube is grounded; and the grid electrode of the second MOS tube is electrically connected with an input signal.
5. The circuit of claim 1, wherein the first mixing circuit comprises:
the input interface of the first mixer is electrically connected with the differential pair signal, and the first mixer is controlled by a first phase signal and a second phase signal;
the input interface of the first intermediate frequency amplifier is electrically connected with the output interface of the first mixer.
6. The circuit of claim 5, wherein the first mixer comprises:
the first end of the first switching tube is connected with a first signal of the differential pair signal, the grid electrode of the first switching tube is electrically connected with a first phase signal through a first capacitor, and the grid electrode of the first switching tube is also electrically connected with a first bias voltage through a first resistor;
the first end of the second switching tube is connected with the first signal of the differential pair signal, and the grid electrode of the second switching tube is electrically connected with a second bias voltage through a second resistor;
the first end of the third switching tube is electrically connected with the second signal of the differential pair signal, the grid electrode of the third switching tube is electrically connected with the grid electrode of the second switching tube through a second capacitor and a third capacitor which are connected in series, the second end of the third switching tube is electrically connected with the second end of the first switching tube, and the grid electrode of the third switching tube is also electrically connected with the first bias voltage through a third resistor;
and the first end of the fourth switching tube is electrically connected with the second signal of the differential pair signal, the grid electrode of the fourth switching tube is electrically connected with the second phase signal through a fourth capacitor, and the grid electrode of the fourth switching tube is also electrically connected with the second bias voltage through a fourth resistor.
7. The circuit of claim 5, wherein a first input interface of the first intermediate frequency amplifier is electrically connected to a first output interface of the first mixer, and a second input interface of the first intermediate frequency amplifier is electrically connected to a second output interface of the first mixer;
the first input end of the first intermediate frequency amplifier is electrically connected with the first end of the fifth capacitor, and the first input end of the first intermediate frequency amplifier is also electrically connected with the first end of the sixth capacitor;
the second input end of the first intermediate frequency amplifier is electrically connected with the second end of the fifth capacitor, and the second input end of the first intermediate frequency amplifier is also electrically connected with the second end of the sixth capacitor;
the first output end of the first intermediate frequency amplifier is electrically connected with the first output end of the first mixer through a fifth resistor;
the second output end of the first intermediate frequency amplifier is electrically connected with the second output end of the first mixer through a sixth resistor.
8. The circuit of claim 1, wherein the second mixing circuit comprises:
the input interface of the second mixer is electrically connected with the differential pair signal, and the second mixer is controlled by a third phase signal and a fourth phase signal;
and the input interface of the second intermediate frequency amplifier is electrically connected with the output interface of the second mixer.
9. The circuit of claim 8, wherein the second mixer comprises:
the first end of the fifth switching tube is connected with the first signal of the differential pair signal, the grid electrode of the fifth switching tube is electrically connected with a third phase signal through a seventh capacitor, and the grid electrode of the fifth switching tube is also electrically connected with a third bias voltage through a seventh resistor;
the first end of the sixth switching tube is connected with the first signal of the differential pair signal, and the grid electrode of the sixth switching tube is electrically connected with the fourth bias voltage through an eighth resistor;
a seventh switching tube, wherein a first end of the seventh switching tube is electrically connected with a second signal of the differential pair signal, a grid electrode of the third switching tube is electrically connected with a grid electrode of the sixth switching tube through an eighth capacitor and a ninth capacitor which are connected in series, a second end of the seventh switching tube is electrically connected with a second end of the fifth switching tube, and the grid electrode of the seventh switching tube is also electrically connected with a third bias voltage through an eighth resistor;
and the first end of the eighth switching tube is electrically connected with the second signal of the differential pair signal, the grid electrode of the eighth switching tube is electrically connected with the fourth phase signal through a tenth capacitor, and the grid electrode of the eighth switching tube is also electrically connected with the fourth bias voltage through a tenth resistor.
10. The circuit of claim 8, wherein a first input interface of the second intermediate frequency amplifier is electrically connected to a first output interface of the second mixer, and a second input interface of the second intermediate frequency amplifier is electrically connected to a second output interface of the second mixer;
the first input end of the second intermediate frequency amplifier is electrically connected with the first end of the eleventh capacitor, and the first input end of the second intermediate frequency amplifier is also electrically connected with the first end of the twelfth capacitor;
the second input end of the second intermediate frequency amplifier is electrically connected with the second end of the eleventh capacitor, and the second input end of the second intermediate frequency amplifier is also electrically connected with the second end of the twelfth capacitor;
the first output end of the second intermediate frequency amplifier is electrically connected with the first output end of the second mixer through an eleventh resistor;
and a second output end of the second intermediate frequency amplifier is electrically connected with a second output end of the second mixer through a twelfth resistor.
11. A chip comprising a second order nonlinear correction circuit of a 25% duty cycle mixer as recited in any one of claims 1-10.
12. A communication terminal, characterized in that it comprises a chip as claimed in claim 11.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310301219.4A CN116318074B (en) | 2023-03-17 | 2023-03-17 | Second-order nonlinear correction circuit of 25% duty cycle mixer |
| CN202311399248.5A CN117375586A (en) | 2023-03-17 | 2023-03-17 | Second-order nonlinear correction circuit of 25% duty cycle mixer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202310301219.4A CN116318074B (en) | 2023-03-17 | 2023-03-17 | Second-order nonlinear correction circuit of 25% duty cycle mixer |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311399248.5A Division CN117375586A (en) | 2023-03-17 | 2023-03-17 | Second-order nonlinear correction circuit of 25% duty cycle mixer |
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| Publication Number | Publication Date |
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| CN116318074A true CN116318074A (en) | 2023-06-23 |
| CN116318074B CN116318074B (en) | 2023-11-21 |
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| CN202311399248.5A Pending CN117375586A (en) | 2023-03-17 | 2023-03-17 | Second-order nonlinear correction circuit of 25% duty cycle mixer |
| CN202310301219.4A Active CN116318074B (en) | 2023-03-17 | 2023-03-17 | Second-order nonlinear correction circuit of 25% duty cycle mixer |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311399248.5A Pending CN117375586A (en) | 2023-03-17 | 2023-03-17 | Second-order nonlinear correction circuit of 25% duty cycle mixer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116846381A (en) * | 2023-08-31 | 2023-10-03 | 宜确半导体（苏州）有限公司 | Differential circuit, phase shifter, attenuator and radio frequency microwave system |
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| US20070285144A1 (en) * | 2006-06-09 | 2007-12-13 | Prasenjit Bhowmik | Delay line with delay cells having improved gain and in built duty cycle control and method thereof |
| CN104539286A (en) * | 2014-12-10 | 2015-04-22 | 深圳市国微电子有限公司 | Fundamental frequency clock generation circuit |
| CN105007044A (en) * | 2014-04-18 | 2015-10-28 | 清华大学 | Harmonic wave inhibition frequency mixer |
| CN110957998A (en) * | 2019-12-02 | 2020-04-03 | 翱捷智能科技(上海)有限公司 | Circuit for accurately correcting duty ratio of clock signal |
| CN114629441A (en) * | 2022-03-03 | 2022-06-14 | 北京大学 | Correction method for suppressing harmonic waves of passive down-mixer of receiver |
-
2023
- 2023-03-17 CN CN202311399248.5A patent/CN117375586A/en active Pending
- 2023-03-17 CN CN202310301219.4A patent/CN116318074B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070285144A1 (en) * | 2006-06-09 | 2007-12-13 | Prasenjit Bhowmik | Delay line with delay cells having improved gain and in built duty cycle control and method thereof |
| CN105007044A (en) * | 2014-04-18 | 2015-10-28 | 清华大学 | Harmonic wave inhibition frequency mixer |
| CN104539286A (en) * | 2014-12-10 | 2015-04-22 | 深圳市国微电子有限公司 | Fundamental frequency clock generation circuit |
| CN110957998A (en) * | 2019-12-02 | 2020-04-03 | 翱捷智能科技(上海)有限公司 | Circuit for accurately correcting duty ratio of clock signal |
| CN114629441A (en) * | 2022-03-03 | 2022-06-14 | 北京大学 | Correction method for suppressing harmonic waves of passive down-mixer of receiver |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116846381A (en) * | 2023-08-31 | 2023-10-03 | 宜确半导体（苏州）有限公司 | Differential circuit, phase shifter, attenuator and radio frequency microwave system |
| CN116846381B (en) * | 2023-08-31 | 2023-11-28 | 宜确半导体（苏州）有限公司 | Differential circuit, phase shifter, attenuator and radio frequency microwave system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117375586A (en) | 2024-01-09 |
| CN116318074B (en) | 2023-11-21 |
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