CN116844963A - Silicon carbide-based FINFET power device, preparation method thereof and chip - Google Patents
Silicon carbide-based FINFET power device, preparation method thereof and chip Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 31
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 27
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000002955 isolation Methods 0.000 claims description 127
- 229910052751 metal Inorganic materials 0.000 claims description 68
- 239000002184 metal Substances 0.000 claims description 68
- 238000009792 diffusion process Methods 0.000 claims description 61
- 238000005530 etching Methods 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- 230000007480 spreading Effects 0.000 claims description 16
- 238000003892 spreading Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Microelectronics & Electronic Packaging (AREA)
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- Ceramic Engineering (AREA)
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- General Physics & Mathematics (AREA)
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Abstract
The application belongs to the technical field of semiconductors, and provides a silicon carbide-based FINFET power device, a preparation method thereof and a chip.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a silicon carbide-based FINFET power device, a preparation method thereof and a chip.
Background
The breakdown voltage (Breakdown Voltage, BV) of a power transistor is a very important parameter in order to increase the BV of the power transistor while saving chip area, the power transistor is converted from a planar structure to a vertical structure. The pursuit of high breakdown voltage, high current density, and smaller device area remains a further development direction for power transistors, and vertical FinFET power devices are receiving widespread attention for their advantages of high current density, high withstand voltage, and small chip area.
However, in a vertical FinFET power device, the surge current generated by the device turn-off is typically drained by a parasitic body diode within the device, which is fragile, with a large negative impact on the reliability of the device.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides a silicon carbide-based FINFET power device, a preparation method thereof and a chip, and aims to solve the problem that the reliability of the device is reduced due to the fact that a parasitic body diode in a vertical type FinFET power device is fragile.
The first aspect of the embodiment of the application provides a preparation method of a silicon carbide-based FINFET power device, which comprises the following steps:
sequentially epitaxially growing an N-type drift layer and a P-type switch isolation layer on the front surface of the silicon carbide substrate;
n-type doping is carried out on the appointed area of the P-type switch isolation layer to form a voltage channel layer so as to divide the P-type switch isolation layer into a first switch isolation area and a second switch isolation area;
forming a current diffusion layer on the voltage channel layer, and forming a first source doping layer, a second source doping layer, a plurality of isolation structures and a plurality of gate region channel structures on two sides of the current diffusion layer; the first source doping layer is positioned on the first switch isolation region and connected with the current diffusion layer through the gate region channel structure, and the second source doping layer is positioned on the second switch isolation region and connected with the current diffusion layer through the gate region channel structure;
forming a gate metal layer on the gate region channel structure; the gate metal layer is insulated from the gate region channel structure;
forming a schottky metal layer on the current diffusion layer; the Schottky metal layer and the current diffusion layer form Schottky contact;
and forming a drain metal layer on the back surface of the silicon carbide substrate.
In one embodiment, the forming a schottky metal layer on the current diffusion layer includes:
depositing a Schottky metal material on the current diffusion layer, and etching the Schottky metal material to form a first Schottky metal region and a second Schottky metal region which are not contacted with each other; the first Schottky metal region is in contact with the gate region channel structure close to the first source doping layer, and the second Schottky metal region is in contact with the gate region channel structure close to the second source doping layer.
In one embodiment, the first schottky metal region and the second schottky metal region are disposed in parallel and the lengths of the first schottky metal region and the second schottky metal region are the same.
In one embodiment, the widths of the first and second schottky metal regions are the same.
In one embodiment, a width of a gap between the first schottky metal region and the second schottky metal region is greater than a width of the first schottky metal region and the second schottky metal region.
In one embodiment, the forming a current diffusion layer on the voltage channel layer and forming a first source doped layer, a second source doped layer, a plurality of isolation structures and a plurality of gate channel structures on two sides of the current diffusion layer includes:
epitaxially growing an N-type epitaxial layer on the voltage channel layer and the P-type switch isolation layer;
etching a first preset etching area on the N-type epitaxial layer to form a plurality of first etching deep grooves and a plurality of first grid region channel structures, and etching a second preset etching area on the N-type epitaxial layer to form a plurality of second etching deep grooves and a plurality of second grid region channel structures so as to form the current diffusion layer, the first source doping layer and the second source doping layer on the voltage channel layer; the first source doping layer and the current diffusion layer are positioned on two sides of the first gate region channel structure, and the second source doping layer and the current diffusion layer are positioned on two sides of the second gate region channel structure.
In one embodiment, the forming a current diffusion layer on the voltage channel layer, and forming a first source doped layer, a second source doped layer, a plurality of isolation structures, and a plurality of gate channel structures on two sides of the current diffusion layer further includes:
depositing a P-type semiconductor material in the first etching deep groove to form a first isolation structure;
and depositing a P-type semiconductor material in the second etched deep groove to form a second isolation structure.
In one embodiment, the current spreading layer, the first source doping layer and the second source doping layer are arranged in parallel. The second aspect of the embodiment of the application also provides a silicon carbide-based FINFET power device, which is prepared by adopting the preparation method of any one of the above.
The third aspect of the embodiment of the application also provides a chip, and the vertical transistor prepared by the preparation method according to any one of the above is integrated in the chip.
Compared with the prior art, the embodiment of the application has the beneficial effects that: through epitaxial growth N type drift layer and P type switch isolation layer in proper order in the front of carborundum substrate, P type switch isolation layer is divided into first switch isolation region and second switch isolation region by the voltage channel layer, form the electric current diffusion layer on the voltage channel layer, and form first source doping layer in electric current diffusion layer both sides, second source doping layer, a plurality of isolation structures and a plurality of gate region channel structures, form the gate metal layer on gate region channel structure, pass through gate metal layer and fin-shaped structured gate region channel structure induction and obtain a plurality of electric current channels and reach the source, and pass through forming schottky metal layer on the electric current diffusion layer, integrate schottky diode in the device with minimum cost and chip area occupied, the switching speed and the reliability of carborundum FINFET power device have been promoted.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a vertical transistor according to an embodiment of the present application;
FIG. 2 is a schematic diagram of forming an N-type drift layer 200 and a P-type switch spacer 300 according to one embodiment of the present application;
FIG. 3 is a schematic diagram of forming a voltage channel layer 210 according to one embodiment of the present application;
FIG. 4 is a schematic illustration of forming a current spreading layer 830 in accordance with one embodiment of the present application;
FIG. 5 is a schematic flow chart of step S30 according to an embodiment of the present application;
FIG. 6 is a schematic diagram of an epitaxial growth process in a voltage channel layer 210 and a P-type switch isolation layer according to one embodiment of the present application;
FIG. 7 is a schematic illustration of forming a first isolation structure 312 and a second isolation structure 322 according to an embodiment of the present application;
FIG. 8 is another flow chart of step S30 provided by one embodiment of the present application;
fig. 9 is a schematic diagram of a first structure of a vertical transistor according to an embodiment of the present application;
FIG. 10 is a schematic diagram of a first current flow of a vertical transistor according to one embodiment of the present application;
fig. 11 is a schematic diagram of a first structure of a vertical transistor according to an embodiment of the present application;
fig. 12 is a second current schematic diagram of a vertical transistor according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is one or more than one unless specifically defined otherwise.
Reference in the specification to "one embodiment," "some embodiments," or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in a specific embodiment," "in a specific application," or the like in various places throughout this specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless specifically emphasized otherwise. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The BV of the power transistor is a very important parameter, and in order to increase the BV while saving chip area, the power transistor is converted from a planar structure to a vertical structure. Fin transistors (FINFETs) have been successfully invented to demonstrate the feasibility of CMOS processes on 14nm processes, even 3-5nm processes. However, in a vertical FinFET power device, the surge current generated by the device turn-off is typically drained by a parasitic body diode within the device, which is fragile, with a large negative impact on the reliability of the device. In order to solve the above technical problems, the embodiment of the application provides a method for manufacturing a silicon carbide-based FINFET power device, as shown in fig. 1, the method includes steps S10 to S50.
As shown in fig. 2, in step S10, an N-type drift layer 200 and a P-type switch isolation layer 300 are sequentially epitaxially grown on the front surface of a silicon carbide substrate 100.
In this embodiment, the N-type drift layer 200 is formed on the front surface of the silicon carbide substrate 100, the P-type switch isolation layer 300 is formed on the surface of the N-type drift layer 200, and the silicon carbide substrate 100 is an N-type semiconductor.
In one embodiment, the silicon carbide substrate 100 may be intrinsic silicon carbide or a P-doped silicon carbide material, or an N-doped silicon carbide material.
Referring to fig. 3, in step S20, N-type doping is performed on the designated area of the P-type switch isolation layer 300 to form the voltage channel layer 210, so as to divide the P-type switch isolation layer 300 into the first switch isolation region 311 and the second switch isolation region 321.
The designated area of the P-type switch isolation layer 300 is N-doped to form a voltage channel layer 210, and the P-type switch isolation layer 300 is divided into a first switch isolation region 311 and a second switch isolation region 321 by the voltage channel layer 210.
In one embodiment, the voltage channel layer 210 may be formed in the P-type switch isolation layer 300 by implanting N-type dopant ions into a central region of the P-type switch isolation layer 300, the first switch isolation region 311 and the second switch isolation region 321 are respectively located at both sides of the voltage channel layer 210, and the first switch isolation region 311 and the second switch isolation region 321 are not in contact with each other.
In one embodiment, the first switch isolation region 311 and the second switch isolation region 321 are symmetrically disposed about the voltage channel layer 210 as an axis of symmetry.
As shown in fig. 4, in step S30, a current diffusion layer 830 is formed on the voltage channel layer 210, and a first source doping layer 810, a second source doping layer 820, and a plurality of isolation structures and gate channel structures alternately arranged are formed on both sides of the current diffusion layer 830.
In this embodiment, the current diffusion layer 830 is located on the voltage channel layer 210, the first source doped layer 810 is located on the first switch isolation region 311, the first source doped layer 810 is connected to the current diffusion layer 830 through the gate channel structure, the second source doped layer 820 is located on the second switch isolation region 321, and the second source doped layer 820 is connected to the current diffusion layer 830 through the gate channel structure.
In one embodiment, the first source doped layer 810 and the current diffusion layer 830 are connected by a plurality of first gate channel structures 410, and the second source doped layer 820 and the current diffusion layer 830 are connected by a plurality of second gate channel structures 420.
In one embodiment, referring to fig. 5, in step S30, a current diffusion layer 830 is formed on a voltage channel layer 210, and a first source doping layer 810, a second source doping layer 820, and a plurality of isolation structures and gate channel structures alternately arranged are formed on both sides of the current diffusion layer 830, including steps S311 to S312.
In step S311, an N-type epitaxial layer 400 is epitaxially grown on the voltage channel layer 210 and the P-type switch isolation layer 300.
In this embodiment, referring to fig. 6, an N-type epitaxial layer 400 is epitaxially grown on the voltage channel layer 210 and the P-type switch isolation layers (i.e., the first switch isolation region 311 and the second switch isolation region 321) using an N-type semiconductor material epitaxial growth process.
In step S312, the first preset etching region on the N-type epitaxial layer 400 is etched to form a plurality of first etched deep trenches 301 and a plurality of first gate channel structures 410, and the second preset etching region on the N-type epitaxial layer 400 is etched to form a plurality of second etched deep trenches 302 and a plurality of second gate channel structures 420, so as to form a current diffusion layer 830, a first source doped layer 810 and a second source doped layer 820 on the voltage channel layer 210.
In this embodiment, as shown in fig. 4, a plurality of first etching deep grooves 301 are formed by etching a first preset etching region on the N-type epitaxial layer 400, the first etching deep grooves 301 extend into the first switch isolation region 311, so that the N-type epitaxial layer 400 on the first switch isolation region 311 is divided into a plurality of first gate channel structures 410, a first source doped layer 810 and a current diffusion layer 830, the first source doped layer 810 and the current diffusion layer 830 are located at two sides of the plurality of first gate channel structures 410, a plurality of second etching deep grooves 302 are formed by etching a second preset etching region on the N-type epitaxial layer 400, the second etching deep grooves 302 extend into the second switch isolation region 321, and the N-type epitaxial layer 400 on the second switch isolation region 321 is divided into a second gate channel structure 420, a second source doped layer 820 and the current diffusion layer 830, and the second source doped layer 820 and the current diffusion layer 830 are located at two sides of the second gate channel structures 420.
In one embodiment, the first etched deep trench 301 extends into the first switch isolation region 311 such that adjacent first gate channel structures 410 are not in contact with each other, and the second etched deep trench 302 extends into the second switch isolation region 321 such that adjacent second gate channel structures 420 are not in contact with each other.
In this embodiment, as shown in fig. 7, the first etched deep trench 301 extends into the first switch isolation region 311, and the second etched deep trench 302 extends into the second switch isolation region 321.
In some embodiments, referring to fig. 8, step S30 further includes steps S313 to S314.
In step S313, a P-type semiconductor material is deposited in the first etched deep trench 301 to form a first isolation structure 312 in contact with the first switch isolation region 311.
In this embodiment, the first isolation structure 312 is formed by filling the P-type doped material into the first etched deep trench 301 under the cover of the P-type doped mask, the first source doped layer 810 and the current diffusion layer 830 are located at two sides of the first isolation structure 312, and the first source doped layer 810 and the current diffusion layer 830 are both in contact with the first isolation structure 312.
In step S314, a P-type semiconductor material is deposited in the second etched deep trench 302 to form a second isolation structure 322 in contact with the second switch isolation region 321.
In this embodiment, the second isolation structure 322 is formed by filling the P-type doped material into the second etched deep trench 302 under the cover of the P-type doped mask, and since the second etched deep trench 302 extends deep into the second switch isolation region 321, the N-type epitaxial layer 400 at the position of the second source doped layer 820 and the current diffusion layer 830 is not etched, so that the second source doped layer 820 and the current diffusion layer 830 are located at two sides of the second isolation structure 322, and the second source doped layer 820 and the current diffusion layer 830 are both in contact with the second isolation structure 322.
In this embodiment, as shown in fig. 9, the first etched deep trench 301 is deep into the first switch isolation region 311, the first isolation structure 312 is in contact with the first switch isolation region 311, the second etched deep trench 302 is deep into the second switch isolation region 321, and the second isolation structure 322 is in contact with the second switch isolation region 321.
In one embodiment, as shown in fig. 9, the number of the first isolation structures 312 may be plural, and the plural first isolation structures 312 are disposed in parallel, and are formed by filling the plural first etching deep trenches 301 with P-type doped material.
In one embodiment, as shown in connection with fig. 9, a first pre-set etch region is used to determine the location of the first isolation structure 312 in the N-type epitaxial layer 400, a second pre-set etch region is used to determine the location of the second isolation structure 322 in the N-type epitaxial layer 400, and the structure between the first isolation structure 312 and the second isolation structure 322 is used as the current spreading layer 830 by determining the location of the first isolation structure 312 and the second isolation structure 322, so that the first pre-set etch region is located above the first isolation structure 312, the second pre-set etch region is located above the second isolation structure 322, and the current spreading layer 830 is located between the first pre-set etch region and the second pre-set etch region.
In one embodiment, the plurality of first isolation structures 312 are disposed in parallel.
In one embodiment, the widths of the plurality of first isolation structures 312 are equal.
In one embodiment, the plurality of second isolation structures 322 are disposed in parallel.
In one embodiment, the widths of the plurality of second isolation structures 322 are equal.
In one embodiment, an N-type semiconductor material is epitaxially grown under a first mask over the voltage channel layer 210 and the P-type switch spacer layer 300 to form a current spreading layer 830, a first gate channel structure 410, a second gate channel structure 420, a first source doping layer 810, and a second source doping layer 820.
In this embodiment, the positions of the current diffusion layer 830, the first gate channel structure 410, the second gate channel structure 420, the first source doped layer 810 and the second source doped layer 820 are defined by a first mask, and then an N-type semiconductor material is deposited or an N-type semiconductor material is epitaxially grown under the mask of the first mask, so that the current diffusion layer 830 is formed on the voltage channel layer 210, a plurality of first gate channel structures 410 and first source doped layers 810 are formed on the first switch isolation region 311, and a plurality of second gate channel structures 420 and second source doped layers 820 are formed on the second switch isolation region 321.
In the present embodiment, the first source doping layer 810 and the current diffusion layer 830 are located at both sides of the first gate channel structure 410, and the second source doping layer 820 and the current diffusion layer 830 are located at both sides of the second gate channel structure 420.
In one embodiment, the N-type semiconductor material may be N-type silicon carbide, N-type silicon, or N-type gallium nitride.
In one embodiment, first gate channel structures contacting the first switch isolation regions are formed between adjacent first gate channel structures 410 under the mask of the second mask, and second isolation structures 322 contacting the second switch isolation regions 321 are formed between adjacent second gate channel structures 420.
In this embodiment, the second mask is used to cover the current diffusion layer 830, the first gate channel structure 410, the second gate channel structure 420, the first source doped layer 810 and the second source doped layer 820, by depositing a P-type semiconductor material under the mask of the second mask, the first isolation structure 312 contacting the first switch isolation region 311 is formed between the adjacent first gate channel structures 410, and the second isolation structure 322 contacting the second switch isolation region 321 is formed between the adjacent second gate channel structures 420.
In one embodiment, the P-type semiconductor material may be P-type silicon carbide, P-type silicon, or P-type gallium nitride.
In one embodiment, to increase the thicknesses of the current spreading layer 830, the first gate channel structure 410, the second gate channel structure 420, the first source doping layer 810, and the second source doping layer 820, the above-described steps S321 and S322 may be alternately performed, and the N-type semiconductor material and the P-type semiconductor material may be alternately epitaxially grown using the first mask and the second mask, thereby increasing the thicknesses of the current spreading layer 830, the first gate channel structure 410, the second gate channel structure 420, the first source doping layer 810, the second source doping layer 820, the first isolation structure 312, and the second isolation structure 322 by a multiple epitaxial manufacturing process.
In one embodiment, the first gate channel structure 410 is located on both sides of the first isolation structure 312 and the second gate channel structure 420 is located on both sides of the second isolation structure 322.
In one embodiment, the plurality of first gate channel structures 410 are disposed in one-to-one correspondence with the plurality of second gate channel structures 420.
In one embodiment, the first gate channel structure 410 is the same width as the second gate channel structure 420.
In one embodiment, the voltage resistance of the device can be improved by designing the thickness of the wafer, so that the width of the device is increased by matching with the switch of the vertical transistor, and the purposes of realizing high current density and high breakdown voltage under the same chip area are achieved. Although there are more current spreading layers 830 than in the general device design, more high aspect ratio techniques can be introduced as the process evolves, and thus the vertical transistor in this embodiment has a deeper development potential.
In step S40, a gate metal layer is formed on the gate channel structure.
In this embodiment, a gate metal layer is formed on the first isolation structure 312 and the second isolation structure 322, and is insulated from the first gate channel structure 410 and the second gate channel structure 420.
In one embodiment, a first gate metal layer is formed on the first isolation structure 312 and a second gate metal layer is formed on the second isolation structure 322.
In step S50, a schottky metal layer 600 is formed on the current diffusion layer 830 as shown in fig. 9.
In this embodiment, schottky contacts are formed between the schottky metal layer 600 and the current spreading layer 830 to integrate schottky diodes within the vertical FinFET power device. In some embodiments, the schottky metal layer 600 is connected to the source electrode, so that the anode of the schottky diode is connected to the source electrode of the device, the cathode of the schottky diode is connected to the drain electrode of the device, and the schottky diode is connected in series between the source electrode and the drain electrode of the device, so as to improve the reverse recovery characteristic of the MOSFET, thereby improving the switching speed of the device, and the current flow diagram of the vertical FinFET power device in this embodiment during operation is shown in fig. 10.
In some embodiments, integrating a schottky diode (SBD) in the region of the current spreading layer 830 may reduce the cost and chip area of the device due to device structure limitations of the vertical FinFET power device.
In some embodiments, the overall integration of the SBD in the region of the current spreading layer 830 may increase negative effects, reduce performance of the vertical FinFET power device, such as possible leakage or increase on-voltage of the device. As can be seen from the current flow diagram shown in fig. 10, most of the schottky metal in the middle of the schottky metal layer 600 has no effect, so as shown in fig. 11, a split schottky metal structure is proposed in this embodiment, and the schottky metal layer 600 is composed of the first schottky metal region 610 and the second schottky metal region 620, so that the fin-shaped switching MOSFET device of the vertical FinFET power device has the benefit of increasing the switching speed of the SBD while reducing the negative effect as much as possible, and the current flow diagram of the vertical FinFET power device in fig. 11 is shown in fig. 12, so that the schottky metal layer 600 is designed into the split schottky metal structure and does not affect the current relationship.
In some embodiments, the first schottky metal region 610 and the second schottky metal region 620 that are not in contact with each other may be formed by depositing a schottky metal material on the current spreading layer 830 and etching the deposited schottky metal material 。
In this embodiment, as shown in conjunction with fig. 10, the first schottky metal region 610 is in contact with the first gate region channel structure 410 adjacent to the first source doped layer 810 and the second schottky metal region 620 is in contact with the second gate region channel structure 420 adjacent to the second source doped layer 820.
In some embodiments, the first gate channel structure 410 and the second gate channel structure 420 are a MOS structure, and in operation, a vertical FinFET power device has current flowing from the drain to the current spreading layer 830, through the gate regions (the first gate channel structure 410 and the second gate channel structure 420) of the FinFET, and the gate periphery induces a channel through which current flows to the source of the device.
In step S60, a drain metal layer 850 is formed on the back surface of the silicon carbide substrate 100.
In the present embodiment, as shown in fig. 9, the drain metal layer 850 may be formed in a partial region of the back surface of the silicon carbide substrate 100 or entirely cover the back surface of the silicon carbide substrate 100.
In one embodiment, the current spreading layer 830, the first source doping layer 810, and the second source doping layer 820 are disposed in parallel.
In one embodiment, the first isolation structure 312 and the first switch isolation region 311 are P-doped semiconductors, the first gate channel structure 410 and the first isolation structure 312 are alternately arranged to form a fin-shaped JFET structure, the first switch isolation region 311 is further used to isolate the first gate channel structure 410 and the N-type drift layer 200, for example, an enhancement vertical transistor device is used, a high voltage is connected to the first gate metal layer, so that a depletion region of the JFET structure under the fin-shaped gate can be reduced, the device is turned on, and if the voltage connected to the first gate metal layer is less than a turn-off threshold voltage, the depletion region of the JFET structure under the fin-shaped gate can be kept unchanged, so that the device is turned off.
In practical applications, if the transistor device is a depletion normally-on device, a negative voltage needs to be applied to the first gate metal layer, so that the transistor is turned off.
And so on, the fin JFET structure formed by the second switch isolation region 321, the second source doped layer 820, the current diffusion layer 830, the second isolation structure 322, and the second gate channel structure 420 has the same operation mechanism.
The embodiment of the application also provides a silicon carbide-based FINFET power device, which is prepared by adopting the preparation method according to any one of the embodiments.
The embodiment of the application also provides a chip, and the vertical transistor prepared by the preparation method according to any one of the above is integrated in the chip.
In one embodiment, the vertical transistor prepared by the preparation method described in the above embodiment is integrated in the chip.
In this embodiment, the chip includes a chip substrate, and one or more vertical transistors are disposed on the substrate, where the vertical transistors may be prepared by the preparation method in any of the foregoing embodiments, or the vertical transistors in any of the foregoing embodiments may be disposed on the chip substrate.
In one specific application embodiment, other related semiconductor devices may also be integrated on the chip substrate to form integrated circuits with the vertical transistors.
In one specific application embodiment, the chip may be a switching chip or a driving chip.
Compared with the prior art, the embodiment of the application has the beneficial effects that: through epitaxial growth N type drift layer and P type switch isolation layer in proper order in the front of carborundum substrate, P type switch isolation layer is divided into first switch isolation region and second switch isolation region by the voltage channel layer, form the electric current diffusion layer on the voltage channel layer, and form first source doping layer in electric current diffusion layer both sides, second source doping layer, a plurality of isolation structures and a plurality of gate region channel structures, form the gate metal layer on gate region channel structure, pass through gate metal layer and fin-shaped structured gate region channel structure induction and obtain a plurality of electric current channels and reach the source, and pass through forming schottky metal layer on the electric current diffusion layer, integrate schottky diode in the device with minimum cost and chip area occupied, the switching speed and the reliability of carborundum FINFET power device have been promoted.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the doped regions is illustrated, and in practical application, the above-described allocation of the functional regions may be performed by different doped regions, i.e. the internal structure of the device is divided into different doped regions, so as to perform all or part of the above-described functions.
In the embodiment, each doped region may be integrated in one functional region, or each doped region may exist physically alone, or two or more doped regions may be integrated in one functional region, where the integrated functional regions may be implemented by using the same doping ion, or may be implemented by using multiple doping ions together. In addition, the specific names of the doped regions are also only for distinguishing from each other, and are not used to limit the protection scope of the present application. The specific working process of the middle doped region in the method for manufacturing a device may refer to the corresponding process in the foregoing method embodiment, and will not be described herein.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. A method of fabricating a silicon carbide-based FINFET power device, the method comprising:
sequentially epitaxially growing an N-type drift layer and a P-type switch isolation layer on the front surface of the silicon carbide substrate;
n-type doping is carried out on the appointed area of the P-type switch isolation layer to form a voltage channel layer so as to divide the P-type switch isolation layer into a first switch isolation area and a second switch isolation area;
forming a current diffusion layer on the voltage channel layer, and forming a first source doping layer, a second source doping layer, a plurality of isolation structures and a plurality of gate region channel structures on two sides of the current diffusion layer; the first source doping layer is positioned on the first switch isolation region and connected with the current diffusion layer through the gate region channel structure, and the second source doping layer is positioned on the second switch isolation region and connected with the current diffusion layer through the gate region channel structure;
forming a gate metal layer on the gate region channel structure; the gate metal layer is insulated from the gate region channel structure;
forming a schottky metal layer on the current diffusion layer; the Schottky metal layer and the current diffusion layer form Schottky contact;
and forming a drain metal layer on the back surface of the silicon carbide substrate.
2. The method of manufacturing of claim 1, wherein forming a schottky metal layer on the current spreading layer comprises:
depositing a Schottky metal material on the current diffusion layer, and etching the Schottky metal material to form a first Schottky metal region and a second Schottky metal region which are not contacted with each other; the first Schottky metal region is in contact with the gate region channel structure close to the first source doping layer, and the second Schottky metal region is in contact with the gate region channel structure close to the second source doping layer.
3. The method of manufacturing of claim 1, wherein the first schottky metal region and the second schottky metal region are disposed in parallel and the lengths of the first schottky metal region and the second schottky metal region are the same.
4. A method of manufacturing as claimed in claim 2 or 3 wherein the widths of the first and second schottky metal regions are the same.
5. The method of manufacturing of claim 2 or 3, wherein a width of a gap between the first schottky metal region and the second schottky metal region is greater than a width of the first schottky metal region and the second schottky metal region.
6. The method of manufacturing of claim 1, wherein forming a current diffusion layer on the voltage channel layer and forming a first source doped layer, a second source doped layer, a plurality of isolation structures, and a plurality of gate channel structures on both sides of the current diffusion layer comprises:
epitaxially growing an N-type epitaxial layer on the voltage channel layer and the P-type switch isolation layer;
etching a first preset etching area on the N-type epitaxial layer to form a plurality of first etching deep grooves and a plurality of first grid region channel structures, and etching a second preset etching area on the N-type epitaxial layer to form a plurality of second etching deep grooves and a plurality of second grid region channel structures so as to form the current diffusion layer, the first source doping layer and the second source doping layer on the voltage channel layer; the first source doping layer and the current diffusion layer are positioned on two sides of the first gate region channel structure, and the second source doping layer and the current diffusion layer are positioned on two sides of the second gate region channel structure.
7. The method of manufacturing of claim 6, wherein forming a current diffusion layer on the voltage channel layer and forming a first source doped layer, a second source doped layer, a plurality of isolation structures, and a plurality of gate channel structures on both sides of the current diffusion layer, further comprises:
depositing a P-type semiconductor material in the first etching deep groove to form a first isolation structure;
and depositing a P-type semiconductor material in the second etched deep groove to form a second isolation structure.
8. The method of any one of claims 2-7, wherein the current spreading layer, the first source doping layer, and the second source doping layer are disposed in parallel.
9. A silicon carbide based FINFET power device prepared by the method of any of claims 1-8.
10. A chip, wherein the vertical transistor prepared by the preparation method of any one of claims 1-8 is integrated in the chip.
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