CN116825824B - LDMOS device of silicon carbide and silicon heterojunction and manufacturing method - Google Patents
LDMOS device of silicon carbide and silicon heterojunction and manufacturing method Download PDFInfo
- Publication number
- CN116825824B CN116825824B CN202311096893.XA CN202311096893A CN116825824B CN 116825824 B CN116825824 B CN 116825824B CN 202311096893 A CN202311096893 A CN 202311096893A CN 116825824 B CN116825824 B CN 116825824B
- Authority
- CN
- China
- Prior art keywords
- region
- silicon carbide
- silicon
- conductive type
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 133
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 130
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 86
- 239000010703 silicon Substances 0.000 title claims abstract description 86
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 77
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 210000000746 body region Anatomy 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 35
- 229920005591 polysilicon Polymers 0.000 claims description 35
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 16
- 230000007704 transition Effects 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 20
- 239000000969 carrier Substances 0.000 abstract description 7
- 238000009825 accumulation Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 230000007774 longterm Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910008065 Si-SiO Inorganic materials 0.000 description 1
- 229910008062 Si-SiO2 Inorganic materials 0.000 description 1
- 229910006405 Si—SiO Inorganic materials 0.000 description 1
- 229910006403 Si—SiO2 Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application relates to the field of semiconductors, and provides an LDMOS device of silicon carbide and silicon heterojunction and a manufacturing method thereof. The LDMOS device comprises: the semiconductor device includes a silicon substrate, a first conductivity type well region, a second conductivity type body region, a first conductivity type drift region, a source region, a drain region, and a gate structure, and further includes: a buried layer of a second conductivity type; the second conductive type buried layer and the second conductive type body region are made of silicon, and the first conductive type drift region and the first conductive type drain region are made of silicon carbide; the first conductive type drift region is longitudinally connected with the second conductive type buried layer so as to form a heterojunction of silicon carbide and silicon in a longitudinally connected interface region in a conductive state; the first conductivity type drift region laterally interfaces with the second conductivity type body region to form a silicon carbide to silicon heterojunction at a laterally interface region in a conductive state. The application utilizes the longitudinal and transverse double heterojunctions to improve the breakdown voltage of the device, improve the mobility of carriers and reduce the on-resistance.
Description
Technical Field
The application relates to the field of semiconductors, in particular to an LDMOS device with silicon carbide and silicon heterojunction, a manufacturing method of the LDMOS device with silicon carbide and silicon heterojunction and a power chip.
Background
With the rapid development of clean energy in recent years, related power electronic devices have put higher demands on indexes such as working voltage and power density. The conventional Si-based LDMOS (Lateral Double-diffused MOSFET) power device is not beneficial to further improving the performance due to the limitation of the forbidden bandwidth, the temperature characteristic, the critical breakdown electric field and other characteristics of the Si material. Compared with Si materials, the SiC material has the characteristics of wide forbidden band, high breakdown field strength, high saturated electron velocity, high thermal conductivity, good chemical stability, strong irradiation resistance and the like, is an ideal material for realizing high-performance power devices, and an LDMOS device manufactured by using a single SiC epitaxial substrate has high cost, has poor compatibility with the traditional Si-based semiconductor process and is not beneficial to improving the integration level of the device.
The breakdown voltage and the on-resistance of the LDMOS device are the most important electrical parameters, and the improvement of the breakdown voltage and the reduction of the on-resistance are important indexes. In the prior art, a Shallow Trench Isolation (STI) structure or a field oxide layer structure is arranged on the surface of an LDMOS drift region to improve the breakdown voltage of a device, but the problem of increasing on-resistance is also brought, and the interface state accumulation of Si-SiO2 at the interface of the STI isolation trench or the field oxide layer structure and a Si substrate can cause long-term degradation of the performance of the device.
How to improve the LDMOS structure by utilizing the characteristics of SiC materials and how to manufacture an LDMOS device by utilizing the SiC materials on the basis of the traditional Si-based semiconductor process are the problems to be solved at present.
Disclosure of Invention
The application aims to provide an LDMOS device of silicon carbide and silicon heterojunction and a manufacturing method thereof, so as to improve breakdown voltage of the device and reduce on-resistance.
To achieve the above object, an aspect of the present application provides an LDMOS device of silicon carbide-silicon heterojunction, comprising: the semiconductor device includes a silicon substrate, a first conductivity type well region, a second conductivity type body region, a first conductivity type drift region, a source region, a drain region, and a gate structure, and further includes: a buried layer of a second conductivity type;
the second conductive type buried layer and the second conductive type body region are made of silicon, and the first conductive type drift region and the drain region are made of silicon carbide;
the first conductive type drift region is longitudinally connected with the second conductive type buried layer so as to form a heterojunction of silicon carbide and silicon in a longitudinally connected interface region in a conductive state;
the first conductivity type drift region is laterally contiguous with the second conductivity type body region to form a silicon carbide to silicon heterojunction at a laterally contiguous interface region in a conductive state.
In an embodiment of the present application, the first conductivity type drift region includes: a first conductivity type ion doped silicon carbide drift region and an undoped silicon carbide transition region; the first conductive type ion doped silicon carbide drift region is longitudinally connected with the second conductive type buried layer and is transversely connected with the second conductive type body region; the undoped silicon carbide transition region is positioned on the surface of the first-conductivity-type ion-doped silicon carbide drift region and is laterally connected with the second-conductivity-type body region.
In the embodiment of the application, a first conductivity type accumulation region is arranged between the first conductivity type drift region and the second conductivity type body region.
In an embodiment of the present application, the gate structure includes: the polysilicon gate electrode, the gate oxide layer and the silicon nitride side wall are arranged between the polysilicon gate electrode and the second conductive type body region, and the silicon nitride side wall is arranged on two sides of the polysilicon gate electrode.
In an embodiment of the present application, the LDMOS device further includes: the substrate electrode is connected with the source region, and the metal electrode is arranged on the surfaces of the substrate electrode, the source region, the drain region and the polysilicon gate.
In another aspect, the present application provides a method for manufacturing an LDMOS device having a silicon carbide-silicon heterojunction, including:
ion implantation is carried out on the silicon substrate to form a first conductive type well region;
forming a groove above the first conductive type well region, and epitaxially growing silicon carbide inside and outside the groove to form a silicon carbide drift region;
forming a buried layer of a second conductivity type in a longitudinal region adjacent to the silicon carbide drift region and forming a body region of the second conductivity type in a lateral region adjacent to the silicon carbide drift region;
and forming a grid structure and a source region on the surface of the second conductive type body region, and forming a drain region on the surface of the silicon carbide drift region.
In an embodiment of the present application, the ion implantation of the first conductivity type well region into the silicon substrate includes: and selecting a P-type silicon substrate, and injecting N-type ions into a preset area of the P-type silicon substrate to form an N-type well region.
In an embodiment of the present application, a trench is formed above a well region of a first conductivity type, and silicon carbide is epitaxially grown inside the trench to form a silicon carbide drift region, including: etching the silicon substrate, and forming a groove above the first conductive type well region; epitaxially growing first-conductivity-type ion-doped silicon carbide in the groove by adopting a chemical vapor deposition method to form a first-conductivity-type ion-doped silicon carbide drift region; and epitaxially growing undoped silicon carbide on the surface of the first-conductivity-type ion-doped silicon carbide drift region to form an undoped silicon carbide transition region.
In an embodiment of the present application, the forming a gate structure on the surface of the second conductive type body region includes: forming a gate oxide layer on the surface of the second conductive type body region by adopting a thermal oxidation method; depositing polysilicon on the surface of the gate oxide layer to form a polysilicon gate; and depositing silicon nitride on the surface of the polysilicon gate, etching the silicon nitride, and reserving the silicon nitride on two sides of the polysilicon gate to form a silicon nitride side wall.
In an embodiment of the present application, the method for manufacturing an LDMOS device with a heterojunction between silicon carbide and silicon further includes: a first conductivity type accumulation region is formed between the silicon carbide drift region and the second conductivity type body region.
In an embodiment of the present application, the ion doping concentration of the silicon carbide drift region is 1×10 16 ~1×10 17 cm -3 The ion doping concentration of the second conductive type buried layer is 3×10 17 ~6×10 17 cm -3 The ion doping concentration of the second conductive type body region is 1×10 17 ~5×10 17 cm -3 。
The application also provides a power chip which comprises the LDMOS device of the silicon carbide-silicon heterojunction.
According to the application, the traditional LDMOS structure is improved, the drift region and the drain region are made of silicon carbide materials, and the buried layer is arranged below the body region and the silicon carbide drift region, so that a heterojunction of silicon carbide and silicon is formed in an interface region where the drift region and the buried layer are longitudinally connected, and a heterojunction of silicon carbide and silicon is formed in an interface region where the drift region and the body region are transversely connected, namely, a longitudinal double heterojunction and a transverse double heterojunction are formed, the breakdown voltage of the device is improved, the mobility of carriers is improved, and the on-resistance is reduced; because the drain electrode and the drift region of the LDMOS are main voltage-resistant regions of the device, and silicon carbide (SiC) has high breakdown field strength characteristics, the drift region and the drain region of the SiC material can remarkably improve the breakdown voltage and long-term reliability of the device.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the embodiments of the application. In the drawings:
fig. 1 is a schematic structural diagram of an LDMOS device with silicon carbide and silicon heterojunction according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an LDMOS device with a silicon carbide-silicon heterojunction according to a second embodiment of the present application;
fig. 3 is a flowchart of a method for manufacturing an LDMOS device with a silicon carbide-silicon heterojunction according to an embodiment of the present application;
fig. 4a is a schematic structural diagram of a well region formed in the manufacturing method according to the embodiment of the present application;
FIG. 4b is a schematic diagram of a silicon carbide drift region formed in a method of fabrication according to an embodiment of the present application;
fig. 4c is a schematic structural diagram of a buried layer and a body region formed in the manufacturing method according to the embodiment of the present application;
fig. 4d is a schematic structural diagram of an LDMOS device formed by the manufacturing method according to the embodiment of the application.
Description of the reference numerals
A 101-P type silicon substrate, a 102-N type well region, a 103-P type buried layer, a 104-P type body region,
105a-N type ion doped silicon carbide drift region, 105 b-undoped silicon carbide transition region,
106-N type accumulation region, 107-polysilicon gate, 108-gate oxide, 109-silicon nitride sidewall,
110-substrate electrode, 111-source region, 112-drain region, 113-metal electrode.
Detailed Description
The following describes specific embodiments of the present application in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the application, are not intended to limit the application.
In the description herein, it should be understood that the terms "center," "longitudinal," "transverse," "upper," "lower," "front," "rear," "left," "right," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate describing the application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the application. In this document, unless explicitly stated and limited otherwise, the terms "connected," "connected," and the like are to be construed broadly, and may be, for example, directly connected or indirectly connected via an intermediary, may be in communication with each other within two structures or regions, or may be in an interaction relationship between two structures or regions. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.
The embodiment of the application provides an LDMOS device of silicon carbide and silicon heterojunction, which comprises: a silicon substrate, a first conductivity type (N) well region, a second conductivity type (P) buried layer, a second conductivity type (P) body region, a first conductivity type (N) drift region, a source region, a drain region and a gate structure. The second conductive type buried layer and the second conductive type body region are made of silicon, and the first conductive type drift region and the first conductive type drain region are made of silicon carbide. The first conductive type drift region is longitudinally connected with the second conductive type buried layer so as to form a heterojunction of silicon carbide and silicon in a longitudinally connected interface region in a conductive state; the first conductivity type drift region laterally interfaces with the second conductivity type body region to form a silicon carbide to silicon heterojunction at a laterally interface region in a conductive state. According to the application, the traditional LDMOS structure is improved, the drift region and the drain region are made of silicon carbide materials, and the buried layer is arranged below the body region and the silicon carbide drift region, so that a heterojunction of silicon carbide and silicon is formed in an interface region where the drift region and the buried layer are longitudinally connected, and a heterojunction of silicon carbide and silicon is formed in an interface region where the drift region and the body region are transversely connected, namely, a longitudinal double heterojunction and a transverse double heterojunction are formed, the breakdown voltage of the device is improved, the mobility of carriers is improved, and the on-resistance is reduced; because the drain electrode and the drift region of the LDMOS are main voltage-resistant regions of the device, and silicon carbide (SiC) has high breakdown field strength characteristics, the drift region and the drain region of the SiC material can remarkably improve the breakdown voltage and long-term reliability of the device.
The LDMOS device comprises an N-type LDMOS device (NLDMOS for short) and a P-type LDMOS device (PLDMOS for short). In the above description, the first conductivity type and the second conductivity type refer to two carrier types, i.e., P-type (carriers are holes) and N-type (carriers are electrons). In the LDMOS device described above, if the silicon substrate is a P-type silicon substrate, the first conductivity type is N-type, the second conductivity type is P-type, and the semiconductor device formed is NLDMOS; if the silicon substrate is an N-type silicon substrate, the first conductivity type is P-type, the second conductivity type is N-type, and the formed semiconductor device is PLDMOS. The technical scheme of the application is explained in detail below by taking NLDMOS devices as examples.
Fig. 1 is a schematic structural diagram of an LDMOS device with silicon carbide and silicon heterojunction according to an embodiment of the present application. As shown in fig. 1, the LDMOS device according to the embodiment includes a P-type silicon substrate 101, an N-type well region 102, a P-type buried layer 103, a P-type body region 104, an N-type drift region, a source region 111, a drain region 112, and a gate structure, wherein the materials of the N-type well region 102, the P-type buried layer 103, and the P-type body region 104 are all silicon, and the materials of the N-type drift region and the drain region 112 are all silicon carbide (SiC). The N-type drift region is longitudinally connected with the P-type buried layer 103, and in a conductive state, the interface region of the N-type drift region and the P-type buried layer 103, which is longitudinally connected, forms a heterojunction of silicon carbide and silicon; the N-type drift region is laterally contiguous with the P-type body region 104, and in the conductive state, the laterally contiguous interface region of the N-type drift region and the P-type body region 104 forms a silicon carbide to silicon heterojunction. According to the LDMOS device, the drift region and the drain region of the silicon carbide material are adopted to form the longitudinal double heterojunction and the transverse double heterojunction, so that the breakdown voltage of the device can be improved, the mobility of carriers is improved, and the on-resistance is reduced.
In this embodiment, the N-type drift region includes an N-type ion doped silicon carbide drift region 105a and an undoped silicon carbide transition region 105b. The N-type ion doped silicon carbide drift region 105a is longitudinally connected with the P-type buried layer 103 and is transversely connected with the P-type body region 104; undoped silicon carbide transition region 105b is located on the upper surface of N-type ion doped silicon carbide drift region 105a and laterally meets P-type body region 104. The drift region of the LDMOS device of this embodiment has a two-layer structure, the lower layer is N-doped SiC, the lower layer is used as a conductive channel of the drift region, the upper layer is undoped SiC, the buffer region and the voltage-withstanding region are made of SiC material, the critical breakdown field strength of the SiC material is ten times that of silicon material, the field plate (the field plate is used to increase the breakdown voltage) is required to be arranged when the Si material is used as the drift region can be avoided when the SiC material is used as the buffer region and the voltage-withstanding region, and the introduced Si-SiO 2 The interface may deteriorate the long-term reliability of the device, i.e., undoped SiC drift regions can significantly improve the long-term reliability of the device.
In the present embodiment, the gate structure includes a polysilicon gate 107, a gate oxide 108, and silicon nitride (Si 3 N 4 ) The sidewall 109, the gate oxide layer 108 is disposed between the polysilicon gate 107 and the P-type body region 104, and the silicon nitride sidewall 109 is disposed on two sides of the polysilicon gate 107. The LDMOS device further includes a substrate electrode 110 and a metal electrode 113, wherein the substrate electrode 110 is connected to the source region 111, and the metal electrode 113 is disposed on the surfaces of the substrate electrode 110, the source region 111, the drain region 112, and the polysilicon gate 107. The LDMOS device adopts a polysilicon gate and side wall technology compatible with a conventional CMOS device to form a silicon nitride side wall of a grid electrode, and local stress is introduced into a channel region by utilizing the silicon nitride side wall to improve the carrier mobility of the device.
Fig. 2 is a schematic structural diagram of an LDMOS device with a silicon carbide-silicon heterojunction according to a second embodiment of the present application. As shown in fig. 2, the LDMOS device improved in this embodiment includes a P-type silicon substrate 101, an N-type well region 102, a P-type buried layer 103, a P-type body region 104, an N-type drift region, an N-type accumulation region 106, a source region 111, a drain region 112, and a gate structure. The N-type accumulation region 106 is disposed between the N-type drift region and the gate structure, and the N-type well region 102, the P-type buried layer 103 and the P-type body region 104 are all made of silicon, and the N-type drift region and the drain region 112 are all made of silicon carbide. The N-type drift region is longitudinally connected with the P-type buried layer 103, and in a conductive state, an interface region where the N-type drift region is longitudinally connected with the P-type buried layer 103 forms a heterojunction of silicon carbide and silicon. The N-type drift region is laterally contiguous with the P-type body region 104, and in the conductive state, the laterally contiguous interface region of the N-type drift region and the P-type body region 104 forms a silicon carbide to silicon heterojunction. The N-type drift region comprises an N-type ion doped silicon carbide drift region 105a and an undoped silicon carbide transition region 105b, wherein the N-type ion doped silicon carbide drift region 105a is longitudinally connected with the P-type buried layer 103 and is transversely connected with the P-type body region 104; undoped silicon carbide transition region 105b is located on the upper surface of N-type ion doped silicon carbide drift region 105a and laterally meets P-type body region 104. The gate structure includes a polysilicon gate 107, a gate oxide layer 108, and a silicon nitride sidewall 109, wherein the gate oxide layer 108 is disposed between the polysilicon gate 107 and the P-type body region 104, and the silicon nitride sidewall 109 is disposed on two sides of the polysilicon gate 107. The LDMOS device further comprises a substrate electrode 110 and a metal electrode 113, wherein the substrate electrode 110 is connected with the source region 111, and the metal electrode 113 is arranged on the surfaces of the substrate electrode 110, the source region 111, the drain region 112 and the polysilicon gate 107.
In comparison with the first embodiment, the second embodiment adds the N-type accumulation region 106. The N-type accumulation region 106 is located between the N-type ion doped silicon carbide drift region 105a and the polysilicon gate 107, and serves as an electron accumulation layer therebetween, so that the conductivity of the device can be greatly improved, and the on-resistance of the device can be reduced.
The method for fabricating the LDMOS device of the silicon carbide-silicon heterojunction is described in detail below.
As shown in fig. 3, the method for manufacturing the LDMOS device with the silicon carbide-silicon heterojunction provided by the embodiment of the application comprises the following steps:
in step 201, ion implantation is performed on a silicon substrate into a well region of a first conductivity type.
Taking NLDMOS device as an example, a P-type silicon substrate is selected, and N-type ions are implanted into a predetermined region of the P-type silicon substrate 101 (ion doping concentration is 3×10) 16 ~1.5×10 17 cm -3 ) An N-type well region 102 is formed resulting in the structure shown in fig. 4 a.
And 202, forming a groove above the first conductive type well region, and epitaxially growing silicon carbide inside and outside the groove to form a silicon carbide drift region.
Specifically, the P-type silicon substrate 101 is etched, and a trench is formed above the N-type well region 102; epitaxial growth of N-type ion doped silicon carbide (ion doping concentration of 1×10) in trench by chemical vapor deposition 16 ~1×10 17 cm -3 ) Forming an N-type ion doped silicon carbide drift region 105a; undoped silicon carbide is epitaxially grown on the surface of the N-type ion doped silicon carbide drift region 105a, and the filled silicon carbide is polished flat by a chemical mechanical polishing method to form an undoped silicon carbide transition region 105b, thereby obtaining the structure shown in fig. 4 b.
And 203, forming a second conductive type buried layer in a longitudinal region adjacent to the silicon carbide drift region and forming a second conductive type body region in a lateral region adjacent to the silicon carbide drift region.
Specifically, P-type ions are implanted into a predetermined buried layer region by using an ion implantation method to form a P-type buried layer 103, and P-type ions are implanted into a predetermined body region to form a P-type body region 104, thereby obtaining the structure shown in fig. 4 c. Wherein the ion doping concentration of the P-type buried layer 103 is 3×10 17 ~6×10 17 cm -3 The ion doping concentration of the P-type body region 104 is 1×10 17 ~5×10 17 cm -3 。
And 204, forming a gate structure and a source region on the surface of the second-conductivity-type body region, and forming a drain region on the surface of the silicon carbide drift region.
Specifically, a gate oxide layer 108 of a predetermined length is formed on the surface of the P-type body region 104 by a thermal oxidation method, polysilicon is deposited on the surface of the gate oxide layer 108 by a Chemical Vapor Deposition (CVD) method, and ion implantation heavy doping (doping concentration of 1×10 is performed 19 ~1×10 20 cm -3 ) Forming a polysilicon gate 107, depositing silicon nitride on the surface of the polysilicon gate 107, etching the silicon nitride, retaining the silicon nitride on both sides of the polysilicon gate, forming a silicon nitride sidewall 109,resulting in a gate structure as shown in fig. 4 d.
P-type ions (ion doping concentration 1×10) are implanted into a predetermined substrate electrode region on the surface of the P-type body region 104 19 ~1×10 20 cm -3 ) Forming a substrate electrode 110; n-type ions (ion doping concentration of 1×10) are implanted into a predetermined source region on the surface of the P-type body region 104 19 ~1×10 20 cm -3 ) Forming a source region 111; n-type ions (ion doping concentration of 1×10) are implanted into a predetermined drain region on the surface of the silicon carbide drift region (undoped silicon carbide transition region 105 b) 19 ~1×10 20 cm -3 ) Forming drain region 112; metal is deposited on the surfaces of substrate electrode 110, source region 111, drain region 112, and polysilicon gate 107 to form metal electrode 113, resulting in the structure shown in fig. 4 d.
In the above steps, after the substrate electrode 110, the source region 111, the drain region 112 and the metal electrode 113 are formed, silicon nitride may be deposited on the surface of the polysilicon gate 107 by Chemical Vapor Deposition (CVD), and etched and planarized, so that silicon nitride on both sides of the polysilicon gate is retained, thereby forming the silicon nitride sidewall 109.
In another embodiment, N-type ions (1×10 ion doping concentration) may also be implanted on the side of the silicon carbide drift region adjacent to the P-type body region 104 after the silicon carbide drift region is formed 16 ~5×10 16 cm -3 ) After forming the N-type accumulation region 106, forming the P-type buried layer 103 and the P-type body region 104, thereby obtaining the LDMOS device structure shown in fig. 2.
According to the manufacturing method of the LDMOS device, the heterojunction of the SiC material and the Si material is formed by extending the SiC material on the silicon substrate, and the silicon substrate and other mature silicon material devices can be integrated on the same substrate, so that the integration level of the device can be improved, and the cost is reduced. The drain region and the drift region of the device are manufactured on an epitaxial SiC material, the substrate, the accumulation region, the body region, the source region, the channel region, the grid electrode and the grid electrode oxide layer are manufactured on a Si substrate material, and the breakdown voltage of the device can be improved, the mobility of carriers is improved, and the on-resistance is reduced by adopting the SiC material to manufacture the drain region and the drift region. The method adopts the P type under the drift regionThe buried layer technology modulates the electric field distribution of the drift region through P-type doping under the drift region, improves the breakdown voltage of the device and inhibits the conduction of the parasitic triode; and, adopt the polysilicon gate and sidewall technology compatible with conventional CMOS device, use Si at the same time 3 N 4 The grid side wall can introduce local stress in the channel region to improve the carrier mobility of the device.
The application also provides a power chip which comprises the LDMOS device of the silicon carbide-silicon heterojunction, and has the advantages of high breakdown voltage, low on-resistance and good long-term reliability.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. An LDMOS device of silicon carbide and silicon heterojunction, comprising: the semiconductor device comprises a silicon substrate, a first conductive type well region, a second conductive type body region, a first conductive type drift region, a source region, a drain region and a gate structure, and is characterized by further comprising: a buried layer of a second conductivity type;
the second conductive type buried layer and the second conductive type body region are made of silicon, and the first conductive type drift region and the drain region are made of silicon carbide;
the first conductive type drift region is longitudinally connected with the second conductive type buried layer so as to form a heterojunction of silicon carbide and silicon in a longitudinally connected interface region in a conductive state;
the first conductivity type drift region is laterally contiguous with the second conductivity type body region to form a silicon carbide to silicon heterojunction at a laterally contiguous interface region in a conductive state.
2. The LDMOS device of claim 1, wherein the first conductivity type drift region comprises: a first conductivity type ion doped silicon carbide drift region and an undoped silicon carbide transition region;
the first conductive type ion doped silicon carbide drift region is longitudinally connected with the second conductive type buried layer and is transversely connected with the second conductive type body region;
the undoped silicon carbide transition region is positioned on the surface of the first-conductivity-type ion-doped silicon carbide drift region and is laterally connected with the second-conductivity-type body region.
3. The LDMOS device of claim 1, wherein the gate structure comprises: the polysilicon gate electrode, the gate oxide layer and the silicon nitride side wall are arranged between the polysilicon gate electrode and the second conductive type body region, and the silicon nitride side wall is arranged on two sides of the polysilicon gate electrode.
4. The LDMOS device of claim 3, further comprising: the substrate electrode is connected with the source region, and the metal electrode is arranged on the surfaces of the substrate electrode, the source region, the drain region and the polysilicon gate.
5. A method of fabricating an LDMOS device having a silicon carbide and silicon heterojunction, comprising:
ion implantation is carried out on the silicon substrate to form a first conductive type well region;
forming a groove above the first conductive type well region, and epitaxially growing silicon carbide inside and outside the groove to form a silicon carbide drift region;
forming a second conductive type buried layer in a longitudinal region adjacent to the silicon carbide drift region, forming a second conductive type body region in a transverse region adjacent to the silicon carbide drift region, forming a heterojunction of silicon carbide and silicon in an interface region where the silicon carbide drift region and the second conductive type buried layer are longitudinally connected, and forming a heterojunction of silicon carbide and silicon in an interface region where the silicon carbide drift region and the second conductive type body region are transversely connected;
and forming a grid structure and a source region on the surface of the second conductive type body region, and forming a drain region of silicon carbide material on the surface of the silicon carbide drift region.
6. The method of manufacturing a silicon carbide and silicon heterojunction LDMOS device according to claim 5, wherein the ion implanting the first conductivity type well region into the silicon substrate comprises:
and selecting a P-type silicon substrate, and injecting N-type ions into a preset area of the P-type silicon substrate to form an N-type well region.
7. The method of fabricating a silicon carbide and silicon heterojunction LDMOS device of claim 5, wherein forming a trench over the well region of the first conductivity type, epitaxially growing silicon carbide within the trench, forming a silicon carbide drift region, comprises:
etching the silicon substrate, and forming a groove above the first conductive type well region;
epitaxially growing first-conductivity-type ion-doped silicon carbide in the groove by adopting a chemical vapor deposition method to form a first-conductivity-type ion-doped silicon carbide drift region;
and epitaxially growing undoped silicon carbide on the surface of the first-conductivity-type ion-doped silicon carbide drift region to form an undoped silicon carbide transition region.
8. The method of fabricating a silicon carbide and silicon heterojunction LDMOS device according to claim 5, wherein forming a gate structure on a surface of the second conductivity type body region comprises:
forming a gate oxide layer on the surface of the second conductive type body region by adopting a thermal oxidation method;
depositing polysilicon on the surface of the gate oxide layer to form a polysilicon gate;
and depositing silicon nitride on the surface of the polysilicon gate, etching the silicon nitride, and reserving the silicon nitride on two sides of the polysilicon gate to form a silicon nitride side wall.
9. The method of manufacturing a silicon carbide and silicon heterojunction LDMOS device as claimed in claim 5, wherein the silicon carbide drift region has an ion doping concentration of 1 x 10 16 ~1×10 17 cm -3 The ion doping concentration of the second conductive type buried layer is 3×10 17 ~6×10 17 cm -3 The ion doping concentration of the second conductive type body region is 1×10 17 ~5×10 17 cm -3 。
10. A power chip comprising an LDMOS device comprising a silicon carbide and silicon heterojunction as claimed in any of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311096893.XA CN116825824B (en) | 2023-08-29 | 2023-08-29 | LDMOS device of silicon carbide and silicon heterojunction and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311096893.XA CN116825824B (en) | 2023-08-29 | 2023-08-29 | LDMOS device of silicon carbide and silicon heterojunction and manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116825824A CN116825824A (en) | 2023-09-29 |
| CN116825824B true CN116825824B (en) | 2023-12-15 |
Family
ID=88141524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311096893.XA Active CN116825824B (en) | 2023-08-29 | 2023-08-29 | LDMOS device of silicon carbide and silicon heterojunction and manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116825824B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6011278A (en) * | 1997-10-28 | 2000-01-04 | Philips Electronics North America Corporation | Lateral silicon carbide semiconductor device having a drift region with a varying doping level |
| CN107994071A (en) * | 2017-12-11 | 2018-05-04 | 电子科技大学 | A kind of hetero-junctions channel insulation grid-type field-effect tube |
| CN108511528A (en) * | 2018-04-11 | 2018-09-07 | 西安电子科技大学 | Lateral double diffusion metal oxide composite semiconductor field-effect tube with deep drain region and preparation method thereof |
| KR102030464B1 (en) * | 2018-03-30 | 2019-10-10 | 현대오트론 주식회사 | Lateral typed power semiconductor device |
| CN212182334U (en) * | 2020-05-27 | 2020-12-18 | 成都蓉矽半导体有限公司 | Novel transverse double-diffusion silicon carbide field effect transistor |
-
2023
- 2023-08-29 CN CN202311096893.XA patent/CN116825824B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6011278A (en) * | 1997-10-28 | 2000-01-04 | Philips Electronics North America Corporation | Lateral silicon carbide semiconductor device having a drift region with a varying doping level |
| CN107994071A (en) * | 2017-12-11 | 2018-05-04 | 电子科技大学 | A kind of hetero-junctions channel insulation grid-type field-effect tube |
| KR102030464B1 (en) * | 2018-03-30 | 2019-10-10 | 현대오트론 주식회사 | Lateral typed power semiconductor device |
| CN108511528A (en) * | 2018-04-11 | 2018-09-07 | 西安电子科技大学 | Lateral double diffusion metal oxide composite semiconductor field-effect tube with deep drain region and preparation method thereof |
| CN212182334U (en) * | 2020-05-27 | 2020-12-18 | 成都蓉矽半导体有限公司 | Novel transverse double-diffusion silicon carbide field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116825824A (en) | 2023-09-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8969953B2 (en) | Method of forming a self-aligned charge balanced power DMOS | |
| US5349224A (en) | Integrable MOS and IGBT devices having trench gate structure | |
| JP4990458B2 (en) | Self-aligned silicon carbide LMOSFET | |
| CN111799322B (en) | Double-groove type SiC MOSFET structure for high-frequency application and manufacturing method | |
| CN114420761B (en) | High-pressure-resistant silicon carbide device and preparation method thereof | |
| CN114823872B (en) | Full-isolation substrate voltage-resistant power semiconductor device and manufacturing method thereof | |
| CN109524472B (en) | Novel power MOSFET device and preparation method thereof | |
| CN115642088A (en) | Groove type SiC MOSFET device structure and manufacturing method thereof | |
| CN114792734A (en) | Double-groove silicon carbide MOSFET and preparation method thereof | |
| US6355944B1 (en) | Silicon carbide LMOSFET with gate reach-through protection | |
| CN114899239B (en) | Silicon carbide MOSFET and preparation method thereof | |
| CN116666435A (en) | Linear power MOSFET device and preparation method | |
| CN116825824B (en) | LDMOS device of silicon carbide and silicon heterojunction and manufacturing method | |
| CN115763562A (en) | High-mobility silicon carbide N-type LDMOS device | |
| CN115148796A (en) | Semiconductor device with split gate structure and method of manufacturing the same | |
| CN114899103B (en) | Silicon carbide LDMOSFET device manufacturing method and silicon carbide LDMOSFET device | |
| CN112909075A (en) | Trench MOSFET with charge balance structure and manufacturing method thereof | |
| CN115172466B (en) | Novel super-junction VDMOS structure and preparation method thereof | |
| CN114242779B (en) | Silicon carbide accumulation state MOSFET with groove | |
| CN115295612B (en) | Single-side channel RC-IGBT device, preparation method thereof and chip | |
| CN114093950A (en) | LDMOS device of stepped STI auxiliary field plate and manufacturing method thereof | |
| CN115547832A (en) | SiC MOSFET device and preparation method thereof | |
| CN115000154A (en) | Silicon carbide MOSFET device with L-shaped vertical source electrode and manufacturing method thereof | |
| CN115732328A (en) | Semiconductor chip manufacturing method and semiconductor chip | |
| CN113517334A (en) | Power MOSFET device with high-K dielectric groove and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |