CN114899103B - Silicon carbide LDMOSFET device manufacturing method and silicon carbide LDMOSFET device - Google Patents
Silicon carbide LDMOSFET device manufacturing method and silicon carbide LDMOSFET device Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 148
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 136
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 71
- 239000002184 metal Substances 0.000 claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 210000000746 body region Anatomy 0.000 claims abstract description 46
- 238000000151 deposition Methods 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005468 ion implantation Methods 0.000 claims abstract description 20
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims description 32
- 230000008569 process Effects 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 24
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- 239000004065 semiconductor Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 200
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
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- 238000005229 chemical vapour deposition Methods 0.000 description 6
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention relates to the field of semiconductors, and provides a silicon carbide LDMOSFET device and a manufacturing method thereof. The method comprises the following steps: forming an N-type silicon carbide epitaxial layer on an N-type silicon carbide substrate in an epitaxial mode, and forming a first oxidation layer on the surface of the N-type silicon carbide epitaxial layer; forming a P-type body region and an N-type drift region on the N-type silicon carbide epitaxial layer; forming first grooves on the edges of two sides of the N-type drift region; forming a second oxide layer on the side wall of the first groove, and performing ion implantation on the N-type silicon carbide at the bottom of the first groove to form a drain electrode; and depositing metal on the surface of the drain electrode to form a drain electrode metal layer, etching the first oxidation layer to form a second groove, and depositing polycrystalline silicon in the second groove to form a polycrystalline silicon gate. The invention forms a double-field plate structure and a double-channel structure, reduces the surface electric field through the double-field plate structure, improves the breakdown voltage, and reduces the on-resistance through the double-channel structure.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a silicon carbide LDMOSFET device and a manufacturing method thereof.
Background
A Double-diffused metal oxide semiconductor field effect transistor (DMOS) has the characteristics of high voltage resistance, low power consumption, large current driving capability and the like, and is widely applied to power management circuits. The Double-diffused metal oxide semiconductor field effect transistor mainly has two types, namely a Vertical Double-diffused MOSFET (VDMOSFET) and a Lateral Double-diffused MOSFET (LDMOSFET).
For the LDMOSFET, the on-resistance and the breakdown voltage are two important indexes, and the thickness of the epitaxial layer, the doping concentration and the length of the drift region are the most important characteristic parameters. In general, the breakdown voltage can be increased by increasing the channel length and the length of the drift region, but this increases the on-resistance of the LDMOSFET. The prior LDMOSFET usually adopts a silicon substrate, and the breakdown voltage of the device is not high because the forbidden bandwidth (1.1 eV) of silicon is not wide enough and the critical breakdown field strength (0.3 MV/cm) is not high. At present, there is a need to research a high breakdown voltage and low on-resistance LDMOSFET device.
Disclosure of Invention
The invention aims to provide a silicon carbide LDMOSFET device and a manufacturing method thereof, so as to improve breakdown voltage and reduce on-resistance.
In order to achieve the above object, a first aspect of the present invention provides a method for manufacturing a silicon carbide LDMOSFET device, comprising:
epitaxially forming an N-type silicon carbide epitaxial layer on the N-type silicon carbide substrate, and forming a first oxide layer on the surface of the N-type silicon carbide epitaxial layer;
etching the N-type silicon carbide epitaxial layer by taking the first oxide layer as a barrier layer so as to form a body region in the N-type silicon carbide epitaxial layer;
epitaxially growing P-type silicon carbide on the body region in the N-type silicon carbide epitaxial layer to form a P-type body region, and forming an N-type drift region in the N-type silicon carbide epitaxial layer except the P-type body region;
forming first grooves on the edges of two sides of the N-type drift region;
forming a second oxide layer on the side wall of the first groove, and performing ion implantation on the N-type silicon carbide at the bottom of the first groove to form a drain electrode;
depositing metal on the surface of the drain electrode to fill the first groove to form a drain electrode metal layer, wherein the drain electrode metal layer and the second oxidation layer form a first field plate structure;
and etching the first oxide layer to form a second groove, depositing polycrystalline silicon in the second groove to form a polycrystalline silicon gate, and forming a second field plate structure by the polycrystalline silicon gate and the first oxide layer.
Further, the forming of the first groove at the two side edges of the N-type drift region includes:
depositing a sacrificial oxide layer on the surface of the first oxide layer; and etching the first oxide layer, the sacrificial oxide layer and the N-type drift region, and removing the N-type silicon carbide on the edges of the two sides of the N-type drift region to form two first grooves.
Further, the forming of the second oxide layer on the sidewall of the first groove includes:
and depositing a second oxide layer on the surface of the sacrificial oxide layer and the inner surface of the first groove, removing the second oxide layer on the surface of the sacrificial oxide layer and the bottom surface of the first groove, and reserving the second oxide layer on the side wall of the first groove.
Further, the ion implantation of the N-type silicon carbide at the bottom of the first groove to form the drain includes: and taking the sacrificial oxide layer and the second oxide layer on the side wall of the first groove as barrier layers, and performing N-type heavily doped ion implantation on the N-type silicon carbide at the bottom of the first groove by adopting a self-alignment process to form a drain electrode.
Further, the method further comprises:
after the drain metal layer is formed, the sacrificial oxide layer is removed by a CMP process.
Further, the etching the first oxide layer to form a second groove, and depositing polysilicon in the second groove to form a polysilicon gate includes:
depositing a gate oxide layer on the surface of the first oxide layer; etching the first oxide layer and the gate oxide layer to form two second grooves which are respectively positioned at two sides of the P-shaped body region; and depositing polycrystalline silicon on the surface of the gate oxide layer and in the second groove, and etching the polycrystalline silicon to form a polycrystalline silicon gate.
Further, the method further comprises:
and performing N-type heavily doped ion implantation on the preset region of the P-type body region by adopting a self-alignment process to form a source electrode.
The second aspect of the present invention provides a silicon carbide LDMOSFET device, which includes an N-type silicon carbide substrate, a P-type body region, an N-type drift region, and a polysilicon gate, and further includes: the field plate structure comprises a first field plate structure and a second field plate structure, wherein the first field plate structure is composed of a drain electrode metal layer and a second oxidation layer, and the second field plate structure is composed of a polysilicon gate and a first oxidation layer;
the P-type body region and the N-type drift region are formed in the following mode:
epitaxially forming an N-type silicon carbide epitaxial layer on the N-type silicon carbide substrate, and forming a first oxide layer on the surface of the N-type silicon carbide epitaxial layer;
etching the N-type silicon carbide epitaxial layer by taking the first oxide layer as a barrier layer so as to form a body region in the N-type silicon carbide epitaxial layer;
epitaxially growing P-type silicon carbide on the body region in the N-type silicon carbide epitaxial layer to form a P-type body region, and forming an N-type drift region in the N-type silicon carbide epitaxial layer except the P-type body region;
the drain field plate structure and the gate field plate structure are formed by the following method:
forming first grooves on the edges of two sides of the N-type drift region;
forming a second oxide layer on the side wall of the first groove, and performing ion implantation on the N-type silicon carbide at the bottom of the first groove to form a drain electrode;
depositing metal on the surface of the drain electrode to fill the first groove to form a drain electrode metal layer, wherein the drain electrode metal layer and the second oxidation layer form a first field plate structure;
and etching the first oxide layer to form a second groove, depositing polycrystalline silicon in the second groove to form a polycrystalline silicon gate, and forming a second field plate structure by the polycrystalline silicon gate and the first oxide layer.
Further, the forming of the first groove at the two side edges of the N-type drift region includes:
depositing a sacrificial oxide layer on the surface of the first oxide layer; and etching the first oxide layer, the sacrificial oxide layer and the N-type drift region, and removing the N-type silicon carbide on the edges of the two sides of the N-type drift region to form two first grooves.
Further, the forming of the second oxide layer on the sidewall of the first groove includes:
and depositing a second oxide layer on the surface of the sacrificial oxide layer and the inner surface of the first groove, removing the second oxide layer on the surface of the sacrificial oxide layer and the bottom surface of the first groove, and reserving the second oxide layer on the side wall of the first groove.
Further, the ion implantation of the N-type silicon carbide at the bottom of the first groove to form the drain includes: and taking the sacrificial oxide layer and the second oxide layer on the side wall of the first groove as barrier layers, and performing N-type heavily doped ion implantation on the N-type silicon carbide at the bottom of the first groove by adopting a self-alignment process to form a drain electrode.
Further, the etching the first oxide layer to form a second groove, and depositing polysilicon in the second groove to form a polysilicon gate includes: depositing a gate oxide layer on the surface of the first oxide layer; etching the first oxide layer and the gate oxide layer to form two second grooves which are respectively positioned at two sides of the P-shaped body region; and depositing polycrystalline silicon on the surface of the gate oxide layer and in the second groove, and etching the polycrystalline silicon to form a polycrystalline silicon gate.
Further, the silicon carbide LDMOSFET device further comprises a source electrode, and the source electrode is formed by performing N-type heavily doped ion implantation on a preset area of the P-type body area by adopting a self-alignment process.
The manufacturing method of the silicon carbide LDMOSFET device provided by the invention has the following advantages:
(1) the silicon carbide substrate is adopted, the silicon carbide epitaxial layer is formed on the silicon carbide substrate in an epitaxial mode, the drift region is formed on the silicon carbide epitaxial layer, and the breakdown voltage of the device is improved by utilizing the high breakdown characteristic of the silicon carbide material.
(2) The drain electrode metal layer and the second oxide layer form a first field plate structure, the polysilicon gate and the first oxide layer form a second field plate structure, and the surface electric field is reduced through the double-field plate structure, so that the breakdown voltage is further improved.
(3) The polysilicon gate and the P-type body region form a double-channel structure of a vertical channel and a transverse channel, and the threshold voltage of the vertical channel is lower, so that the on-resistance is lower.
(4) The first oxide layer formed in the primary deposition step is used as a barrier layer for etching silicon carbide and a protective layer for extending silicon carbide in the subsequent steps, and is also used as an isolation oxide layer in the second field plate structure, so that the mask frequency and the deposition frequency are reduced, and the process steps are simplified.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 is a flow chart of a method for manufacturing a silicon carbide LDMOSFET device according to an embodiment of the present invention;
fig. 2a to 2h are schematic diagrams of a manufacturing process of a silicon carbide LDMOSFET device according to an embodiment of the present invention.
Description of the reference numerals
1-a first oxide layer, 2-a body region, 3-a first recess, 4-a sacrificial oxide layer, 5-a second oxide layer,
6-drain electrode, 7-drain electrode metal layer, 8-gate oxide layer, 9-second groove, 10-polysilicon gate electrode and 11-source electrode.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when in use, and are used only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
Fig. 1 is a flow chart of a method of fabricating a silicon carbide LDMOSFET device according to an embodiment of the invention. As shown in fig. 1, the present embodiment provides a method for manufacturing a silicon carbide LDMOSFET device, the method comprising the steps of:
and S1, epitaxially forming an N-type silicon carbide epitaxial layer on the N-type silicon carbide substrate, and forming a first oxidation layer on the surface of the N-type silicon carbide epitaxial layer.
Referring to fig. 2a, an N-type silicon carbide substrate SUB-SiC is epitaxially coated with an N-type silicon carbide material to form an N-type silicon carbide epitaxial layer EPI-SiC, and silicon dioxide (SiO) is deposited on the surface of the N-type silicon carbide epitaxial layer EPI-SiC by a Chemical Vapor Deposition (CVD) process 2 ) A first oxide layer 1 is formed. The material of the N-type silicon carbide substrate and the silicon carbide epitaxial layer is preferably 4H — SiC. The forbidden band width of the 4H-SiC is 3.25eV, the critical breakdown field intensity is 3.0MV/cm, and the SiC material has high breakdown property. However, Si has a forbidden band width of 1.1eV,the critical breakdown field strength is 0.3 MV/cm. Therefore, by using 4H-SiC as the substrate of the LDMOSFET, the breakdown voltage of the LDMOSFET device can be further improved compared to a silicon substrate.
And S2, etching the N-type silicon carbide epitaxial layer by taking the first oxide layer as a barrier layer, and forming a body region in the N-type silicon carbide epitaxial layer.
Referring to fig. 2b, the first oxide layer is etched by a dry method, the etched first oxide layer is used as a barrier layer to etch the EPI-SiC of the N-type silicon carbide epitaxial layer, a trench is formed in the EPI-SiC, and the trench is used as a body region 2 for forming a body region of a device in a subsequent step.
And S3, epitaxially growing P-type silicon carbide outside the body region to form a P-type body region, and forming an N-type drift region in the N-type silicon carbide epitaxial layer except the P-type body region.
Referring to fig. 2c, P-type silicon carbide is epitaxially grown in the trench as the body region 2 to fill the trench, and the filled trench is planarized to form a P-body region P-body. The region other than the P-body in the N-type silicon carbide epitaxial layer EPI-SiC constitutes an N-type drift region NRF.
And S4, forming first grooves at the two side edges of the N-type drift region.
Referring to fig. 2d, a certain thickness of silicon dioxide is deposited on the surface of the first oxide layer 1 as a sacrificial oxide layer 4. And etching the first oxide layer 1, the sacrificial oxide layer 4 and the N-type drift region NRF by adopting a dry etching method, and removing the silicon carbide materials at the two side edges of the N-type drift region NRF to form two first grooves 3.
And S5, forming a second oxide layer on the side wall of the first groove, and performing ion implantation on the N-type silicon carbide at the bottom of the first groove to form a drain.
Referring to fig. 2e, a second oxide layer 5 is formed by depositing a certain thickness of silicon dioxide on the surface of the sacrificial oxide layer 4 and the inner surface of the first groove 3.
Referring to fig. 2f, the surface of the sacrificial oxide layer 4 and the second oxide layer 5 on the bottom surface of the first groove are etched away by using a dry etching method, and the second oxide layer 5 on the sidewall of the first groove is remained. And taking the sacrificial oxide layer 4 and the second oxide layer 5 on the side wall of the first groove as barrier layers, and performing N-type heavily doped ion implantation on the N-type silicon carbide at the bottom of the first groove by adopting a self-alignment process to form a drain electrode 6.
And S6, depositing metal on the surface of the drain electrode to fill the first groove to form a drain electrode metal layer, wherein the drain electrode metal layer and the second oxide layer form a first field plate structure.
Referring to fig. 2g, a metal material is deposited on the surface of the drain electrode 6 by using a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process until the metal material completely fills the first groove 3, the metal-filled first groove forms a drain metal layer 7, and the drain metal layer 7 and the second oxide layer 5 form a first field plate structure (drain field plate structure). Among them, the metal material of the drain metal layer 7 is preferably high temperature resistant tungsten metal. The LDMOSFET device has a large current amount and a large heat generation amount, and is likely to generate a Self-Heating Effect (Self-Heating Effect), and when the device is turned on, the surface current density is too large to generate heat, which causes a decrease in carrier mobility and a decrease in on-current. In the embodiment of the invention, the drain electrode and the drain electrode metal layer are embedded into the NRF region, and the drain electrode metal layer and the second oxidation layer form a field plate structure, so that on one hand, the surface electric field of the NRF can be reduced, and the breakdown voltage can be improved; on the other hand, carriers flow in the NRF region (but not flow on the surface of the NRF region), so that the on-resistance is reduced; in addition, the drain electrode metal layer has the characteristics of high temperature resistance, good heat conductivity and low resistance, and can reduce the self-heating effect of the device.
After the drain metal layer is formed, the sacrificial oxide layer 4 is removed using a CMP (Chemical Mechanical Polishing) process.
S7, etching the first oxide layer to form a second groove, depositing polycrystalline silicon in the second groove to form a polycrystalline silicon gate, and enabling the polycrystalline silicon gate and the first oxide layer to form a second field plate structure.
Referring to fig. 2h, a gate oxide layer 8 is deposited on the surface of the first oxide layer 1, and the first oxide layer 1 and the gate oxide layer 8 are etched to form two second grooves 9 respectively located at two sides of the P-body region P-body. And depositing polycrystalline silicon on the surface of the gate oxide layer 8 and in the second groove 9, and etching the polycrystalline silicon to form a polycrystalline silicon gate 10. The polysilicon gate 10 and the first oxide layer 1 form a second field plate structure (gate field plate structure), so that the surface electric field of the device is further reduced, and the breakdown voltage is improved. In this embodiment, the second recess 9 filled with polysilicon forms a lower portion of the polysilicon gate 10, and the lower portion of the polysilicon gate 10 is embedded into the first oxide layer 1 to form a vertical channel with the P-body. The upper portion of the polysilicon gate 10 forms a lateral channel with the P-body. The vertical channel and the lateral channel have different threshold voltages, and the lower threshold voltage of the vertical channel means that the on-resistance becomes lower.
After the polysilicon gate 10 is formed, a self-aligned process is used to perform N-type heavily doped ion implantation in a predetermined region of the P-body region to form a source 11. Accurate alignment of the polysilicon gate 10 and the source 11 is achieved through a self-aligned process, reducing overlap capacitance.
The manufacturing method of the silicon carbide LDMOSFET device has the following advantages that:
(1) the silicon carbide substrate is adopted, the silicon carbide epitaxial layer is formed on the silicon carbide substrate in an epitaxial mode, the drift region is formed on the silicon carbide epitaxial layer, and the breakdown voltage of the device is improved by utilizing the high breakdown characteristic of the silicon carbide material.
(2) The drain electrode metal layer and the second oxide layer form a first field plate structure, the polysilicon gate and the first oxide layer form a second field plate structure, and the surface electric field is reduced through the double-field plate structure, so that the breakdown voltage is further improved.
(3) The polysilicon gate and the P-type body region form a double-channel structure of a vertical channel and a transverse channel, and the threshold voltage of the vertical channel is lower, so that the on-resistance is lower.
(4) The first oxide layer formed in the primary deposition step is used as a barrier layer for etching silicon carbide and a protective layer for extending silicon carbide in the subsequent steps, and is also used as an isolation oxide layer in the second field plate structure, so that the mask frequency and the deposition frequency are reduced, and the process steps are simplified.
The embodiment of the invention also provides a silicon carbide LDMOSFET device. As shown in fig. 2h, the silicon carbide LDMOSFET device includes an N-type silicon carbide substrate SUB-SiC, a P-type body region P-body, an N-type drift region NRF, a polysilicon gate 10, a drain electrode 6, a drain metal layer 7, and a source electrode 11, and further includes a first field plate structure composed of the drain metal layer 7 and a second oxide layer 5, and a second field plate structure composed of the polysilicon gate 10 and a first oxide layer 1. The P-type body region and the N-type drift region are formed in the following way: epitaxially forming an N-type silicon carbide epitaxial layer on an N-type silicon carbide substrate, and forming a first oxidation layer 1 on the surface of the N-type silicon carbide epitaxial layer; etching the N-type silicon carbide epitaxial layer by taking the first oxide layer as a barrier layer so as to form a body region in the N-type silicon carbide epitaxial layer; epitaxially growing P-type silicon carbide on the body region in the N-type silicon carbide epitaxial layer to form a P-type body region, and forming an N-type drift region in the N-type silicon carbide epitaxial layer except the P-type body region; the drain field plate structure and the gate field plate structure are formed by: forming first grooves on the edges of two sides of the N-type drift region; forming a second oxide layer 5 on the side wall of the first groove, and performing ion implantation on the N-type silicon carbide at the bottom of the first groove to form a drain electrode; depositing metal on the surface of the drain electrode to fill the first groove to form a drain electrode metal layer, wherein the drain electrode metal layer 7 and the second oxidation layer 5 form a first field plate structure; and etching the first oxide layer 1 to form a second groove 9, depositing polycrystalline silicon in the second groove 9 to form a polycrystalline silicon grid 10, and forming a second field plate structure by the polycrystalline silicon grid 10 and the first oxide layer 1. The source 11 is formed by implanting N-type heavily doped ions into a preset region of the P-type body region by using a self-aligned process.
Referring to fig. 2d, silicon dioxide is deposited on the surface of the first oxide layer 1 as a sacrificial oxide layer 4. And etching the first oxide layer 1, the sacrificial oxide layer 4 and the N-type drift region NRF by adopting a dry etching method, and removing the silicon carbide materials at the edges of the two sides of the N-type drift region NRF to form two first grooves 3.
Referring to fig. 2e, a second oxide layer 5 is formed by depositing a certain thickness of silicon dioxide on the surface of the sacrificial oxide layer 4 and the inner surface of the first groove 3.
Referring to fig. 2f, the surface of the sacrificial oxide layer 4 and the second oxide layer 5 on the bottom surface of the first groove are etched away by using a dry etching method, and the second oxide layer 5 on the sidewall of the first groove is remained. And taking the sacrificial oxide layer 4 and the second oxide layer 5 on the side wall of the first groove as barrier layers, and performing N-type heavily doped ion implantation on the N-type silicon carbide at the bottom of the first groove by adopting a self-alignment process to form a drain electrode 6.
Referring to fig. 2g, a metal material is deposited on the surface of the drain electrode 6 by using a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process until the metal material completely fills the first groove 3, the metal-filled first groove forms a drain metal layer 7, and the drain metal layer 7 and the second oxide layer 5 form a first field plate structure (drain field plate structure). After the drain metal layer is formed, the sacrificial oxide layer 4 is removed using a CMP process. Among them, the metal material of the drain metal layer 7 is preferably high temperature resistant tungsten metal. In the embodiment of the invention, the drain electrode and the drain electrode metal layer are embedded into the NRF region, and the drain electrode metal layer and the second oxidation layer form a field plate structure, so that on one hand, the surface electric field of the NRF can be reduced, and the breakdown voltage can be improved; on the other hand, carriers flow in the NRF region (but not on the surface of the NRF region), so that the on-resistance is reduced; in addition, the drain electrode metal layer has the characteristics of high temperature resistance, good heat conductivity and low resistance, and can reduce the self-heating effect of the device.
Referring to fig. 2h, a gate oxide layer 8 is deposited on the surface of the first oxide layer 1, and the first oxide layer 1 and the gate oxide layer 8 are etched to form two second grooves 9 respectively located at two sides of the P-body region P-body. And depositing polycrystalline silicon on the surface of the gate oxide layer 8 and in the second groove 9, and etching the polycrystalline silicon to form a polycrystalline silicon gate 10. The polysilicon gate 10 and the first oxide layer 1 form a second field plate structure (gate field plate structure), so that the surface electric field of the device is further reduced, and the breakdown voltage is improved. In this embodiment, the second recess 9 filled with polysilicon forms a lower portion of the polysilicon gate 10, and the lower portion of the polysilicon gate 10 is embedded into the first oxide layer 1 to form a vertical channel with the P-body. The upper portion of the polysilicon gate 10 forms a lateral channel with the P-body. The vertical channel and the lateral channel have different threshold voltages, and the threshold voltage of the vertical channel is lower, meaning that the on-resistance becomes lower.
According to the silicon carbide LDMOSFET device, the silicon carbide substrate is adopted, the silicon carbide epitaxial layer is formed on the silicon carbide substrate in an epitaxial mode, the drift region is formed on the silicon carbide epitaxial layer, and the breakdown voltage of the device is improved by utilizing the high breakdown characteristic of the silicon carbide material. A drain electrode metal layer and a second oxide layer of the device form a first field plate structure, a polysilicon gate and the first oxide layer form a second field plate structure, and the surface electric field is reduced and the breakdown voltage is improved through the double-field plate structure. The polysilicon gate and the P-type body region of the device form a vertical channel and a transverse channel, and the threshold voltage of the vertical channel is lower, so that the on-resistance is lower.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (13)
1. A method for manufacturing a silicon carbide LDMOSFET device is characterized by comprising the following steps:
epitaxially forming an N-type silicon carbide epitaxial layer on the N-type silicon carbide substrate, and forming a first oxide layer on the surface of the N-type silicon carbide epitaxial layer;
etching the N-type silicon carbide epitaxial layer by taking the first oxide layer as a barrier layer so as to form a body region in the N-type silicon carbide epitaxial layer;
epitaxially growing P-type silicon carbide on the body region in the N-type silicon carbide epitaxial layer to form a P-type body region, and forming an N-type drift region in the N-type silicon carbide epitaxial layer except the P-type body region;
forming first grooves on the edges of two sides of the N-type drift region;
forming a second oxide layer on the side wall of the first groove, and performing ion implantation on the N-type silicon carbide at the bottom of the first groove to form a drain electrode;
depositing metal on the surface of the drain electrode to fill the first groove to form a drain electrode metal layer, wherein the drain electrode metal layer and the second oxidation layer form a first field plate structure;
and etching the first oxide layer to form a second groove, depositing polycrystalline silicon in the second groove to form a polycrystalline silicon grid, and forming a second field plate structure by the polycrystalline silicon grid and the first oxide layer.
2. The method of manufacturing a silicon carbide LDMOSFET device as claimed in claim 1, wherein said forming first recesses at both side edges of the N-type drift region includes:
depositing a sacrificial oxide layer on the surface of the first oxide layer;
and etching the first oxide layer, the sacrificial oxide layer and the N-type drift region, and removing the N-type silicon carbide on the edges of the two sides of the N-type drift region to form two first grooves.
3. The method of manufacturing a silicon carbide LDMOSFET device as claimed in claim 2, wherein said forming a second oxide layer on the sidewalls of the first recess comprises:
and depositing a second oxide layer on the surface of the sacrificial oxide layer and the inner surface of the first groove, removing the second oxide layer on the surface of the sacrificial oxide layer and the bottom surface of the first groove, and reserving the second oxide layer on the side wall of the first groove.
4. The method of manufacturing a silicon carbide LDMOSFET device as set forth in claim 3, wherein said ion implanting the N-type silicon carbide in the bottom of the first recess to form the drain comprises:
and taking the sacrificial oxide layer and the second oxide layer on the side wall of the first groove as barrier layers, and performing N-type heavily doped ion implantation on the N-type silicon carbide at the bottom of the first groove by adopting a self-alignment process to form a drain electrode.
5. The method of manufacturing a silicon carbide LDMOSFET device as set forth in claim 4, further including:
after the drain metal layer is formed, the sacrificial oxide layer is removed by a CMP process.
6. The method of manufacturing a silicon carbide LDMOSFET device as claimed in claim 1, wherein said etching the first oxide layer to form a second recess and depositing polysilicon in the second recess to form a polysilicon gate comprises:
depositing a gate oxide layer on the surface of the first oxide layer;
etching the first oxide layer and the gate oxide layer to form two second grooves which are respectively positioned at two sides of the P-shaped body region;
and depositing polycrystalline silicon on the surface of the gate oxide layer and in the second groove, and etching the polycrystalline silicon to form a polycrystalline silicon gate.
7. The method of manufacturing a silicon carbide LDMOSFET device as set forth in claim 6, further including:
and performing N-type heavily doped ion implantation on the preset region of the P-type body region by adopting a self-alignment process to form a source electrode.
8. The utility model provides a carborundum LDMOSFET device, includes N type carborundum substrate, P type body region, N type drift region and polycrystalline silicon grid, its characterized in that still includes: the field plate structure comprises a first field plate structure and a second field plate structure, wherein the first field plate structure is composed of a drain electrode metal layer and a second oxidation layer, and the second field plate structure is composed of a polysilicon gate and a first oxidation layer;
the P-type body region and the N-type drift region are formed in the following way:
epitaxially forming an N-type silicon carbide epitaxial layer on the N-type silicon carbide substrate, and forming a first oxide layer on the surface of the N-type silicon carbide epitaxial layer;
etching the N-type silicon carbide epitaxial layer by taking the first oxide layer as a barrier layer so as to form a body region in the N-type silicon carbide epitaxial layer;
epitaxially growing P-type silicon carbide on the body region in the N-type silicon carbide epitaxial layer to form a P-type body region, and forming an N-type drift region in the N-type silicon carbide epitaxial layer except the P-type body region;
the first field plate structure and the second field plate structure are formed by:
forming first grooves at the edges of two sides of the N-type drift region;
forming a second oxide layer on the side wall of the first groove, and performing ion implantation on the N-type silicon carbide at the bottom of the first groove to form a drain electrode;
depositing metal on the surface of the drain electrode to fill the first groove to form a drain electrode metal layer, wherein the drain electrode metal layer and the second oxidation layer form a first field plate structure;
and etching the first oxide layer to form a second groove, depositing polycrystalline silicon in the second groove to form a polycrystalline silicon gate, and forming a second field plate structure by the polycrystalline silicon gate and the first oxide layer.
9. The silicon carbide LDMOSFET device of claim 8, wherein the forming of the first grooves at both side edges of the N-type drift region comprises:
depositing a sacrificial oxide layer on the surface of the first oxide layer;
and etching the first oxide layer, the sacrificial oxide layer and the N-type drift region, and removing the N-type silicon carbide on the edges of the two sides of the N-type drift region to form two first grooves.
10. The silicon carbide LDMOSFET device of claim 9, wherein said forming of said second oxide layer on the sidewalls of said first recess comprises:
and depositing a second oxide layer on the surface of the sacrificial oxide layer and the inner surface of the first groove, removing the second oxide layer on the surface of the sacrificial oxide layer and the bottom surface of the first groove, and reserving the second oxide layer on the side wall of the first groove.
11. The silicon carbide LDMOSFET device as claimed in claim 10, wherein said ion implanting the N-type silicon carbide in the bottom of the first recess to form the drain comprises:
and taking the sacrificial oxide layer and the second oxide layer on the side wall of the first groove as barrier layers, and performing N-type heavily doped ion implantation on the N-type silicon carbide at the bottom of the first groove by adopting a self-alignment process to form a drain electrode.
12. The silicon carbide LDMOSFET device of claim 8, wherein said etching of said first oxide layer to form a second recess and depositing polysilicon in said second recess to form a polysilicon gate electrode comprises:
depositing a gate oxide layer on the surface of the first oxide layer;
etching the first oxide layer and the gate oxide layer to form two second grooves which are respectively positioned at two sides of the P-shaped body region;
and depositing polycrystalline silicon on the surface of the gate oxide layer and in the second groove, and etching the polycrystalline silicon to form a polycrystalline silicon gate.
13. The silicon carbide LDMOSFET device of claim 12, further comprising: and the source electrode is formed by performing N-type heavily doped ion implantation on a preset region of the P-type body region by adopting a self-alignment process.
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| US10068965B1 (en) * | 2017-06-26 | 2018-09-04 | University Of Electronic Science And Technology Of China | Lateral high-voltage device |
| CN114744027A (en) * | 2022-06-10 | 2022-07-12 | 北京芯可鉴科技有限公司 | Silicon carbide LDMOSFET device manufacturing method and silicon carbide LDMOSFET device |
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| CN102969355A (en) * | 2012-11-07 | 2013-03-13 | 电子科技大学 | Silicon on insulator (SOI)-based metal-oxide-semiconductor field-effect transistor (PMOSFET) power device |
| US10068965B1 (en) * | 2017-06-26 | 2018-09-04 | University Of Electronic Science And Technology Of China | Lateral high-voltage device |
| CN114744027A (en) * | 2022-06-10 | 2022-07-12 | 北京芯可鉴科技有限公司 | Silicon carbide LDMOSFET device manufacturing method and silicon carbide LDMOSFET device |
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