CN116819286B - Semiconductor package testing tool and testing method thereof - Google Patents
Semiconductor package testing tool and testing method thereof Download PDFInfo
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- CN116819286B CN116819286B CN202311075749.8A CN202311075749A CN116819286B CN 116819286 B CN116819286 B CN 116819286B CN 202311075749 A CN202311075749 A CN 202311075749A CN 116819286 B CN116819286 B CN 116819286B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 238000012360 testing method Methods 0.000 title claims abstract description 84
- 238000004806 packaging method and process Methods 0.000 claims description 24
- 239000011521 glass Substances 0.000 claims description 13
- 238000009434 installation Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000005476 soldering Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013527 convolutional neural network Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- -1 gold tin copper aluminum Chemical compound 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0425—Test clips, e.g. for IC's
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention provides a semiconductor package testing tool and a testing method thereof, belonging to the technical field of semiconductor package testing, wherein the semiconductor package testing tool comprises a tool main body, and the lower inner wall of the tool main body is fixedly connected with a mounting block; the plurality of the inserting grooves are arranged, the plurality of inserting grooves are all formed in the upper end of the mounting block, and an elastic assembly is arranged in each inserting groove; and clamping components are arranged in two groups, each group of clamping components comprises a clamping plate, a sliding block, a sliding rod and an electric push rod, the sliding blocks and the sliding rods are both provided with two groups, the semiconductor package is placed in the tool for positioning when being tested, the semiconductor package main body is installed in the tool main body and connected with pins through the elastic components, the two groups of clamping components are clamped on the surface of the semiconductor package main body, the semiconductor package main body is installed and detached very conveniently, compared with the traditional use of soldering and fixing, the time required by fixing is reduced, and the testing speed of the tool is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor package testing, and particularly relates to a semiconductor package testing tool and a semiconductor package testing method.
Background
Semiconductor packaging refers to the process of processing a wafer that passes testing to obtain individual chips according to product model and functional requirements. The packaging process is as follows: the wafer from the wafer front process is cut into small chips (Die) through the dicing process, then the cut chips are attached to the corresponding islands of the substrate (Lead frame) frame by glue, and then the bonding pads (Bond pads) of the chips are connected to the corresponding pins (Lead) of the substrate by using ultra-fine metal (gold tin copper aluminum) wires or conductive resin, and the required circuit is formed; packaging and protecting the independent wafer by using a plastic shell, performing a series of operations after plastic packaging, performing finished product testing after packaging, generally performing procedures such as checking in, testing Test and packaging, and finally warehousing and discharging, wherein the semiconductor package is required to be placed in the package for testing when testing;
the publication number CN114972327B discloses a semiconductor package test system and a test method thereof, which acquire ultrasonic images of a plastic package microcircuit through an ultrasonic scanner, further extract shallow implicit characteristic information of the ultrasonic images and high-dimensional implicit characteristic distribution information focused on chip layering, wire bonding and chip bonding areas respectively by using a convolutional neural network model, and carry out dimensional and correction processing on characteristic images of the two characteristic images during characteristic fusion, so that the probability of the cauchy weight is carried out by carrying out probabilistic information interpretation on characteristic values of each position of the global characteristic image, thereby enhancing the robustness to information loss and improving the characteristic expression capability of the global characteristic image. Furthermore, the packaging effect of the plastic packaging microcircuit can be accurately evaluated.
In the prior art, a semiconductor package is placed in a tool for positioning when being tested, then the tool is placed in test equipment for equipment, and when the semiconductor package is installed in the tool, the semiconductor package is usually fixed by soldering, so that the installation and the disassembly are inconvenient, and the test speed is influenced.
Disclosure of Invention
The invention aims to provide a semiconductor package testing tool and a testing method thereof, and aims to solve the problems that in the prior art, when a semiconductor package is tested, the semiconductor package is placed in the tool for positioning, then the tool is placed in testing equipment for equipment, and when the semiconductor package is installed in the tool, the semiconductor package is fixed by soldering, so that the installation and the disassembly are inconvenient, and the testing speed is influenced.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a semiconductor package test fixture, comprising:
the tool comprises a tool main body, wherein the lower inner wall of the tool main body is fixedly connected with a mounting block;
the plurality of the inserting grooves are arranged, the plurality of inserting grooves are formed in the upper end of the mounting block, and each inserting groove is internally provided with an elastic component;
and clamping components are arranged in two groups, each clamping component comprises a clamping plate, a sliding block, sliding rods and electric pushing rods, the sliding blocks and the sliding rods are both provided with two groups, the sliding rods are fixedly connected to one side end of the installation block and one side inner wall of the tool main body, the electric pushing rods are fixedly connected to one side inner wall of the tool main body, the clamping plates are fixedly connected to the extending ends of the electric pushing rods, the sliding blocks are respectively and fixedly connected to two side ends of the clamping plates, and the sliding blocks are respectively and slidably connected to the circumferential surfaces of the two sliding rods.
As a preferable scheme of the invention, each group of elastic components comprises a spring and a test wire, wherein the spring is fixedly connected to one side inner wall of the inserting groove, and the test wire is fixedly connected to one side end of the spring.
As a preferable scheme of the invention, two connector lugs are fixedly connected to two side ends of the tool main body.
As a preferable scheme of the invention, the upper end of the tool main body is fixedly connected with two top plates.
As a preferable scheme of the invention, the close ends of the two top plates are movably hinged with the cover plates through hinge shafts, and the two side ends of the two cover plates are fixedly connected with handles.
As a preferable scheme of the invention, glass holes are formed in the upper ends of the two cover plates, and glass is fixedly connected in the two glass holes.
As a preferable scheme of the invention, a plurality of semiconductor packaging main bodies are arranged in the tool main body, a plurality of pins are fixedly connected to two side ends of each semiconductor packaging main body, and the pins are respectively and slidably connected to the plurality of inserting grooves.
As a preferable scheme of the invention, a plurality of test wires are fixedly connected in the mounting block, and the plurality of test wires are respectively and electrically connected with the plurality of springs.
As a preferred embodiment of the present invention, the size of the mounting block is 20×15cm.
A testing method of a semiconductor package testing tool comprises the following steps:
s1, mounting a semiconductor package: firstly, mounting a semiconductor package main body to be tested in a tool main body, enabling pins mounted at two side ends of the semiconductor package main body to slide into a plug-in groove, driving a test wire to slide on the surface of the pins through the elasticity of a spring, and enabling the pins to be mounted in the plug-in groove stably;
s2, fixing and packaging: the clamping assembly is controlled to operate, an electric push rod in the clamping assembly operates to drive clamping plates connected with output ends of the clamping assembly to move, and the two clamping plates are clamped on the surfaces of the semiconductor packaging main bodies in a matched mode, so that the semiconductor packaging main bodies are stably installed;
s3, connecting a tool: then the cover plate is controlled to rotate through the handle, the cover plate is closed on the surface of the tool main body, and finally the tool main body is placed in the testing equipment, so that the plurality of connector lugs are connected with the testing equipment;
s4, testing: and finally, testing the semiconductor packaging test fixture.
Compared with the prior art, the invention has the beneficial effects that:
1. in this scheme, through this device, place in the frock and fix a position when semiconductor package tests, semiconductor package main part installs in the frock main part, is connected with the pin by elastic component, by two sets of clamping assembly centre gripping at semiconductor package main part's surface, and installation semiconductor package main part is all very convenient with dismantling semiconductor package main part, and it is fixed in traditional use soldering to compare, reduces the required time when fixed, improves the test speed of frock.
2. In this scheme, carry out the centre gripping by clamping assembly to a plurality of semiconductor package main bodies, drive splint operation by the electric putter operation in the clamping assembly, slide bar and slider play the spacing effect to splint, improve the stability when splint slide, two splint cooperations carry out the centre gripping to a plurality of semiconductor package main bodies, accomplish the fixed of semiconductor package main body, improve the stability of the installation of semiconductor package main body.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a perspective view of the present invention;
FIG. 2 is a top view of the present invention;
FIG. 3 is a side view of the present invention;
FIG. 4 is a bottom view of the present invention;
FIG. 5 is a first cross-sectional view of the present invention;
FIG. 6 is an enlarged view of a portion of the invention at A in FIG. 5;
FIG. 7 is a second cross-sectional view of the present invention;
FIG. 8 is a flow chart of the test method of the present invention.
In the figure: 1. a tool main body; 101. a mounting block; 2. a top plate; 3. a cover plate; 301. a glass hole; 302. a handle; 4. a connector lug; 401. a plug-in groove; 5. a semiconductor package body; 501. pins; 6. a test line; 601. a spring; 602. a metal spring block; 7. a clamping plate; 701. a slide block; 702. a slide bar; 703. an electric push rod.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples
Referring to fig. 1-8, the present invention provides the following technical solutions:
a semiconductor package test fixture, comprising:
the tool comprises a tool main body 1, wherein an installation block 101 is fixedly connected to the lower inner wall of the tool main body 1;
the plurality of inserting grooves 401 are arranged, the plurality of inserting grooves 401 are formed in the upper end of the mounting block 101, and an elastic assembly is arranged in each inserting groove 401;
and clamping components are arranged, each clamping component comprises two clamping plates 7, a sliding block 701, a sliding rod 702 and an electric push rod 703, the sliding blocks 701 and the sliding rods 702 are respectively provided with two sliding rods 702, the two sliding rods 702 are fixedly connected to one side end of the mounting block 101 and one side inner wall of the tool main body 1, the electric push rod 703 is fixedly connected to one side inner wall of the tool main body 1, the clamping plates 7 are fixedly connected to the extending ends of the electric push rod 703, the two sliding blocks 701 are respectively fixedly connected to two side ends of the clamping plates 7, and the two sliding blocks 701 are respectively and slidably connected to the circumferential surfaces of the two sliding rods 702.
In the embodiment of the invention, the mounting block 101 mounted in the tool main body 1 is used for mounting the semiconductor package main body 5, the plurality of inserting grooves 401 are respectively arranged into six rows, each two rows of inserting grooves 401 are used for mounting one semiconductor package main body 5, pins 501 mounted on two sides of the semiconductor package main body 5 are matched with the two rows of inserting grooves 401, after the pins 501 are inserted into the inserting grooves 401, the pins 501 are connected with the pins 501 through elastic components, springs 601 in the elastic components are electrically connected with test wires 6, the test wires 6 are used for transmitting electric signals, the test wires 6 are electrically connected with the connector lugs 4, electric signals generated by the test equipment enter the semiconductor package main body 5 through the connector lugs 4, the test wires 6 and the pins 501, the semiconductor package main body 5 is tested, before testing, the clamping components clamp the semiconductor package main body 5, an electric push rod 703 in the clamping components drives the clamping plate 7 to operate, the slide bars 702 and the slide blocks 701 play a role of limiting the clamping plate 7, stability when the clamping plate 7 slides is improved, the two clamping plates 7 are matched with the clamping the semiconductor package main bodies 5, and the fixing of the semiconductor package main body 5 is completed, and the semiconductor package main body 5 is mounted with improved stability.
Referring to fig. 1-4, each elastic assembly includes a spring 601 and a test wire 6, the spring 601 is fixedly connected to an inner wall of one side of the socket 401, and the test wire 6 is fixedly connected to one side end of the spring 601.
In this embodiment: the spring 601 in the elastic component acts on the elastic force to drive the metal elastic block 602 to slide to the surface of the pin 501, the surface of the pin 501 is provided with a groove matched with the metal elastic block 602, the connection of the pin 501 is completed by the metal elastic block 602 sliding into the groove, and an electric signal is connected with the pin 501 through the spring 601 and the metal elastic block 602.
Referring to fig. 1-4, two lugs 4 are fixedly connected to two side ends of the tool main body 1.
In this embodiment: the connector lug 4 is internally provided with a connecting wire which is connected with a test wire 6 and is connected with test equipment through the connecting wire.
Referring to fig. 1-4, two top plates 2 are fixedly connected to the upper end of the tool main body 1.
In this embodiment: the top plate 2 is used for connecting the cover plate 3.
Referring to fig. 1-4 specifically, the close ends of the two top plates 2 are movably hinged with cover plates 3 through hinge shafts, and two side ends of the two cover plates 3 are fixedly connected with handles 302.
In this embodiment: when the semiconductor package is installed, the cover plate 3 is opened, the semiconductor package is installed, and after the semiconductor package is installed, the cover plate 3 is closed on the surface of the tool main body 1.
Referring to fig. 1-4, glass holes 301 are formed at the upper ends of the two cover plates 3, and glass is fixedly connected in the two glass holes 301.
In this embodiment: glass is installed in the glass hole 301, and the semiconductor package main body 5 in the tool main body 1 is convenient to view through the glass.
Referring to fig. 1 to fig. 4, a plurality of semiconductor package bodies 5 are disposed in the tool body 1, and a plurality of pins 501 are fixedly connected to two side ends of each semiconductor package body 5, and the plurality of pins 501 are respectively slidably connected to the plurality of inserting slots 401.
In this embodiment: pins 501 mounted on both sides of each semiconductor package body 5 are matched with the socket 401.
Referring to fig. 1-4, a plurality of test wires 6 are fixedly connected in the mounting block 101, and the plurality of test wires 6 are electrically connected with a plurality of springs 601 respectively.
In this embodiment: the test lines 6 are four, two test lines 6 are arranged in four rows of inserting grooves 401 in the middle, and two test lines 6 are arranged on two sides of the two rows of inserting grooves 401 on the far side.
Referring specifically to fig. 1-4, mounting block 101 has dimensions of 20 x 15cm.
In this embodiment: the mounting block 101 of this size is used for mounting three semiconductor package main bodies 5.
What needs to be explained is: the specific type of the semiconductor package body 5 and the electric putter 703 are selected by those skilled in the art, and the above related semiconductor package body 5 and electric putter 703 are all in the prior art, and the present solution is not repeated.
The working principle and the using flow of the invention are as follows: when the device is used, firstly, the semiconductor package main body 5 to be tested is arranged in the tool main body 1, pins 501 arranged at two side ends of the semiconductor package main body 5 slide into the inserting grooves 401, and the elastic force of the springs 601 drives the test wires 6 to slide on the surfaces of the pins 501, so that the pins 501 are stably arranged in the inserting grooves 401; the clamping assembly is controlled to operate, an electric push rod 703 in the clamping assembly operates to drive clamping plates 7 connected with output ends of the clamping assembly to move, and the two clamping plates 7 are matched and clamped on the surfaces of the semiconductor packaging main bodies 5, so that the semiconductor packaging main bodies 5 are stably installed; then the cover plate 3 is controlled to rotate through the handle 302, the cover plate 3 is closed on the surface of the tool main body 1, and finally the tool main body 1 is placed in test equipment, so that a plurality of connector lugs 4 are connected with the test equipment; finally, testing the semiconductor packaging test fixture; through this device, place when semiconductor package tests and fix a position in the frock, and semiconductor package main part 5 is installed in frock main part 1, is connected with pin 501 by elastic component, and the centre gripping is at the surface of semiconductor package main part 5 by two sets of clamping components, and installation semiconductor package main part 5 is all very convenient with dismantling semiconductor package main part 5, compares in traditional use soldering fixed, reduces the required time when fixed, improves the test speed of frock.
Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. The utility model provides a semiconductor package test fixture which characterized in that includes:
the tool comprises a tool main body (1), wherein an installation block (101) is fixedly connected to the lower inner wall of the tool main body (1);
the plurality of inserting grooves (401) are formed, the plurality of inserting grooves (401) are formed in the upper end of the mounting block (101), and elastic components are arranged in each inserting groove (401);
the clamping assembly is provided with two groups, each group of clamping assembly comprises a clamping plate (7), sliding blocks (701), sliding rods (702) and an electric push rod (703), the sliding blocks (701) and the sliding rods (702) are respectively provided with two sliding rods (702), the two sliding rods (702) are fixedly connected to one side end of the mounting block (101) and one side inner wall of the tool main body (1), the electric push rods (703) are fixedly connected to one side inner wall of the tool main body (1), the clamping plates (7) are fixedly connected to the extending ends of the electric push rods (703), the two sliding blocks (701) are respectively fixedly connected to two side ends of the clamping plates (7), and the two sliding blocks (701) are respectively and slidably connected to the circumferential surfaces of the two sliding rods (702);
a plurality of semiconductor packaging main bodies (5) are arranged in the tool main body (1), a plurality of pins (501) are fixedly connected to two side ends of each semiconductor packaging main body (5), and the pins (501) are respectively and slidably connected to the plurality of inserting grooves (401);
each group of elastic components comprises a spring (601) and a test wire (6), the spring (601) is fixedly connected to one side inner wall of the inserting groove (401), the test wire (6) is fixedly connected to one side end of the spring (601), the groove is formed in the surface of the pin (501), the metal elastic block (602) is connected with the spring (601), and the metal elastic block (602) is matched with the groove.
2. The semiconductor package testing tool according to claim 1, wherein: two side ends of the tool main body (1) are fixedly connected with two connector lugs (4).
3. The semiconductor package testing tool according to claim 2, wherein: the upper end of the tool main body (1) is fixedly connected with two top plates (2).
4. A semiconductor package testing tool according to claim 3, wherein: the close ends of the two top plates (2) are movably hinged with cover plates (3) through hinge shafts, and two side ends of the two cover plates (3) are fixedly connected with handles (302).
5. The semiconductor package testing tool according to claim 4, wherein: glass holes (301) are formed in the upper ends of the two cover plates (3), and glass is fixedly connected in the two glass holes (301).
6. The semiconductor package testing tool according to claim 5, wherein: a plurality of test wires (6) are fixedly connected in the mounting block (101), and the test wires (6) are respectively and electrically connected with the springs (601).
7. The semiconductor package testing tool according to claim 6, wherein: the size of the mounting block (101) is 2015cm。
8. A testing method of a semiconductor package testing fixture using the semiconductor package testing fixture according to any one of claims 1 to 7, comprising the steps of:
s1, mounting a semiconductor package: firstly, a semiconductor packaging main body (5) to be tested is arranged in a tool main body (1), pins (501) arranged at two side ends of the semiconductor packaging main body (5) slide into a plug-in groove (401), and a test wire (6) is driven to slide on the surface of the pins (501) through the elasticity of a spring (601), so that the pins (501) are stably arranged in the plug-in groove (401);
s2, fixing and packaging: the clamping assembly is controlled to operate, an electric push rod (703) in the clamping assembly operates to drive clamping plates (7) connected with output ends of the clamping plates to move, and the two clamping plates (7) are clamped on the surfaces of the semiconductor packaging main bodies (5) in a matched mode, so that the semiconductor packaging main bodies (5) are stably installed;
s3, connecting a tool: then the cover plate (3) is controlled to rotate through the handle (302), the cover plate (3) is closed on the surface of the tool main body (1), and finally the tool main body (1) is placed in test equipment, so that a plurality of connector lugs (4) are connected with the test equipment;
s4, testing: and finally, testing the semiconductor packaging test fixture.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311075749.8A CN116819286B (en) | 2023-08-25 | 2023-08-25 | Semiconductor package testing tool and testing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311075749.8A CN116819286B (en) | 2023-08-25 | 2023-08-25 | Semiconductor package testing tool and testing method thereof |
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| Publication Number | Publication Date |
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| CN116819286A CN116819286A (en) | 2023-09-29 |
| CN116819286B true CN116819286B (en) | 2023-11-24 |
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| CN116819286B (en) * | 2023-08-25 | 2023-11-24 | 成都宇熙电子技术有限公司 | Semiconductor package testing tool and testing method thereof |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990002003U (en) * | 1997-06-25 | 1999-01-15 | 김영환 | Jig for semiconductor package test |
| JP2005337904A (en) * | 2004-05-27 | 2005-12-08 | New Japan Radio Co Ltd | Fixture and method for measuring semiconductor device characteristics |
| KR101245837B1 (en) * | 2012-03-28 | 2013-03-20 | (주)마이크로컨텍솔루션 | Socket device for testing a ic package |
| CN209231471U (en) * | 2018-12-05 | 2019-08-09 | 福建福顺半导体制造有限公司 | A kind of encapsulation chip testing structure |
| CN211603437U (en) * | 2019-12-24 | 2020-09-29 | 上海北臻电子科技有限公司 | Semiconductor static testing device |
| CN214473743U (en) * | 2021-03-02 | 2021-10-22 | 江苏钰晶半导体科技有限公司 | Withstand voltage testing device of discrete semiconductor device |
| CN113567827A (en) * | 2021-09-26 | 2021-10-29 | 山东元捷电子科技有限公司 | Electrical performance test tool for semiconductor device |
| CN214622875U (en) * | 2021-01-29 | 2021-11-05 | 标景精密科技(苏州)有限公司 | Semiconductor integrated circuit chip test equipment |
| CN113643998A (en) * | 2021-08-02 | 2021-11-12 | 东莞先导先进科技有限公司 | Semiconductor packaging test system and method |
| CN216435871U (en) * | 2021-12-23 | 2022-05-03 | 深圳市合泰智造技术有限公司 | Testing mechanism of semiconductor testing and braiding integrated machine |
| CN218298320U (en) * | 2022-07-28 | 2023-01-13 | 弘润半导体(苏州)有限公司 | Adjustable test fixture for discrete semiconductor device |
| CN218447817U (en) * | 2022-08-10 | 2023-02-03 | 深圳明嘉瑞科技有限公司 | Measuring tool for integrated circuit processing |
| CN116564917A (en) * | 2023-05-16 | 2023-08-08 | 深圳市金誉半导体股份有限公司 | Semiconductor packaging substrate structure and manufacturing process thereof |
| CN116819286A (en) * | 2023-08-25 | 2023-09-29 | 成都宇熙电子技术有限公司 | Semiconductor package testing tool and testing method thereof |
-
2023
- 2023-08-25 CN CN202311075749.8A patent/CN116819286B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990002003U (en) * | 1997-06-25 | 1999-01-15 | 김영환 | Jig for semiconductor package test |
| JP2005337904A (en) * | 2004-05-27 | 2005-12-08 | New Japan Radio Co Ltd | Fixture and method for measuring semiconductor device characteristics |
| KR101245837B1 (en) * | 2012-03-28 | 2013-03-20 | (주)마이크로컨텍솔루션 | Socket device for testing a ic package |
| CN209231471U (en) * | 2018-12-05 | 2019-08-09 | 福建福顺半导体制造有限公司 | A kind of encapsulation chip testing structure |
| CN211603437U (en) * | 2019-12-24 | 2020-09-29 | 上海北臻电子科技有限公司 | Semiconductor static testing device |
| CN214622875U (en) * | 2021-01-29 | 2021-11-05 | 标景精密科技(苏州)有限公司 | Semiconductor integrated circuit chip test equipment |
| CN214473743U (en) * | 2021-03-02 | 2021-10-22 | 江苏钰晶半导体科技有限公司 | Withstand voltage testing device of discrete semiconductor device |
| CN113643998A (en) * | 2021-08-02 | 2021-11-12 | 东莞先导先进科技有限公司 | Semiconductor packaging test system and method |
| CN113567827A (en) * | 2021-09-26 | 2021-10-29 | 山东元捷电子科技有限公司 | Electrical performance test tool for semiconductor device |
| CN216435871U (en) * | 2021-12-23 | 2022-05-03 | 深圳市合泰智造技术有限公司 | Testing mechanism of semiconductor testing and braiding integrated machine |
| CN218298320U (en) * | 2022-07-28 | 2023-01-13 | 弘润半导体(苏州)有限公司 | Adjustable test fixture for discrete semiconductor device |
| CN218447817U (en) * | 2022-08-10 | 2023-02-03 | 深圳明嘉瑞科技有限公司 | Measuring tool for integrated circuit processing |
| CN116564917A (en) * | 2023-05-16 | 2023-08-08 | 深圳市金誉半导体股份有限公司 | Semiconductor packaging substrate structure and manufacturing process thereof |
| CN116819286A (en) * | 2023-08-25 | 2023-09-29 | 成都宇熙电子技术有限公司 | Semiconductor package testing tool and testing method thereof |
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