CN116564917A - Semiconductor packaging substrate structure and manufacturing process thereof - Google Patents
Semiconductor packaging substrate structure and manufacturing process thereof Download PDFInfo
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- CN116564917A CN116564917A CN202310550773.6A CN202310550773A CN116564917A CN 116564917 A CN116564917 A CN 116564917A CN 202310550773 A CN202310550773 A CN 202310550773A CN 116564917 A CN116564917 A CN 116564917A
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- box body
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- cover plate
- heat dissipation
- fixedly connected
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- 239000000758 substrate Substances 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 230000017525 heat dissipation Effects 0.000 claims description 27
- 229910052802 copper Inorganic materials 0.000 claims description 20
- 239000010949 copper Substances 0.000 claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 230000008093 supporting effect Effects 0.000 claims description 19
- 239000000428 dust Substances 0.000 claims description 11
- 238000001125 extrusion Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000003466 welding Methods 0.000 claims description 2
- 238000009434 installation Methods 0.000 abstract description 2
- 238000005538 encapsulation Methods 0.000 abstract 2
- 230000006978 adaptation Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 49
- 238000001816 cooling Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 230000003139 buffering effect Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000009423 ventilation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Packaging Frangible Articles (AREA)
Abstract
The invention relates to the technical field of semiconductors, in particular to a semiconductor packaging substrate structure and a manufacturing process thereof; including base plate, the wafer, many wires, a plurality of pad, a plurality of pin and encapsulation subassembly, encapsulation subassembly includes the box body, the apron, many guide bars, many support and hold the spring, many pull rods and the spacing arc piece of polylith, base plate and box body looks adaptation, the apron sets up in the top of box body, a plurality of spacing chambeies of box body, every spacing arc piece sets up respectively in the spacing intracavity that corresponds, every both ends that support the spring respectively with box body and the spacing arc piece fixed connection that corresponds, every pull rod respectively with the spacing arc piece fixed connection that corresponds, many guide bars all with apron fixed connection, every guide bar all has the fixed orifices, through the setting of above-mentioned structure, it is convenient for encapsulate the semiconductor to have realized, the connected mode is simple, do benefit to the installation and the dismantlement of semiconductor.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor packaging substrate structure and a manufacturing process thereof.
Background
The semiconductor packaging generally refers to packaging and protecting an independent chip by using a plastic shell, so that a better working environment is conveniently provided for the semiconductor element, and the semiconductor element is prevented from being influenced by external factors to perform normal and stable operation. The existing semiconductor element is usually larger in size after packaging, meanwhile, the packaging stability is insufficient, so that the packaging shell is easy to loose, and normal installation and use of the semiconductor element are not facilitated.
In the prior art patent CN210467799U discloses a semiconductor packaging structure, which comprises a substrate, a wafer, a wire, a bonding pad, a pin and a packaging layer, wherein the wafer is mounted on the substrate through a mounting groove, the thickness between the wafer and the substrate is reduced, so that the packaging thickness of a semiconductor element is reduced, packaging is convenient, and the packaging layer is connected with the substrate through a connecting pin and a limiting groove, thereby improving the packaging stability of the packaging layer.
However, in the above method, the semiconductor is mounted on the substrate and packaged by the package layer, and the connection method is complicated, and it takes a lot of time, which is inconvenient to mount and dismount.
Disclosure of Invention
The invention aims to provide a semiconductor packaging substrate structure and a manufacturing process thereof, which solve the problems that the prior semiconductor is mounted on a substrate, packaged by a packaging layer, the connection mode is complex, a great deal of time is required, and the mounting and the dismounting are inconvenient.
In order to achieve the above object, the semiconductor package substrate structure adopted by the invention comprises a substrate, a wafer, a plurality of wires, a plurality of bonding pads, a plurality of pins and a package assembly, wherein the substrate is provided with a mounting groove, the wafer is arranged in the mounting groove, the plurality of pins are respectively arranged on the substrate, each of the pins is provided with the bonding pad, each of the bonding pads is provided with the wire, each of the wires is respectively connected with the wafer, the package assembly comprises a box body, a cover plate, a plurality of guide rods, a plurality of supporting springs, a plurality of pull rods and a plurality of limit arc blocks, the substrate is matched with the box body, the cover plate is arranged above the box body, a plurality of limit cavities are respectively arranged in the corresponding limit cavities, two ends of each supporting spring are respectively fixedly connected with the box body and the corresponding limit arc blocks, each pull rod is respectively fixedly connected with the corresponding limit arc blocks, and is respectively inserted into the corresponding guide rods and is respectively fixedly connected with the corresponding limit arc blocks, and each guide rod is respectively matched with the corresponding limit arc cavities.
The packaging assembly further comprises a plurality of extrusion arc blocks, and each extrusion arc block is fixedly connected with the corresponding guide rod.
The packaging assembly further comprises a plurality of protecting covers, wherein the protecting covers are detachably connected with the box body and are respectively positioned outside the pull rod.
The semiconductor packaging substrate structure further comprises a heat dissipation assembly, the cover plate is provided with a plurality of vent holes, two sides of the box body are respectively provided with a plurality of heat dissipation holes, and the heat dissipation assembly is arranged above the cover plate.
The heat dissipation assembly comprises a mounting frame, a heat dissipation fan, a dust screen and a plurality of limit bolts, wherein the mounting frame is arranged above the cover plate, the heat dissipation fan is fixedly connected with the mounting frame and is positioned in the mounting frame, the dust screen is fixedly connected with the mounting frame and is positioned above the heat dissipation fan, and each limit bolt penetrates through the mounting frame respectively and is in threaded fit with the cover plate.
The heat dissipation assembly further comprises a copper plate and a plurality of heat conduction columns, wherein the copper plate is fixedly connected with the cover plate and is located on the outer wall of the copper plate, each heat conduction column is connected with the copper plate and penetrates through the cover plate, and the heat conduction columns are uniformly distributed above the copper plate.
The invention also provides a semiconductor package manufacturing process, which is applied to the semiconductor package substrate structure and comprises the following steps:
coating an adhesive substance in the mounting groove of the substrate;
placing the wafer in the mounting groove to fix the wafer on the substrate;
welding two ends of the lead with the wafer and the bonding pad on the pin respectively;
and packaging the wafer by using the cover plate and the box body.
According to the semiconductor packaging substrate structure and the manufacturing process thereof, when the wafers are packaged, the wafers are arranged in the mounting grooves on the substrate, the pins are connected with the wafers through the bonding pads and the wires, after the connection is completed, the substrates are placed in the box body, the guide rods on the cover plate are respectively inserted into the limiting cavities of the box body, the guide rods enter the limiting cavities to extrude the limiting arc blocks, the limiting arc blocks extrude the supporting springs, and when each guide rod completely enters the limiting cavities, the elastic force of the supporting springs pushes the limiting arc blocks to enter the fixing holes of the guide rods, and then the cover plate is fixed in the box body, so that the packaging of the wafers is completed; when the cover plate needs to be opened from the box body, the pull rods are pulled through the outer walls of the box body respectively, at the moment, the pull rods drive the limiting arc blocks to leave the fixing holes on the guide rods, then the cover plate is separated from the box body, and then the wafer is detached.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic overall structure of a first embodiment of the present invention.
Fig. 2 is a cross-sectional view of the overall internal structure of the first embodiment of the present invention.
Fig. 3 is a cross-sectional view showing the internal structure of the package assembly according to the first embodiment of the present invention.
Fig. 4 is an enlarged view of the partial structure at a of fig. 3 according to the present invention.
Fig. 5 is a schematic overall structure of a second embodiment of the present invention.
Fig. 6 is a cross-sectional view of the overall internal structure of a second embodiment of the present invention.
Fig. 7 is a cross-sectional view of the overall internal structure of a third embodiment of the present invention.
Fig. 8 is an enlarged view of the partial structure at B of fig. 7 according to the present invention.
Fig. 9 is a flow chart of steps of the semiconductor package fabrication process of the present invention.
101-base plate, 102-wafer, 103-wire, 104-pad, 105-pin, 106-box, 107-cover plate, 108-guide bar, 109-holding spring, 110-pull bar, 111-limit arc block, 112-extrusion arc block, 113-protecting cover, 114-limit cavity, 115-fixing hole, 116-mounting groove, 201-mounting frame, 202-radiator fan, 203-dust screen, 204-limit bolt, 205-copper plate, 206-heat conducting column, 207-vent hole, 208-heat radiating hole, 301-support plate, 302-buffer spring, 303-inner rod, 304-outer cylinder.
The first embodiment is:
referring to fig. 1 to 4, fig. 1 is a schematic overall structure of the first embodiment, fig. 2 is a sectional view of an overall internal structure of the first embodiment, fig. 3 is a sectional view of an internal structure of a package assembly of the first embodiment, and fig. 4 is a partial enlarged view of a portion of fig. 3 a. The invention provides a semiconductor packaging substrate 101 structure, which comprises a substrate 101, a wafer 102, a plurality of leads 103, a plurality of bonding pads 104, a plurality of pins 105 and a packaging assembly, wherein the packaging assembly comprises a box body 106, a cover plate 107, a plurality of guide rods 108, a plurality of supporting springs 109, a plurality of pull rods 110, a plurality of limiting arc blocks 111, a plurality of extrusion arc blocks 112 and a plurality of protecting covers 113;
for this embodiment, the substrate 101 has a mounting groove 116, the die 102 is disposed in the mounting groove 116, the plurality of pins 105 are respectively disposed on the substrate 101, each of the pins 105 is provided with a bonding pad 104, each of the bonding pads 104 is provided with a wire 103, each of the wires 103 is respectively connected with the die 102, when the die 102 is packaged, the die 102 is disposed in the mounting groove 116 on the substrate 101, and the pins 105 are connected with the die 102 through the bonding pads 104 and the wires 103.
The substrate 101 is matched with the box body 106, the cover plate 107 is arranged above the box body 106, the box body 106 is provided with a plurality of limiting cavities 114, each limiting arc block 111 is respectively arranged in the corresponding limiting cavity 114, two ends of each supporting spring 109 are respectively fixedly connected with the box body 106 and the corresponding limiting arc block 111, each pull rod 110 is respectively fixedly connected with the corresponding limiting arc block 111 and is respectively inserted into the corresponding limiting cavity 114, the guide rods 108 are respectively fixedly connected with the cover plate 107 and are respectively matched with the corresponding limiting cavity 114, each guide rod 108 is provided with a fixing hole 115, each limiting arc block 111 is respectively matched with the corresponding fixing hole 115, when the substrate 101 is placed in the box body 106, the guide rods 108 on the cover plate 107 are respectively inserted into the limiting cavities 114 of the box body 106, the guide rods 108 enter the limiting arc blocks 114 and are respectively pushed into the limiting arc blocks 111, and the guide rods 108 are completely pushed into the limiting cavities 111 when the supporting spring 108 are pushed into the limiting cavities 106, and the guide rods 108 are completely pushed into the limiting cavities 111, and when the supporting arc blocks 108 are completely pushed into the limiting arc blocks 108 and the limiting arc blocks 108 are completely pushed into the limiting cavities 106; when the cover plate 107 needs to be opened from the box body 106, the pull rods 110 are pulled respectively through the outer wall of the box body 106, at this time, the pull rods 110 drive the limiting arc blocks 111 to leave the fixing holes 115 on the guide rods 108, then the cover plate 107 is separated from the box body 106, and then the wafer 102 is detached.
Secondly, each extrusion arc block 112 is fixedly connected with the corresponding guide rod 108, the extrusion arc blocks 112 are provided with cambered surfaces, and the extrusion arc blocks 112 are arranged on the guide rods 108, so that the guide rods 108 can conveniently extrude the limit arc blocks 111, and the guide rods 108 can conveniently enter the limit cavities 114.
Meanwhile, the protecting covers 113 are all detachably connected with the box body 106 and are respectively located outside the pull rod 110, and the protecting covers 113 can cover the outside of the pull rod 110, so that the pull rod 110 is prevented from being exposed and easy to be touched by mistake.
When the wafer 102 is packaged, the wafer 102 is arranged in the mounting groove 116 on the substrate 101, the pins 105 are connected with the wafer 102 through the bonding pads 104 and the wires 103, after the connection is completed, the substrate 101 is placed in the box body 106, then the guide rods 108 on the cover plate 107 are respectively inserted into the limiting cavities 114 of the box body 106, the guide rods 108 enter the limiting cavities 114, the pressing arc blocks 112 on the guide rods 108 press the limiting arc blocks 111, the limiting arc blocks 111 press the supporting springs 109, and when each guide rod 108 completely enters the limiting cavities 114, the elastic force of the supporting springs 109 pushes the limiting arc blocks 111 to enter the fixing holes 115 of the guide rods 108, and at this time, the cover plate 107 is fixed in the box body 106, so that the packaging of the wafer 102 is completed; when the cover plate 107 needs to be opened from the box body 106, the protecting cover 113 is detached from the outer wall of the box body 106, a plurality of pull rods 110 are exposed, the pull rods 110 are pulled by the outer wall of the box body 106 respectively, at this time, the pull rods 110 drive the limit arc blocks 111 to leave the fixing holes 115 on the guide rods 108, then the cover plate 107 is separated from the box body 106, and then the wafer 102 is detached.
The second embodiment is:
on the basis of the first embodiment, please refer to fig. 5 and 6, wherein fig. 5 is a schematic overall structure of the second embodiment, and fig. 6 is a sectional view of an overall internal structure of the second embodiment. The invention provides a semiconductor packaging substrate 101 structure which also comprises a heat dissipation assembly, wherein the heat dissipation assembly comprises a mounting frame 201, a heat dissipation fan 202, a dust screen 203, a plurality of limit bolts 204, a copper plate 205 and a plurality of heat conduction columns 206;
for this embodiment, the cover 107 has a plurality of ventilation holes 207, two sides of the case 106 have a plurality of heat dissipation holes 208, and the heat dissipation component is disposed above the cover 107, so that the heat dissipation effect of the wafer 102 in the case 106 can be increased by the heat dissipation component, which is beneficial to the use of the wafer 102.
The mounting frame 201 is disposed above the cover plate 107, the cooling fan 202 is fixedly connected with the mounting frame 201, and is located in the mounting frame 201, the dust screen 203 is fixedly connected with the mounting frame 201, and is located above the cooling fan 202, each limit bolt 204 penetrates through the mounting frame 201 respectively and is in threaded fit with the cover plate 107, the mounting frame 201 is fixedly supported by the cover plate 107 on the cooling fan 202, cold air enters the box body 106 through the vent holes 207 on the cover plate 107, then the cold air exchanges heat in the box body 106, heat is discharged through the cooling holes 208 on two sides of the box body 106, the dust screen 203 prevents dust from accumulating at the cooling fan 202, the effect that the heat dissipation effect of the wafer 102 in the box body 106 can be increased is achieved, and the use of the wafer 102 is facilitated.
Secondly, the copper plate 205 is fixedly connected with the cover plate 107, and is located on an outer wall of the copper plate 205, each heat conduction column 206 is connected with the copper plate 205 and penetrates through the cover plate 107, the plurality of heat conduction columns 206 are uniformly distributed above the copper plate 205, the copper plate 205 is in contact with the wafer 102, and heat generated by operation of the wafer 102 is conducted through the copper plate 205 and the heat conduction columns 206, so that a heat dissipation effect of the wafer 102 in the box 106 can be further improved.
The mounting frame 201 is fixedly supported by the cover plate 107 on the cooling fan 202, the cooling fan 202 enables cold air to enter the box body 106 through the vent holes 207 on the cover plate 107, then the cold air exchanges heat in the box body 106, heat is discharged through the cooling holes 208 on two sides of the box body 106, dust is prevented from accumulating at the cooling fan 202 by the dust screen 203, the copper plate 205 is contacted with the wafer 102, heat generated by operation of the wafer 102 is conducted through the copper plate 205 and the heat conducting columns 206, the heat dissipation effect of the wafer 102 in the box body 106 can be further improved, the heat dissipation effect of the wafer 102 in the box body 106 can be increased, and the use of the wafer 102 is facilitated.
The third embodiment is:
on the basis of the second embodiment, please refer to fig. 7 and 8, wherein fig. 7 is a cross-sectional view of the overall internal structure of the third embodiment, and fig. 8 is an enlarged view of the partial structure at B of fig. 7. The invention provides a semiconductor packaging substrate 101 structure, which also comprises a buffer assembly, wherein the buffer assembly comprises a supporting plate 301, a plurality of buffer springs 302 and a plurality of telescopic rods, and the telescopic rods comprise an inner rod 303 and an outer cylinder 304;
for this embodiment, the buffer assembly is disposed in the box 106, and the wafer 102 and the substrate 101 can be protected by the buffer assembly, so as to avoid the wafer 102 from being damaged during the transportation process.
The supporting plate 301 is disposed below the substrate 101, two ends of each telescopic rod are fixedly connected with the substrate 101 and the box body 106 respectively, two ends of each buffer spring 302 are fixedly connected with the substrate 101 and the box body 106 respectively and are sleeved outside the corresponding telescopic rods respectively, the supporting plate 301 and the buffer springs 302 are used for buffering and supporting the substrate 101 in the box body 106, when the box body 106 collides with the outside, the buffer springs 302 deform, the telescopic rods stretch along with the buffer springs 302, and the wafers 102 on the substrate 101 are buffered and protected through the elastic effect of the buffer springs 302, so that the wafers 102 are prevented from being damaged in the transportation process.
Secondly, the outer cylinder 304 is fixedly connected with the box body 106 and is located in the box body 106, one end of the inner rod 303 is slidably connected with the outer cylinder 304, the other end of the inner rod 303 is fixedly connected with the support plate 301, the inner rod 303 can slide and stretch in the outer cylinder 304 and change along with the expansion and contraction of the buffer spring 302, and the supporting effect and the buffering effect on the wafer 102 can be further improved through the arrangement of the inner rod 303 and the outer cylinder 304.
The supporting plate 301 and the buffer spring 302 are used for buffering and supporting the substrate 101 in the box body 106, when the box body 106 collides with the outside, the buffer spring 302 deforms, meanwhile, the inner rod 303 slides and stretches in the outer cylinder 304, and the wafer 102 on the substrate 101 is buffered and protected through the elastic effect of the buffer spring 302, so that the wafer 102 and the substrate 101 can be protected, and the wafer 102 is prevented from being damaged in the transportation process.
Referring to fig. 9, a flow chart of steps of the semiconductor package manufacturing process of fig. 9 is shown.
The invention also provides a semiconductor package manufacturing process, which is applied to the semiconductor package substrate 101 structure and comprises the following steps:
s1: an adhesive substance is applied to the mounting groove 116 of the substrate 101;
s2: placing the wafer 102 in the mounting groove 116 to fix the wafer 102 on the substrate 101;
s3: soldering both ends of the wire 103 to the bonding pads 104 on the die 102 and the leads 105, respectively;
s4: the wafer 102 is encapsulated using the cover 107 and the cassette 106.
In this embodiment, an adhesive substance is applied to the mounting groove 116 of the substrate 101, the wafer 102 is placed in the mounting groove 116, the wafer 102 is fixed to the substrate 101, both ends of the wire 103 are soldered to the wafer 102 and the pads 104 on the leads 105, respectively, and finally the wafer 102 is packaged by using the cover 107 and the case 106.
The above disclosure is only a preferred embodiment of the present invention, and it should be understood that the scope of the invention is not limited thereto, and those skilled in the art will appreciate that all or part of the procedures described above can be performed according to the equivalent changes of the claims, and still fall within the scope of the present invention.
Claims (7)
1. The semiconductor package substrate structure comprises a substrate, a wafer, multiple wires, multiple bonding pads and multiple pins, wherein the substrate is provided with a mounting groove, the wafer is arranged in the mounting groove, the multiple pins are respectively arranged on the substrate, each pin is provided with a bonding pad, each bonding pad is provided with a wire, each wire is respectively connected with the wafer,
the packaging assembly comprises a box body, a cover plate, a plurality of guide rods, a plurality of supporting springs, a plurality of pull rods and a plurality of limiting arc blocks, wherein the base plate is matched with the box body, the cover plate is arranged above the box body, the box body is provided with a plurality of limiting cavities, each limiting arc block is respectively arranged in the corresponding limiting cavity, each supporting spring is respectively fixedly connected with the box body and the corresponding limiting arc block at two ends, each pull rod is respectively fixedly connected with the corresponding limiting arc block, is respectively inserted into the corresponding limiting cavity, and is respectively fixedly connected with the cover plate and is respectively matched with the corresponding limiting cavity, each guide rod is provided with a fixing hole, and each limiting arc block is respectively matched with the corresponding fixing hole.
2. The semiconductor package substrate structure of claim 1, wherein,
the packaging assembly further comprises a plurality of extrusion arc blocks, and each extrusion arc block is fixedly connected with the corresponding guide rod.
3. The semiconductor package substrate structure of claim 2, wherein,
the packaging assembly further comprises a plurality of protecting covers, wherein the protecting covers are detachably connected with the box body and are respectively positioned outside the pull rod.
4. The semiconductor package substrate structure of claim 3, wherein,
the semiconductor packaging substrate structure further comprises a heat dissipation assembly, the cover plate is provided with a plurality of vent holes, two sides of the box body are respectively provided with a plurality of heat dissipation holes, and the heat dissipation assembly is arranged above the cover plate.
5. The semiconductor package substrate structure of claim 4, wherein,
the heat dissipation assembly comprises a mounting frame, a heat dissipation fan, a dust screen and a plurality of limit bolts, wherein the mounting frame is arranged above the cover plate, the heat dissipation fan is fixedly connected with the mounting frame and is positioned in the mounting frame, the dust screen is fixedly connected with the mounting frame and is positioned above the heat dissipation fan, and each limit bolt penetrates through the mounting frame respectively and is in threaded fit with the cover plate.
6. The semiconductor package substrate structure of claim 5, wherein,
the heat dissipation assembly further comprises a copper plate and a plurality of heat conduction columns, wherein the copper plate is fixedly connected with the cover plate and is positioned on the outer wall of the copper plate, each heat conduction column is connected with the copper plate and penetrates through the cover plate, and the plurality of heat conduction columns are uniformly distributed above the copper plate.
7. A semiconductor package fabrication process applied to the semiconductor package substrate structure of claim 4, comprising the steps of:
coating an adhesive substance in the mounting groove of the substrate;
placing the wafer in the mounting groove to fix the wafer on the substrate;
welding two ends of the lead with the wafer and the bonding pad on the pin respectively;
and packaging the wafer by using the cover plate and the box body.
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| CN202310550773.6A CN116564917B (en) | 2023-05-16 | 2023-05-16 | Semiconductor packaging substrate structure and manufacturing process thereof |
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| CN202310550773.6A CN116564917B (en) | 2023-05-16 | 2023-05-16 | Semiconductor packaging substrate structure and manufacturing process thereof |
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| CN116564917B CN116564917B (en) | 2024-06-28 |
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Cited By (1)
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| CN116819286A (en) * | 2023-08-25 | 2023-09-29 | 成都宇熙电子技术有限公司 | Semiconductor package testing tool and testing method thereof |
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| CN113932079A (en) * | 2021-09-10 | 2022-01-14 | 重庆山堆石机械制造有限公司 | Easy dismouting ball valve |
| CN218884293U (en) * | 2022-12-17 | 2023-04-18 | 广东竣凯电器有限公司 | Electric water heater anticreep device |
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| CN116819286A (en) * | 2023-08-25 | 2023-09-29 | 成都宇熙电子技术有限公司 | Semiconductor package testing tool and testing method thereof |
| CN116819286B (en) * | 2023-08-25 | 2023-11-24 | 成都宇熙电子技术有限公司 | Semiconductor package testing tool and testing method thereof |
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