CN116759438A - Device manufacturing method and transistor device - Google Patents

Device manufacturing method and transistor device Download PDF

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Publication number
CN116759438A
CN116759438A CN202310644602.XA CN202310644602A CN116759438A CN 116759438 A CN116759438 A CN 116759438A CN 202310644602 A CN202310644602 A CN 202310644602A CN 116759438 A CN116759438 A CN 116759438A
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CN
China
Prior art keywords
wafer
source
region
power supply
target
Prior art date
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Pending
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CN202310644602.XA
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Chinese (zh)
Inventor
王延锋
吴恒
黄达
李作
林冠贤
施雪捷
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Bitmain Technologies Inc
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Bitmain Technologies Inc
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Application filed by Bitmain Technologies Inc filed Critical Bitmain Technologies Inc
Priority to CN202310644602.XA priority Critical patent/CN116759438A/en
Publication of CN116759438A publication Critical patent/CN116759438A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Abstract

The embodiment of the disclosure provides a device manufacturing method and a transistor device, wherein the device manufacturing method comprises the following steps: forming an air gap in a target area on a wafer; the target area includes: a region between the target location and the gate; the target position is a position where the source electrode contacts the power supply circuit. Therefore, parasitic capacitance between the grid electrode and the power supply circuit can be reduced based on the air gap, and device and circuit performance are improved.

Description

Device manufacturing method and transistor device
Technical Field
The present disclosure relates to the field of microelectronic devices, and more particularly to a device fabrication method and a transistor device.
Background
In the related art, there is often a large parasitic capacitance between the power supply line and the gate of the transistor device, for example, in a device applying the technology of a back side power supply network (BackSidePowerDeliveryNetwork, BSPDN), there is a large parasitic capacitance between the back side power supply line and the gate, which is unfavorable for further reducing transistor parasitics, resulting in limited overall circuit performance.
Disclosure of Invention
The embodiment of the disclosure provides a device manufacturing method and a transistor device.
A first aspect of an embodiment of the present disclosure provides a device manufacturing method, the method including:
forming an air gap in a target area on a wafer; the target area includes: a region between the target location and the gate; the target position is a position where the source electrode contacts the power supply circuit.
Based on the above scheme, the forming the air gap located in the target area on the wafer includes:
forming a groove in a target area on the back surface of the wafer through selective etching treatment;
an air gap is formed by filling an insulating material in the trench.
Based on the above, after the forming of the air gap by filling the trench with the insulating material, the method further includes:
and contacting a source electrode with the power supply circuit at the target position.
Based on the above solution, the contacting the source with the power supply circuit at the target position includes:
and punching holes in the target position through photoetching, and enabling the source electrode to be in contact with the power supply circuit.
Based on the above scheme, before the target area on the back surface of the wafer is formed with the trench by selective etching treatment, the method further includes:
bonding the front surface of the wafer with the carrier sheet;
and turning over the wafer, and thinning the back of the wafer.
Based on the above scheme, before bonding the front surface of the wafer with the carrier, the method further includes:
filling a sacrificial layer material in the source electrode region and the drain electrode region;
performing epitaxial growth of a source electrode and/or a drain electrode based on the position of the sacrificial layer material;
and performing a front-end process, a middle-end process and a back-end process on the wafer.
Based on the above scheme, the thinning processing of the back surface of the wafer includes:
and thinning the back surface of the wafer until the sacrificial layer material is exposed.
Based on the scheme, the front-end process at least comprises the following steps: source, drain, and gate forming operations.
Based on the above, before the source region and the drain region are filled with the sacrificial layer material, the method further includes:
performing epitaxial growth of the substrate on the wafer; the substrate comprises: a nanosheet;
and manufacturing a pseudo gate and a space layer in the epitaxial growth area of the substrate, and etching a source electrode and a drain electrode to obtain a source electrode area and a drain electrode area.
A second aspect of the disclosed embodiments provides a transistor device manufactured by the device manufacturing method according to one or more of the foregoing technical solutions.
The technical scheme provided by the embodiment of the disclosure can comprise the following beneficial effects:
the device manufacturing method provided by the embodiment of the disclosure comprises the following steps: forming an air gap in a target area on a wafer; the target area includes: a region between the target location and the gate; the target position is a position where the source electrode contacts the power supply circuit. Therefore, the insulation between the grid electrode and the power supply circuit can be improved through the air gap, so that parasitic capacitance between the grid electrode and power supply lines of the power supply circuit is reduced, overall parasitic of the transistor is reduced, and the performance of the transistor and the circuit is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a flow diagram illustrating a device manufacturing method according to an exemplary embodiment;
fig. 2 is a schematic structural view of a device in the related art;
FIG. 3 is a schematic diagram of a device made by a device fabrication method according to an exemplary embodiment;
FIG. 4 is a flow diagram illustrating a device manufacturing method according to an example embodiment;
FIG. 5 is a flow diagram illustrating a device manufacturing method according to an example embodiment;
FIG. 6 is a schematic diagram of a device made by a device manufacturing method according to an exemplary embodiment;
FIG. 7 is a schematic diagram of a device made by a device manufacturing method according to an exemplary embodiment;
FIG. 8 is a schematic diagram of a device made by a device manufacturing method according to an exemplary embodiment;
FIG. 9 is a schematic diagram of a device made by a device manufacturing method according to an exemplary embodiment;
FIG. 10 is a schematic diagram of a device made by a device manufacturing method according to an exemplary embodiment;
FIG. 11 is a schematic diagram of equivalent capacitance of a circuit in which a device is located, according to an example embodiment;
fig. 12 is a schematic time delay diagram illustrating a circuit in which a device is located, according to an example embodiment.
Description of the reference numerals
1. A target area; 2. an air gap; 3. a target location; 4. a gate; 5. a source electrode; 6. a drain electrode;
7. a power supply line; 8. a sacrificial layer; 41. a dummy gate; 51. a source epitaxial growth region; 52. a source region;
61. a drain epitaxial growth region; 62. a drain region.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus consistent with some aspects of the disclosure as detailed in the accompanying claims.
The embodiments of the present disclosure take a gate-all-around (GateAllAround, GAA) transistor as an example, and other suitable device architectures include: fin transistors (finfets), planar transistors, and the like.
As shown in fig. 1, an embodiment of the present disclosure provides a device manufacturing method, the method including:
s110: forming an air gap 2 on the wafer at the target area 1; the target area 1 includes: a region between the target location 3 and the gate 4; the target position 3 is a position where the source 5 contacts the power supply circuit.
The target region 1 may be located between a source epitaxial growth region 51 corresponding to the source 5 and a drain epitaxial growth region 61 corresponding to the drain 6.
In the related art, as shown in fig. 2, there is a large parasitic capacitance in the region between the gate electrode 4 and the power supply line 7 in the power supply circuit, and there is a parasitic channel between the source and drain based on the region, resulting in high leakage in the off state.
In the disclosed embodiments, the power supply circuit may be a back-side power supply network of the wafer. The target location 3 may be a location where the source 5 is connected to a power supply circuit, for example, the source 5 and the power supply circuit may make metal contact at the target location 3 to access the power supply circuit, or the like.
In one embodiment, the target area 1 is an area between the target position 3 and the gate electrode 4, wherein the target area 1 may be an area of a predetermined range near the target position 3 and the gate electrode 4, or the like. For example, the connection between the gate 4 and the target location 3 may pass through the target area 1.
As illustrated in fig. 3, the target region 1 may be located between a source epitaxial growth region 51 corresponding to the source 5 and a drain epitaxial growth region 61 corresponding to the drain 6, for example, between a source region filled sacrificial layer 8 and a drain region filled sacrificial layer 8. Parasitic capacitance between the gate electrode 4 and the power supply line 7 of the target location 3, and parasitic channel between the source and drain electrodes, are generated in the target region 1. An air gap 2 is thus provided in the target area 1 to reduce parasitic capacitance and parasitic channels.
In one embodiment, step S110 may include: after the thinning process is performed on the back of the wafer, an air gap 2 is formed at the target area 1. For example, after the thinning process, the surface of the sacrificial layer 8 where the sacrificial layer material is located is exposed, and then the air gap 2 located in the target area 1 is formed thereon.
In one embodiment, the air gap 2 is formed, and the air gap 2 may be formed by filling an insulating material after forming the trench by etching. For example, the air gap 2 may be formed by filling the trench with an insulating material after the trench is formed, and not filling the trench, so that the insulating material and the trench may form a closed or semi-closed air gap 2.
Therefore, the insulation between the grid electrode 4 and the power supply circuit can be improved through the air gap 2, so that parasitic capacitance between the grid electrode 4 and a power supply line of the power supply circuit and the like is reduced, a parasitic channel between a source electrode and a drain electrode can be reduced, the whole parasitic effect of the transistor is reduced, and the performance of the transistor and the circuit is improved.
In some embodiments, as shown in fig. 4, step S110 may include:
s111: forming a groove in a target area on the back surface of the wafer through selective etching treatment;
s112: an air gap is formed by filling an insulating material in the trench.
In the embodiment of the present disclosure, the selective etching may be selective etching of the target area 1, for example, etching a part or all of the target area 1 to form a trench, or the like.
In one embodiment, the dimensions of the trench, such as cross-sectional area or depth, may be determined based on the dimensions of the wafer or the manufacturing requirements of the device. Accordingly, the filling thickness or filling area of the filling insulating material, etc. may also be determined according to the size of the trench or the size of the air gap 2 to be formed.
In one embodiment, the trench is filled with insulating material and not filled, e.g., an air gap 2 is left between the filled insulating material and the trench bottom. Wherein the air gap 2 may be closed or semi-closed or not.
Thus, the grooves are etched on the back of the wafer and the air gap 2 is formed, so that the front of the wafer is prevented from being damaged, and the air gap manufacturing process is better performed.
In some embodiments, after forming the air gap 2, e.g., after step S110 or step S112, the method may further comprise:
the source 5 is in contact with the supply circuit at the target location 3.
In one embodiment, after the formation of the air gap 2 in the target area 3, the connection of the source 5 to the supply circuit can be done at the target location 3 by contacting the source 5 to the supply circuit, thereby switching the transistor into the supply circuit.
In one embodiment, contacting the source 5 with the power supply circuit at the target location 3 may include contacting the source 5 with the power supply circuit at the target location 3. For example, the source 5 is brought into contact with a predetermined metal point at the target position 3, the predetermined metal point being used for connection with a power supply circuit.
In some embodiments, the method may further comprise:
and carrying out a manufacturing process of the power supply circuit.
In one embodiment, the power supply circuit is fabricated before the source 5 is brought into contact with the power supply circuit at the target location 3. After the power supply circuit manufacturing process is completed, the source electrode 5 is connected with the power supply circuit at the target position 3.
In one embodiment, the power supply circuit is fabricated after the source 5 is brought into contact with the power supply circuit at the target location 3. For example, after the source 5 is brought into contact with a predetermined metal point at the target position 3, a process for manufacturing a power supply circuit is performed. The manufacturing process of the power supply circuit may include a manufacturing process of the power supply circuit based on a predetermined metal point, for example, the manufacturing process is to start manufacturing from the predetermined metal point or to manufacture around the predetermined metal point, etc. The predetermined metal points may be connected to a power supply circuit.
In some embodiments, said contacting the source 5 with the power supply circuit at the target location 3 comprises:
and punching holes in the target position 3 through photoetching, and enabling the source electrode 5 to be in contact with the power supply circuit.
In the embodiment of the disclosure, the photoresist may be covered on the area except the target position 3 through lithography punching, and the target position 3 may be punched through lithography. For example, the photoresist is covered in the source region or in the source epitaxial growth region 51 or in a region other than the target position in the sacrificial layer 8 corresponding to the source region.
In one embodiment, the source 5 is in contact with the power supply circuit, which may include making metal contact with the power supply circuit through a metal dot, a metal post, a metal sheet, or the like corresponding to the hole after punching the target position 3.
In some embodiments, as shown in fig. 5, before the step S111, the method may further include:
s101: bonding the front surface of the wafer with the carrier sheet;
s102: and turning over the wafer, and thinning the back of the wafer.
In the disclosed embodiment, the bonding and thinning processes may be performed before the air gap 2 located in the target region 1 is formed on the wafer. The wafer and carrier bonding may be bonding the front surface of the wafer and the carrier after the standard process is completed, and the standard process may include at least one of a front-end process, a middle-end process, and a back-end process.
Wherein the front-end process may comprise: source, drain, and gate formation. The midsection process may include: and adding a process for replacing the metal gate, a local interconnection process and the like after the source and drain electrode forming operation. The back-end process may include: dielectric deposition between interconnection lines, metal line formation, lead-out bonding pads and the like.
In one embodiment, the step S101 is to process the front surface of the wafer, and the steps S102, S111 and S112 are to process the back surface of the wafer, so after the front surface of the wafer is processed upwards, the wafer may be turned over so that the back surface of the wafer faces upwards, thereby facilitating the thinning process and the trench etching process of the back surface of the wafer.
In one embodiment, the thinning of the back side of the wafer may be performed until the sacrificial layer material of the sacrificial layer 8 is exposed, where the sacrificial layer material may be filled in the source and/or drain regions to form the sacrificial layer 8 prior to the front-end-of-line process of the wafer.
In one embodiment, prior to step S101, the method may further comprise:
filling the source region 52 and the drain region 62 with a sacrificial layer material;
performing epitaxial growth of a source electrode and/or a drain electrode based on the position of the sacrificial layer material;
and performing a front-end process, a middle-end process and a back-end process on the wafer.
In the embodiment of the present disclosure, the target region 1 may be a first region between a sacrificial layer material filling position corresponding to the source region 52 and a sacrificial layer material filling position corresponding to the drain region, and the air gap 2 may be formed in the first region. Wherein the sacrificial layer material filling locations may be locations of the sacrificial layer 8.
In one embodiment, the sacrificial layer material may be a silicon germanium material (SiGe) or other insulating material.
In one embodiment, as shown in fig. 6, the sacrificial layer 8 is formed by filling the source region 52 and the drain region 62 with a sacrificial layer material. Wherein the front-end process may comprise: source, drain, and gate forming operations. For the source and drain forming operation, the source and drain forming operation may be performed for a region epitaxially grown on the source and drain.
In one embodiment, as shown in fig. 7, the source epitaxial growth may be performed based on the sacrificial layer 8 formed of the sacrificial layer material to obtain the source epitaxial growth region 51, and the drain epitaxial growth may be performed to obtain the drain epitaxial growth region 61.
In one embodiment, the thinning the back surface of the wafer includes:
and thinning the back surface of the wafer until the sacrificial layer material is exposed.
In one embodiment, the exposed sacrificial layer material may be a plane in which the exposed sacrificial layer material resides.
In one embodiment, the front-end process includes at least: source, drain, and gate forming operations.
The source 5 forming operation may be source 5 metal forming, the drain 6 forming operation may be drain 6 metal forming, and the gate 4 forming operation may be gate 4 metal forming. The gate 4 forming operation may be to perform the gate 4 forming operation in the dummy gate region.
In one embodiment, as shown in fig. 8, a gate 4 forming operation may be performed in the dummy gate 41 region, and a source and drain forming operation may be performed based on the source and drain epitaxial growth regions.
In some embodiments, the method further comprises, prior to filling the source region and the drain region with the sacrificial layer material:
performing epitaxial growth of the substrate on the wafer; the substrate comprises: a nanosheet;
dummy gate 41 and spatial layer fabrication and source and drain etching are performed in the epitaxially grown regions of the substrate to yield source region 52 and drain region 62.
In the embodiment of the disclosure, the source and drain etching may be performed by dry etching.
In one embodiment, the region of substrate epitaxial growth is shown in fig. 9, and the substrate epitaxial growth may comprise substrate multilayer stack epitaxial growth. As shown in fig. 10, the source region 52 and the drain region 62 can be obtained by etching.
Embodiments of the present disclosure provide a transistor device manufactured by the device manufacturing method according to one or more of the foregoing technical solutions.
In the embodiments of the present disclosure, the device manufacturing method may be applied to a Gate-All-Around (GAA) device, for example. The transistor device may be a gate-all-around nanoflake device such as a GAA device.
In one embodiment, as shown in fig. 11, the equivalent capacitance of the circuit where the device is located is compared under the conditions of no air gap, a part of air gap, and an all-air gap, where the part of air gap may be the air gap in one or more of the above-mentioned technical schemes for only part of the transistor devices in the circuit, and the all-air gap may be the air gap in one or more of the above-mentioned technical schemes for all of the transistor devices in the circuit. Therefore, the parasitic capacitance of the transistor device can be weakened to different degrees under the condition of full filling or partial filling by the air gap, so that the equivalent capacitance of a circuit is reduced, and the circuit performance can be improved based on different requirements.
In one embodiment, as shown in fig. 12, there is no air gap, a part of the air gap may be the air gap in one or more of the foregoing technical schemes for only a part of the transistor devices in the circuit, and a time delay comparison of the circuit in which the devices are located under the full air gap may be the air gap in one or more of the foregoing technical schemes for all of the transistor devices in the circuit. Therefore, the air gap can reduce the working time delay of the circuit where the transistor device is located to different degrees under the condition of full filling or partial filling, and therefore the circuit performance can be improved based on different requirements.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (10)

1. A device manufacturing method, the method comprising:
forming an air gap in a target area on a wafer; the target area includes: a region between the target location and the gate; the target position is a position where the source electrode contacts the power supply circuit.
2. The method of claim 1, wherein forming an air gap in the target area on the wafer comprises:
forming a groove in a target area on the back surface of the wafer through selective etching treatment;
an air gap is formed by filling an insulating material in the trench.
3. The method according to claim 1, wherein the method further comprises:
the source is brought into contact with the power supply circuit at the target location.
4. A method according to claim 3, wherein said contacting the source with the power supply circuit at the target location comprises:
and punching holes in the target position through photoetching, and enabling the source electrode to be in contact with the power supply circuit.
5. The method of claim 2, wherein the method further comprises, prior to forming the trench in the target region of the wafer backside by the selective etching process:
bonding the front surface of the wafer with the carrier sheet;
and turning over the wafer, and thinning the back of the wafer.
6. The method of claim 5, wherein prior to bonding the wafer front side to the carrier, the method further comprises:
filling a sacrificial layer material in the source electrode region and the drain electrode region;
performing epitaxial growth of a source electrode and/or a drain electrode based on the position of the sacrificial layer material;
and performing a front-end process, a middle-end process and a back-end process on the wafer.
7. The method of claim 6, wherein the thinning the wafer backside comprises:
and thinning the back surface of the wafer until the sacrificial layer material is exposed.
8. The method according to claim 6, wherein the front-end process comprises at least: source, drain, and gate forming operations.
9. The method of claim 6, wherein prior to filling the source region and the drain region with the sacrificial layer material, the method further comprises:
performing epitaxial growth of the substrate on the wafer; the substrate comprises: a nanosheet;
and manufacturing a pseudo gate and a space layer in the epitaxial growth area of the substrate, and etching a source electrode and a drain electrode to obtain a source electrode area and a drain electrode area.
10. A transistor device, characterized in that the transistor device is manufactured by the device manufacturing method according to any one of claims 1 to 9.
CN202310644602.XA 2023-06-01 2023-06-01 Device manufacturing method and transistor device Pending CN116759438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310644602.XA CN116759438A (en) 2023-06-01 2023-06-01 Device manufacturing method and transistor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310644602.XA CN116759438A (en) 2023-06-01 2023-06-01 Device manufacturing method and transistor device

Publications (1)

Publication Number Publication Date
CN116759438A true CN116759438A (en) 2023-09-15

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CN202310644602.XA Pending CN116759438A (en) 2023-06-01 2023-06-01 Device manufacturing method and transistor device

Country Status (1)

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