CN116741240A - FPGA configuration memory and FPGA chip - Google Patents

FPGA configuration memory and FPGA chip Download PDF

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Publication number
CN116741240A
CN116741240A CN202310704570.8A CN202310704570A CN116741240A CN 116741240 A CN116741240 A CN 116741240A CN 202310704570 A CN202310704570 A CN 202310704570A CN 116741240 A CN116741240 A CN 116741240A
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CN
China
Prior art keywords
tube
pull
electrically connected
electrode
configuration memory
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Pending
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CN202310704570.8A
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Chinese (zh)
Inventor
杨献
薛庆华
王海力
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Jingwei Qili Beijing Technology Co ltd
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Jingwei Qili Beijing Technology Co ltd
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Priority to CN202310704570.8A priority Critical patent/CN116741240A/en
Publication of CN116741240A publication Critical patent/CN116741240A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An FPGA memory and an FPGA chip. The FPGA configuration memory comprises a first modification unit; the first modification unit is formed based on modification of the first storage unit; the source electrode, the drain electrode and the grid electrode of the first pull-up tube are electrically connected with the working power supply end, and the source electrode, the drain electrode and the grid electrode of the second pull-up tube are electrically connected with the working power supply end; the grid electrode of the first pull-down tube is electrically connected with the working power supply end, and the source electrode and the drain electrode of the first pull-down tube are electrically connected with the working ground end; the grid electrode of the second pull-down tube is electrically connected with the working power supply end, and the source electrode and the drain electrode of the second pull-down tube are electrically connected with the working ground end; the grid electrode of the first transmission tube is electrically connected with the word line, and the source electrode and the drain electrode of the first transmission tube are electrically connected with the working ground end; the grid electrode of the second transmission tube is electrically connected with the word line, and the source electrode and the drain electrode of the second transmission tube are electrically connected with the working ground.

Description

FPGA configuration memory and FPGA chip
Technical Field
The present application relates to the field of integrated circuits, and in particular, to an FPGA configuration memory and an FPGA chip.
Background
The current Field programmable gate array (Field-Programmable Gate Array, FPGA) chip is mainly completed by 6 parts, which are respectively: programmable input-output units, basic programmable logic units, complete clock management, embedded block random access memory (Random Access Memory, RAM), rich wiring resources, embedded underlying functional units, and embedded dedicated hardware modules. Often, embedded block RAM includes a large amount of configuration memory that may be used to store configuration files, which may include FPGA instructions in particular.
The number of the memory cells in each column in the configuration memory is the same, but in practical application, a part of the memory cells in the configuration memory are in idle state and are not used for storing data, and the memory cells are only manufactured to avoid generating blank in the FPGA configuration memory, so that the yield of manufacturing the FPGA configuration memory can be prevented from being influenced. However, these memory cells are connected to the working power source terminal and the working ground terminal, and static power consumption is constantly generated.
Therefore, how to reduce the static power consumption of the FPGA configuration memory can be a technical problem to be solved in the field.
Disclosure of Invention
In order to solve the above-mentioned problems, an embodiment of the present application provides an FPGA configuration memory, which includes a first modification unit; the first modification unit is formed based on modification of a first storage unit, and the first storage unit comprises a first transmission pipe, a second transmission pipe, a first pull-up pipe, a second pull-up pipe, a first pull-down pipe and a second pull-down pipe; the first storage unit is not used for storing data in the FPGA configuration memory; the FPGA configuration memory further comprises a second storage unit; the second storage unit is used for storing data; the source electrode, the drain electrode and the grid electrode of the first pull-up tube are electrically connected with a working power supply end, and the source electrode, the drain electrode and the grid electrode of the second pull-up tube are electrically connected with the working power supply end; the grid electrode of the first pull-down tube is electrically connected with the working power supply end, and the source electrode and the drain electrode of the first pull-down tube are electrically connected with the working ground end; the grid electrode of the second pull-down tube is electrically connected with the working power supply end, and the source electrode and the drain electrode of the second pull-down tube are electrically connected with the working ground end; the grid electrode of the first transmission tube is electrically connected with the word line, and the source electrode and the drain electrode of the first transmission tube are electrically connected with the working ground terminal; the grid electrode of the second transmission tube is electrically connected with the word line, and the source electrode and the drain electrode of the second transmission tube are electrically connected with the working ground terminal. According to the application, through changing the circuit connection relation of the first transmission tube, the second transmission tube, the first pull-up tube, the second pull-up tube, the first pull-down tube and the second pull-down tube in the first storage unit, the static leakage current flowing through the circuit connection relation can be reduced, and the static power consumption of the FPGA configuration memory can be further reduced.
For this purpose, the following technical scheme is adopted in the embodiment of the application:
in a first aspect, the present application provides an FPGA configuration memory, the FPGA configuration memory comprising a first modification unit; the first modification unit is formed based on modification of a first storage unit, and the first storage unit comprises a first transmission pipe, a second transmission pipe, a first pull-up pipe, a second pull-up pipe, a first pull-down pipe and a second pull-down pipe; the first storage unit is not used for storing data in the FPGA configuration memory; the FPGA configuration memory further comprises a second storage unit; the second storage unit is used for storing data; the source electrode, the drain electrode and the grid electrode of the first pull-up tube are electrically connected with a working power supply end, and the source electrode, the drain electrode and the grid electrode of the second pull-up tube are electrically connected with the working power supply end; the grid electrode of the first pull-down tube is electrically connected with the working power supply end, and the source electrode and the drain electrode of the first pull-down tube are electrically connected with the working ground end; the grid electrode of the second pull-down tube is electrically connected with the working power supply end, and the source electrode and the drain electrode of the second pull-down tube are electrically connected with the working ground end; the grid electrode of the first transmission tube is electrically connected with the word line, and the source electrode and the drain electrode of the first transmission tube are electrically connected with the working ground terminal; the grid electrode of the second transmission tube is electrically connected with the word line, and the source electrode and the drain electrode of the second transmission tube are electrically connected with the working ground terminal.
In this embodiment, the source, the drain and the gate of the first pull-up tube are all electrically connected to the working power supply terminal, so that the first pull-up tube does not affect the circuit functions of other parts, and is not used for implementing any circuit function, and the first pull-up tube becomes a virtual MOS tube, does not flow through static leakage current, and does not generate static power consumption. The second pull-up tube is also the same and will not be described in detail herein. Similarly, the grid electrode of the first pull-down tube is electrically connected with the working power supply end, and the source electrode and the drain electrode of the first pull-down tube are electrically connected with the working ground end, so that the first pull-down tube becomes a decoupling capacitor, static leakage current can be reduced, and voltage stabilization effect is achieved in the circuit. The second pull-down pipe is also the same and will not be described in detail herein. In addition, the grid electrode of the first transmission tube is electrically connected with the word line, and the source electrode and the drain electrode of the first transmission tube are electrically connected with the working ground, so that the static leakage current of the first transmission tube can be reduced, and the static power consumption of the FPGA configuration memory can be further reduced. The same is true of the second transfer tube, and will not be described in detail herein.
By the mode, the static leakage current of the first transmission tube, the second transmission tube, the first pull-up tube, the second pull-up tube, the first pull-down tube and the second pull-down tube can be reduced, and therefore the static power consumption of the FPGA configuration memory can be reduced.
In one embodiment, when the level of the word line is high, the gate level of the first transfer tube is high, the source and drain levels of the first transfer tube are low, and the first transfer tube becomes a decoupling capacitor.
In this embodiment, the gate level of the first transmission tube is high, and the source level and the drain level of the first transmission tube are low, so that the first transmission tube becomes a decoupling capacitor, thereby reducing the static leakage current flowing through the first transmission tube and stabilizing the voltage in the circuit.
In one embodiment, when the level of the word line is high, the gate level of the second transfer tube is high, the source and drain levels of the second transfer tube are low, and the second transfer tube becomes a decoupling capacitor.
In this embodiment, the gate level of the second transmission tube is high, and the source level and the drain level of the second transmission tube are low, so that the second transmission tube becomes a decoupling capacitor, thereby reducing static leakage current flowing through the second transmission tube and stabilizing voltage in the circuit.
In one embodiment, when the level of the word line is low, the gate level, the source level, and the drain level of the first transfer transistor are low, and the first transfer transistor is a dummy MOS transistor.
In this embodiment, the gate level, the source level, and the drain level of the first transfer tube are on average low, and thus static leakage current does not flow in the first transfer tube, so that static power consumption of the first transfer tube can be reduced.
In one embodiment, when the level of the word line is low, the gate level, the source level, and the drain level of the second transfer transistor are low, and the second transfer transistor is a dummy MOS transistor.
In this embodiment, the gate level, the source level, and the drain level of the second transfer tube are on average low, and thus static leakage current does not flow in the second transfer tube, so that static power consumption of the second transfer tube can be reduced.
In another embodiment, the first pull-up tube and the second pull-up tube are PMOS field effect tubes, and the first transmission tube, the second transmission tube, the first pull-down tube and the second pull-down tube are NMOS field effect tubes.
In a second aspect, an embodiment of the present application provides an FPGA chip, where the FPGA chip includes any one of the FPGA configuration memories described above.
In this embodiment, the FPGA chip includes any of the FPGA configuration memories described above, so that the static power consumption of the FPGA configuration memory can be reduced, and thus the static power consumption of the FPGA chip can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of a memory cell in an FPGA configuration memory;
fig. 2 is a circuit diagram of a modification unit in an FPGA configuration memory according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an FPGA chip according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
The term "and/or" is used herein to describe an association relationship of associated objects, and means that there may be three relationships, for example, a and/or B, and that there may be three cases where a exists alone, while a and B exist together, and B exists alone. The symbol "/" herein indicates a relationship in which the associated object is "or", e.g., a/B indicates a or B.
The terms "first" and "second" and the like in the description and in the claims are used for distinguishing between different objects and not for describing a particular sequential order of objects. For example, the first response message and the second response message, etc. are used to distinguish between different response messages, and are not used to describe a particular order of response messages.
In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration.
Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the description of the embodiments of the present application, unless otherwise specified, the meaning of "plurality" means two or more, for example, the meaning of a plurality of processing units means two or more, or the like; the plurality of elements means two or more elements and the like.
FPGA is a field programmable gate array, which is a product of further development based on programmable devices such as programmable array logic (Programming Array Logic, PAL), general-purpose array logic (Generic Array Logic, GAL), complex programmable logic devices (Complex Programmable Logic Device, CPLD), etc. The programmable device is used as a semi-custom circuit in the field of application specific integrated circuits, not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable device. The FPGA can select to build a storage module, or can select the FPGA with an internal storage block.
The FPGA chip is mainly completed by 6 parts, which are respectively: the system comprises a programmable input-output unit, a basic programmable logic unit, a complete clock management unit, an embedded block RAM, rich wiring resources, an embedded bottom layer functional unit and an embedded special hardware module. The FPGA configuration memory is located in embedded block RAM, typically static RAM. FPGA configuration memory typically includes a plurality of memory cells.
Each memory cell consists of a bistable structure of 2 inverters and two switches (the switches may be implemented by transfer tubes), using a total of 6 transistors, transistors M0 to M5, respectively, as shown in fig. 1. The level of the Word Line (WL) is used to control the transfer tube to be in on or off state, and only when the transfer tube is in on state, the read operation or the write operation can be performed; the two Bit lines are Bit Line (BL) and Bit Line inversion (BLB) respectively, so that a balance circuit is realized and the effect of the balance circuit is more stable.
For the read operation process, assuming that the current stored data is 0, the read process is to perform pre-charge, turn on the switch, select the word line, generate current, BL flow current, voltage decrease, BLB flow current, voltage increase, at this time the bit line is no longer balanced, the sense amplifier captures the left bit line low, the right bit line high, indicating that 0 is stored.
In the configuration memory of the FPGA chip, the number of memory cells in each column is the same, but in actual use, the memory cells in some columns are in an idle state and are not used for performing a memory function. The configuration memory in the FPGA chip comprises, for example, 20 columns of memory cells, each column comprising 100 memory cells, only 60 of the 100 memory cells in the first column are actually used effectively, the remaining 40 memory cells are in an idle state and do not exert a memory effect, and all of the memory cells in the other 19 columns are used to exert a memory effect. For 40 memory cells in idle state, the idle memory cells can flow static leakage current due to the connection of the working power supply terminal and the working ground terminal, so that the static power consumption of the configuration memory is improved.
In order to solve the technical problem of how to reduce the static power consumption of the FPGA configuration memory, the application provides a solution. An FPGA configuration memory comprising a first modification unit; the first modification unit is formed based on modification of a first storage unit, and the first storage unit comprises a first transmission pipe, a second transmission pipe, a first pull-up pipe, a second pull-up pipe, a first pull-down pipe and a second pull-down pipe; the first storage unit is not used for storing data in the FPGA configuration memory; the source electrode, the drain electrode and the grid electrode of the first pull-up tube are electrically connected with a working power supply end, and the source electrode, the drain electrode and the grid electrode of the second pull-up tube are electrically connected with the working power supply end; the grid electrode of the first pull-down tube is electrically connected with the working power supply end, and the source electrode and the drain electrode of the first pull-down tube are electrically connected with the working ground end; the grid electrode of the second pull-down tube is electrically connected with the working power supply end, and the source electrode and the drain electrode of the second pull-down tube are electrically connected with the working ground end; the grid electrode of the first transmission tube is electrically connected with the word line, and the source electrode and the drain electrode of the first transmission tube are electrically connected with the working ground terminal; the grid electrode of the second transmission tube is electrically connected with the word line, and the source electrode and the drain electrode of the second transmission tube are electrically connected with the working ground terminal.
In the embodiment of the application, the static leakage current of the first transmission tube, the second transmission tube, the first pull-up tube, the second pull-up tube, the first pull-down tube and the second pull-down tube can be reduced by changing the circuit connection relation in the first storage unit, so that the static power consumption of the FPGA configuration memory can be reduced.
Fig. 2 is a circuit diagram of a modification unit in an FPGA configuration memory according to an embodiment of the present application. The embodiment of the application provides an FPGA configuration memory, which comprises a first modification unit; the first modification unit is formed based on a modification to a first storage unit that is not used to store data in the FPGA configuration memory. Because the first storage unit is not used for storing data in the FPGA configuration memory, the first storage unit can be subjected to circuit modification, so long as the modification mode does not influence the functions of other parts of the circuit. The FPGA configuration memory may further include a second storage unit, where the second storage unit is used to store data and is not in an idle state, and the embodiment of the present application does not make any modification to the second storage unit, and the structure of the second storage unit is shown in fig. 1.
The first memory unit may include a first transmission tube M0, a second transmission tube M1, a first pull-up tube M2, a second pull-up tube M3, a first pull-down tube M4, and a second pull-up tube M5, which are 6 field effect tubes in total.
The structure of the first modification unit is shown in fig. 2, and the source, the drain and the gate of the first pull-up tube M2 are all electrically connected to the power supply terminal VCC, so that the first pull-up tube M2 does not affect the circuit functions of other parts, and is not used for implementing any circuit function, so that the first pull-up tube M2 becomes a dummy MOS tube (dummy cell). Since the source, the drain and the gate of the first pull-up tube M2 are all electrically connected to the power supply terminal VCC, no static leakage current flows through the first pull-up tube M2, and no static power consumption is generated. Similarly, the source, the drain and the gate of the second pull-up tube M3 are electrically connected to the power supply VCC, so that the second pull-up tube M3 does not affect the circuit functions of other portions, and is not used for implementing any circuit function, and therefore the second pull-up tube M3 becomes a dummy MOS tube. Since the source, the drain and the gate of the second pull-up tube M3 are electrically connected to the power supply terminal VCC, no static leakage current flows through the second pull-up tube M3, and no static power consumption is generated.
Similarly, the gate of the first pull-down tube M4 is electrically connected to the working power supply terminal VCC, and the source and the drain of the first pull-down tube M4 are electrically connected to the working ground terminal VSS, so that the first pull-down tube M4 becomes a decoupling capacitor, thereby reducing static leakage current and stabilizing voltage in the circuit. Meanwhile, the capacitance of the decoupling capacitor is substantially the same as the capacitance of the gate capacitor of the first pull-down tube M4, so that the load is less affected by the modification. Similarly, the gate of the second pull-up tube M5 is electrically connected to the working power supply terminal VCC, and the source and the drain of the second pull-up tube M5 are electrically connected to the working ground terminal VSS, so that the second pull-up tube M5 becomes a decoupling capacitor, thereby reducing static leakage current and performing voltage stabilizing function in the circuit.
In addition, the grid electrode of the first transmission tube M0 is electrically connected with the word line WL, and the source electrode and the drain electrode of the first transmission tube M0 are electrically connected with the working ground end VSS, so that the static leakage current of the first transmission tube M0 can be reduced, and the static power consumption of the FPGA configuration memory can be further reduced. Similarly, by electrically connecting the gate of the second transmission tube M1 with the word line WL, the source and the drain of the second transmission tube M1 are electrically connected with the working ground VSS, so that the static leakage current of the second transmission tube M1 can be reduced, and the static power consumption of the FPGA configuration memory can be further reduced.
Through the above manner, the static leakage current of the first transmission tube M0, the second transmission tube M1, the first pull-up tube M2, the second pull-up tube M3, the first pull-down tube M4 and the second pull-up tube M5 can be reduced, so that the static power consumption of the FPGA configuration memory can be reduced. In addition, in the chip design process, the modification mode in the embodiment of the application is adopted, so that the base layer and the size of the chip are not required to be changed, and the design workload is reduced. Meanwhile, in the chip manufacturing process, no gap is generated, so that the yield of the chip can be ensured. In one embodiment, to perform a read operation or a write operation on a memory cell, the memory cell may be controlled to be in a read state or a write state, and, for example, the level of the word line WL may be set to a high level. At this time, the gate level of the first transmission tube M0 is high, and the source level and the drain level of the first transmission tube M0 are low, so that the first transmission tube M0 becomes a decoupling capacitor, thereby reducing the static leakage current flowing through the first transmission tube M0 and stabilizing the voltage in the circuit.
Similarly, when the level of the word line WL is high, the gate level of the second transmission tube M1 is high, and the source level and the drain level of the second transmission tube M1 are low, so that the second transmission tube M1 becomes a decoupling capacitor, thereby reducing the static leakage current flowing through the second transmission tube M1 and stabilizing the voltage in the circuit.
In one embodiment, when the level of the word line WL is low, the gate level, the source level and the drain level of the first transmission tube M0 are low, so that the first transmission tube M0 does not affect the functions of other parts of the circuit, and is not used for implementing any circuit function, and no static power consumption is generated, so that the first transmission tube M0 becomes a virtual MOS tube. Similarly, when the level of the word line WL is low, the gate level, the source level and the drain level of the second transmission tube M1 are low, so that the second transmission tube M1 does not affect the functions of other parts of the circuit, and is not used for implementing any circuit function, and no static power consumption is generated, so that the second transmission tube M1 becomes a virtual MOS tube.
In one embodiment, the first pull-up tube M2 and the second pull-up tube M3 may be positive channel metal oxide semiconductor (Positive channel Metal Oxide Semiconductor, PMOS) field effect transistors, and the first transmission tube M0, the second transmission tube M1, the first pull-down tube M4, and the second pull-up tube M5 may be negative channel metal oxide semiconductor (Negative channel Metal Oxide Semiconductor, NMOS) field effect transistors, for example.
In the embodiment of the present application, an FPGA chip is further provided, and fig. 3 is a schematic structural diagram of the FPGA chip provided in the embodiment of the present application, where the FPGA chip 1 includes any of the FPGA configuration memories 11, so that static power consumption of the FPGA configuration memory 11 may be reduced, and further static power consumption of the FPGA chip 1 may be reduced. In addition, in the chip design process, the layout of the first storage unit in the FPGA configuration memory 11 is modified in the modification mode, and the basic layer and the size of the FPGA chip are not required to be additionally modified, so that the workload of chip design is reduced, and meanwhile, the chip design is used for not generating a gap in the chip, and therefore, the yield of the chip can be ensured in the chip manufacturing process.
Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
The foregoing embodiments have been provided for the purpose of illustrating the general principles of the present application in further detail, and are not to be construed as limiting the scope of the application, but are merely intended to cover any modifications, equivalents, improvements, etc. based on the teachings of the application.

Claims (7)

1. An FPGA configuration memory, characterized in that the FPGA configuration memory comprises a first modification unit; the first modification unit is formed based on modification of a first storage unit, and the first storage unit comprises a first transmission pipe, a second transmission pipe, a first pull-up pipe, a second pull-up pipe, a first pull-down pipe and a second pull-down pipe; the first storage unit is not used for storing data in the FPGA configuration memory; the FPGA configuration memory further comprises a second storage unit; the second storage unit is used for storing data;
the source electrode, the drain electrode and the grid electrode of the first pull-up tube are electrically connected with a working power supply end, and the source electrode, the drain electrode and the grid electrode of the second pull-up tube are electrically connected with the working power supply end;
the grid electrode of the first pull-down tube is electrically connected with the working power supply end, and the source electrode and the drain electrode of the first pull-down tube are electrically connected with the working ground end; the grid electrode of the second pull-down tube is electrically connected with the working power supply end, and the source electrode and the drain electrode of the second pull-down tube are electrically connected with the working ground end;
the grid electrode of the first transmission tube is electrically connected with the word line, and the source electrode and the drain electrode of the first transmission tube are electrically connected with the working ground terminal; the grid electrode of the second transmission tube is electrically connected with the word line, and the source electrode and the drain electrode of the second transmission tube are electrically connected with the working ground terminal.
2. The FPGA configuration memory of claim 1, wherein when the level of the word line is high, the gate level of the first transfer tube is high, the source and drain levels of the first transfer tube are low, and the first transfer tube becomes a decoupling capacitor.
3. The FPGA configuration memory of claim 1, wherein when the level of the word line is high, the gate level of the second transfer tube is high, the source and drain levels of the second transfer tube are low, and the second transfer tube becomes a decoupling capacitor.
4. The FPGA configuration memory of claim 1, wherein when the level of the word line is low, the gate level, source level, and drain level of the first pass transistor are low on average, and the first pass transistor becomes a virtual MOS transistor.
5. The FPGA configuration memory of claim 1, wherein when the level of the word line is low, the gate level, source level, and drain level of the second pass transistor are low on average, and the second pass transistor becomes a virtual MOS transistor.
6. The FPGA configuration memory according to any one of claims 1 to 5, wherein the first pull-up tube and the second pull-up tube are PMOS field effect tubes, and the first transmission tube, the second transmission tube, the first pull-down tube, and the second pull-down tube are NMOS field effect tubes.
7. An FPGA chip characterized in that it comprises an FPGA configuration memory according to any of the preceding claims 1 to 6.
CN202310704570.8A 2023-06-14 2023-06-14 FPGA configuration memory and FPGA chip Pending CN116741240A (en)

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CN202310704570.8A CN116741240A (en) 2023-06-14 2023-06-14 FPGA configuration memory and FPGA chip

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CN202310704570.8A CN116741240A (en) 2023-06-14 2023-06-14 FPGA configuration memory and FPGA chip

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CN116741240A true CN116741240A (en) 2023-09-12

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