CN116737641A - Connection device, four-way server, and initialization method and device of four-way server - Google Patents

Connection device, four-way server, and initialization method and device of four-way server Download PDF

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Publication number
CN116737641A
CN116737641A CN202310764643.2A CN202310764643A CN116737641A CN 116737641 A CN116737641 A CN 116737641A CN 202310764643 A CN202310764643 A CN 202310764643A CN 116737641 A CN116737641 A CN 116737641A
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CN
China
Prior art keywords
bus interface
processor
way server
cpu
connecting device
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Pending
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CN202310764643.2A
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Chinese (zh)
Inventor
申明伟
佟小敏
赵佳旺
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Shanghai Hexin Digital Technology Co ltd
Hexin Technology Co ltd
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Shanghai Hexin Digital Technology Co ltd
Hexin Technology Co ltd
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Priority to CN202310764643.2A priority Critical patent/CN116737641A/en
Publication of CN116737641A publication Critical patent/CN116737641A/en
Pending legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application discloses a connecting device, a four-way server, an initializing method and device of the four-way server, electronic equipment and a computer readable storage medium, wherein the connecting device comprises the following components: the device comprises a connector, a redrive chip and three A-BUS interfaces; the first A-BUS interface is connected with the third A-BUS interface, the second A-BUS interface is respectively connected with the redrive chip and the connector, and the redrive chip is connected with the connector. According to the application, the two connecting devices capable of receiving and transmitting clock signals and data signals are additionally arranged, and the A-BUS buses of the two processors in the four-way server are connected in series through the two connecting devices, so that the interconnection communication bandwidth of the four-way server is increased, and the data access delay among the processors is reduced.

Description

Connection device, four-way server, and initialization method and device of four-way server
Technical Field
The present application relates to the field of server circuits, and in particular, to a connection device, a four-way server, and a method and apparatus for initializing a four-way server.
Background
With the development of computer technology, more and more processors can be supported by a single system. The servers may be divided into single-path servers, double-path servers, four-path servers, and multiple-path servers (8 paths and more) according to the number of processors. Each HX-C1000 processor in the core-closing server is provided with three groups of A-BUS interfaces, and the processors can be mutually interconnected through the A-BUS BUS to form a single-path, double-path and four-path server.
In actual use, different servers can be configured according to different requirements, and the situation that only one CPU is installed on a two-way server or only two processors are installed on a four-way server can be possibly caused. For example, in order to use the characteristics of multiple hard disks and multiple PCIe slots of a 4U 4-way server, only two processors may be installed for performing configuration reduction in the case of low demand for computing resources, so as to achieve the effect of reducing cost. However, when only two processors are installed in the four-way server, the topology of the A-BUS is designed according to the mode of 4 CPUs at the beginning of the design of the four-way server, and when only two CPUs are installed, the A-BUS resources of the processors cannot form full connection, the bandwidths of the processors cannot be fully used, and the communication bandwidth is insufficient.
Disclosure of Invention
The application provides a connecting device, a four-way server and a method and a device for initializing the four-way server, wherein the connecting device can be arranged in a CPU slot of the four-way server and can be connected with two processors of the four-way server in series, so that the bandwidth of the four-way server is increased, and the communication rate is improved.
A first aspect of an embodiment of the present application provides a connection device, including: the device comprises a connector, a redrive chip and three A-BUS interfaces;
the first A-BUS interface is connected with the third A-BUS interface, the second A-BUS interface is respectively connected with the redrive chip and the connector, and the redrive chip is connected with the connector; the connection mode comprises a data signal and a clock signal.
A second aspect of an embodiment of the present application provides a four-way server, including: two processors and two connecting means as described above;
the three A-BUS interfaces of the first processor are respectively connected with one A-BUS interface of the second processor and one A-BUS interface corresponding to the two connecting devices respectively, the other two A-BUS interfaces of the second processor are respectively connected with the other A-BUS interfaces corresponding to the two connecting devices respectively, the other A-BUS interfaces of the two connecting devices are connected in series, so that the two processors are connected in series, and the two connecting devices are connected in series.
In a possible implementation manner of the second aspect, the four-way server is provided with four CPU slots, a first processor is disposed in a first CPU slot, a first connection device is disposed in a second CPU slot, a second connection device is disposed in a third CPU slot, and a second processor is disposed in a fourth CPU slot;
the first A-BUS interface of the first processor is connected with the third A-BUS interface of the second processor, the second A-BUS interface of the first processor is connected with the second A-BUS interface of the second connecting device, and the third A-BUS interface of the first processor is connected with the first A-BUS interface of the first connecting device;
the second A-BUS interface of the second processor is connected with the second A-BUS interface of the first connecting device, and the first A-BUS interface of the second processor is connected with the third A-BUS interface of the second processor;
the third A-BUS interface of the first connecting device is connected with the first A-BUS interface of the second connecting device;
the second A-BUS interface of the first connecting device is connected with the second A-BUS interface of the second connecting device through a cable.
In a possible implementation manner of the second aspect, the four-way server is provided with four CPU slots, a first processor is disposed in a first CPU slot, a second processor is disposed in a second CPU slot, a first connection device is disposed in a third CPU slot, and a second connection device is disposed in a fourth CPU slot;
the first A-BUS interface of the first processor is connected with the third A-BUS interface of the second connecting device, the second A-BUS interface of the first processor is connected with the second A-BUS interface of the first connecting device, and the third A-BUS interface of the first processor is connected with the first A-BUS interface of the second processor;
the second A-BUS interface of the second processor is connected with the second A-BUS interface of the second connecting device, and the third A-BUS interface of the second processor is connected with the first A-BUS interface of the first connecting device;
the third A-BUS interface of the first connecting device is connected with the first A-BUS interface of the second connecting device;
the second A-BUS interface of the first connecting device is connected with the second A-BUS interface of the second connecting device through a cable.
In a possible implementation manner of the second aspect, the connection device includes: the device comprises a connector, a redrive chip and three A-BUS interfaces;
the first A-BUS interface is connected with the third A-BUS interface, the second A-BUS interface is respectively connected with the redrive chip and the connector, and the redrive chip is connected with the connector.
A third aspect of an embodiment of the present application provides a method for initializing a four-way server, where the method includes:
after the level detection signals of the CPU slots of the four-way server are obtained, determining the installation state of the CPU slots according to the level detection signals, wherein the installation type comprises an in-place state and a type state;
and sending a corresponding configuration file to the four-way server based on the installation state so that the four-way server can be initialized by adopting the configuration file.
In a possible implementation manner of the third aspect, the determining manner of the in-place state includes:
if the level detection signal is at a low level, determining that the in-place state is an installation processor or an installation connecting device;
and if the level detection signal is at a high level, determining that the bit state is that the processor is not installed or the connecting device is not installed.
In a possible implementation manner of the third aspect, the determining manner of the type state includes:
if the level detection signal is at a low level, determining that the type state is a CPU slot installation processor;
and if the level detection signal is at a high level, determining that the type state is a CPU slot installation connection device.
A fourth aspect of an embodiment of the present application provides an initializing device of a four-way server, where the device includes:
the system comprises a determining module, a judging module and a judging module, wherein the determining module is used for determining the installation state of a CPU slot according to the level detection signal after the level detection signal of the CPU slot of the four-way server is obtained, and the installation type comprises an in-place state and a type state;
and the initialization module is used for sending a corresponding configuration file to the four-way server based on the installation state so that the four-way server can be initialized by adopting the configuration file.
Compared with the prior art, the connecting device, the four-way server and the initializing method and device of the four-way server provided by the embodiment of the application have the beneficial effects that: according to the application, the connecting device capable of receiving and transmitting clock signals and data signals is additionally arranged, and the A-BUS buses of the two processors in the four-way server are connected in series through the two connecting devices, so that the interconnection communication bandwidth of the four-way server is increased, and the data access delay among the processors is reduced.
Drawings
FIG. 1 is a schematic diagram of the connection relationship between the interconnections of the connection device according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a four-way server A-BUS topology according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a topology of a four-way server with a present connection unit according to an embodiment of the present application;
FIG. 4 is a second topology diagram of a four-way server with a present connection unit according to an embodiment of the present application;
FIG. 5 is a flowchart illustrating an initialization method of a four-way server according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an initializing device of a four-way server according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In order to solve the above-mentioned problems, the following detailed description and descriptions will be given by the following specific embodiments of the present application, and a method and apparatus for initializing a four-way server.
Referring to fig. 1, a schematic structural diagram of a connection device according to an embodiment of the present application is shown.
Wherein, as an example, the connection device may include: the device comprises a connector, a redrive chip and three A-BUS interfaces;
the first A-BUS interface is connected with the third A-BUS interface, the second A-BUS interface is respectively connected with the redrive chip and the connector, and the redrive chip is connected with the connector; the connection mode of the redrive chip and the connector comprises data signal connection and clock signal connection.
In an embodiment, the connection device comprises: the device comprises a PCB, a connector, a redrive chip and three A-BUS interfaces;
the connector, the redrive chip and the three A-BUS interfaces are respectively arranged on the PCB.
In this embodiment, the connection device may use a PCB board as a main body, and the size and shape of the PCB board may be the same as those of the CPU board, so that the connection device is conveniently installed in the CPU SOCKET.
In an embodiment, the back surface of the PCB board may be a PAD (PAD) for connection with pins in the CPU SOCKET. And wiring is designed on the PCB board, so that three A-BUS interfaces are connected.
In an embodiment, the front side of the PCB board may be provided with devices such as a connector, a Re-driver chip (Re-driver), etc.
In an embodiment, in order to further fix the connection device on the CPU SOCKET, the connection device may be designed with a fixing device, and the connection of the device is ensured to be firm and the signal contact is normal by matching the fixing device with the fixing device on the CPU SOCKET.
In an embodiment, the three a-BUS interfaces of the connection device may be an A0 port, an A2 port, and an A1 port, respectively. Referring to fig. 1, the connection device has a connection relationship of an A0 port and an A2 port, and the A1 port is connected with the connector.
Since the A0 transmit port is connected to the A2 receive port, the A0 transmit clock is connected to the A2 clock receive port; the A2 transmit port is connected to the A0 receive port and the A2 transmit clock is connected to the A0 clock receive port.
The A1 transmitting port and the A1 transmitting end clock are connected to part of signals of the connector through the redrive chip, and the other part of signals of the connector are connected to the A1 receiving end and the A1 receiving end clock.
Referring to fig. 1, the in-place detection signal of the connection device is shorted to the ground, and the type detection signal is suspended.
In this embodiment, the embodiment of the present application provides a four-way server, which has the following beneficial effects: the connecting device can be arranged in the CPU slot of the four-way server, and can receive and send clock signals and data signals, and the A-BUS buses of the two processors in the four-way server are connected in series through the two connecting devices, so that the interconnection communication bandwidth of the four-way server is increased, and the data access delay among the processors is reduced.
Referring to FIG. 2, a schematic diagram of a four-way server A-BUS topology is shown, according to an embodiment of the present application.
Wherein, as an example, the four-way server may include: two processors and two connecting means as described in the above embodiments;
each processor and each connecting device are provided with three A-BUS interfaces, and each interface consists of a transmitting end, a transmitting end clock, a receiving end and a receiving end clock.
The three A-BUS interfaces of the first processor are respectively connected with one A-BUS interface of the second processor and one A-BUS interface corresponding to the two connecting devices respectively, the other two A-BUS interfaces of the second processor are respectively connected with the other A-BUS interfaces corresponding to the two connecting devices respectively, the other A-BUS interfaces of the two connecting devices are connected in series, so that the two processors are connected in series, and the two connecting devices are connected in series.
Taking fig. 2 as an example, four CPU slots (assuming that CPU0, CPU1, CPU2 and CPU3 are respectively) are provided in the four-way server, two processors and two connection devices may be respectively provided in the four CPU slots, and then three a-BUS interfaces of the first processor are respectively connected with one a-BUS interface of the second processor, one a-BUS interface of the first connection device and one a-BUS interface of the second connection device, the other two a-BUS interfaces of the second processor are connected with the other a-BUS interface of the first connection device and the other a-BUS interface of the second connection device, the remaining other a-BUS interfaces of the two connection devices are connected in series, the two processors are connected in series, and the two connection devices are connected in series.
It should be noted that, taking fig. 2 as an example, four CPU slots (CPU 0, CPU1, CPU2, and CPU3 respectively) may be all provided with a processor, so as to implement expansion of the four-core server.
The A-BUS buses of the two processors in the four-way server are interconnected through the two connecting devices, so that the bandwidth of the four-way server is increased, the communication rate is improved, and the data access delay is reduced.
Alternatively, if processors may be installed in all four CPU slots of a four-way server, the A-BUS BUS topology between the four processors may be as shown in FIG. 2 below. The signal processing is as follows:
1. the CPU0A 0 transmitting end is connected to the CPU3A 2 receiving end, and meanwhile, the CPU0A 0 transmitting end clock is connected to the CPU3A 2 receiving end clock; the CPU3A 2 transmitting end is connected to the CPU0A 0 receiving end, and the CPU3A 2 transmitting end clock is connected to the CPU0A 0 clock receiving end.
2. The CPU0A1 transmitting end is connected to the CPU 2A 1 receiving end, and meanwhile, the CPU0A1 transmitting end clock is connected to the CPU 2A 1 receiving end clock; the CPU 2A 1 transmitting end is connected to the CPU0A1 receiving end, and the CPU 2A 1 transmitting end clock is connected to the CPU0A1 clock receiving end.
3. The CPU0A2 transmitting end is connected to the CPU 1A 0 receiving end, and meanwhile, the CPU0A2 transmitting end clock is connected to the CPU 1A 0 receiving end clock; the CPU 1A 0 transmitting end is connected to the CPU0A2 receiving end, and the CPU 1A 0 transmitting end is connected to the CPU0A2 clock receiving end.
4. The CPU 1A 1 transmitting end is connected to the CPU3A 1 receiving end, and meanwhile, the CPU 1A 1 transmitting end clock is connected to the CPU3A 1 receiving end clock; the CPU3A 1 transmitting end is connected to the CPU 1A 1 receiving end, and the CPU3A 1 transmitting end clock is connected to the CPU 1A 1 clock receiving end.
5. The CPU 1A 2 transmitting end is connected to the CPU 2A 0 receiving end, and meanwhile, the CPU 1A 2 transmitting end clock is connected to the CPU 2A 0 receiving end clock; the CPU 2A 0 transmitting end is connected to the CPU 1A 2 receiving end, and the CPU 2A 0 transmitting end clock is connected to the CPU 1A 2 clock receiving end.
6. The CPU 2A 2 transmitting end is connected to the CPU3A0 receiving end, and meanwhile, the CPU 2A 2 transmitting end clock is connected to the CPU3A0 receiving end clock; the CPU3A0 transmitting end is connected to the CPU 2A 2 receiving end, and the CPU3A0 transmitting end clock is connected to the CPU 2A 2 clock receiving end.
Referring to fig. 3, a first topology diagram of a four-way server and a connection device according to an embodiment of the application is shown.
In one embodiment, the two processors and the two connection devices are connected in the manner shown in FIG. 3. In this embodiment, each processor and each connection device is provided with three a-BUS interfaces, which are A0, A1, and A2, respectively.
Specifically, the four-way server is provided with four CPU slots, a first processor is arranged in the first CPU slot, a first connecting device is arranged in the second CPU slot, a second connecting device is arranged in the third CPU slot, and a second processor is arranged in the fourth CPU slot.
The four CPU slots combined with fig. 2 correspond to the positions of CPU0, CPU1, CPU2, and CPU3, respectively. The first processor is arranged at the position of the CPU0, the first connecting device is arranged at the position of the CPU1, the second connecting device is arranged at the position of the CPU2, and the second processor is arranged at the position of the CPU 3.
Wherein a first A-BUS interface A0 of a first one of the processors is connected with a third A-BUS interface A2 of a second one of the processors, a second A-BUS interface A1 of the first one of the processors is connected with a second A-BUS interface A1 of a second one of the connection devices, and the third A-BUS interface A2 of the first one of the processors is connected with a first A-BUS interface A0 of the first one of the connection devices;
the second A-BUS interface A1 of the second processor is connected with the second A-BUS interface A1 of the first connecting device, and the first A-BUS interface A0 of the second processor is connected with the third A-BUS interface A2 of the second processor;
the third A-BUS interface A2 of the first said connection device is connected with the first A-BUS interface A0 of the second said connection device.
The second A-BUS interface of the first connecting device is connected with the second A-BUS interface of the second connecting device through a cable.
When the four-way server only needs to install two processors, in order to increase the interconnection bandwidth between the processors, a connection device needs to be installed in a CPU SOCKET (CPU SOCKET) where no processor is installed, and the two connection devices are connected by a cable.
Specifically, the CPU0 and the CPU3 mount processors, and the CPU1, the CPU2 mount connection devices. After installation, the connection relation between the CPU0 and the CPU3 is as follows:
specifically, the transmitting end of the CPU0A 0 is connected to the receiving end of the CPU3A 2, and meanwhile, the transmitting end clock of the CPU0A 0 is connected to the receiving end clock of the CPU3A 2; the CPU3A 2 transmitting end is connected to the CPU0A 0 receiving end, and the CPU3A 2 transmitting end clock is connected to the CPU0A 0 clock receiving end.
Specifically, the sending end of the CPU0A1 is connected to the receiving end of the CPU3A 1 through a connecting device arranged on the CPU2SOCKET through a CABLE (CABLE) and through a connecting device arranged on the CPU1 SOCKET, and meanwhile, the clock of the sending end of the CPU0A1 is connected to the clock of the receiving end of the CPU3A 1 through a connecting device arranged on the CPU2SOCKET and through a connecting device arranged on the CPU1 SOCKET through a CABLE (CABLE); the CPU3A 1 transmitting end is connected to the CPU0A1 receiving end through a connecting device installed on the CPU1 SOCKET through a CABLE (CABLE) and through a connecting device installed on the CPU2SOCKET, and meanwhile, the CPU3A 1 transmitting end clock is connected to the CPU0A2 receiving end clock through a connecting device installed on the CPU1 SOCKET and through a connecting device installed on the CPU2 SOCKET.
Specifically, the transmitting end of the CPU0A2 is connected to the receiving end of the CPU3A0 through a connecting device arranged on the CPU SOCKET1 and a connecting device arranged on the CPU2SOCKET, and meanwhile, the clock of the transmitting end of the CPU0A2 is connected to the clock of the receiving end of the CPU3A0 through a connecting device arranged on the CPU SOCKET1 and a connecting device arranged on the CPU2 SOCKET; the CPU3A0 transmitting end is connected to the CPU0A2 receiving end through a connecting device arranged on the CPU SOCKET2 and a connecting device arranged on the CPU1 SOCKET, and the CPU3A0 transmitting end clock is connected to the CPU0A2 clock receiving end through a connecting device arranged on the CPU SOCKET2 and a connecting device arranged on the CPU1 SOCKET.
So far, the CPU0 and the CPU3 form full connection; namely, CPU0A 0-CPU 3A 2, CPU0A1-CPU 3A 1, CPU0A 2-CPU 3A 0.
Referring to fig. 4, a second topology diagram of a four-way server according to an embodiment of the present application with the present connection device is shown.
In addition to the above connection relationship, a processor may be mounted on CPU0 or CPU1, and a connection device may be mounted on CPU2 or CPU 3. The specific connection is shown in fig. 4 below.
In this embodiment, the first a-BUS interface A0 of the first processor is connected to the third a-BUS interface A2 of the second connection device, the second a-BUS interface A1 of the first processor is connected to the second a-BUS interface A1 of the first connection device, and the third a-BUS interface A2 of the first processor is connected to the first a-BUS interface A1 of the second processor;
the second A-BUS interface A1 of the second processor is connected with the second A-BUS interface A1 of the second connecting device, and the third A-BUS interface A2 of the second processor is connected with the first A-BUS interface A0 of the first connecting device;
the third A-BUS interface A2 of the first said connection device is connected with the first A-BUS interface A0 of the second said connection device.
The second A-BUS interface of the first connecting device is connected with the second A-BUS interface of the second connecting device through a cable.
It should be noted that, the input end of the processor at the CPU0 position of the four-way server may be connected to a basic input/output system (Basic Input Output System, abbreviated as BIOS) to receive the input signal of the BIOS system, and the output ends of the processors and the connection devices at the positions of the CPU1, the CPU2 and the CPU3 may be connected to the BIOS system.
When the 4-path server is provided with only two processors, only one path of bus is connected between the processors; after the connecting device is added, the connecting bandwidth between the processors can be increased, the processors are interconnected by three buses, which is three times of the bandwidth of the traditional scheme, so that the interconnection bandwidth between the processors is greatly increased, and the data access delay is reduced.
In this embodiment, the embodiment of the present application provides a four-way server, which has the following beneficial effects: according to the application, the two connecting devices capable of receiving and transmitting clock signals are additionally arranged, and the time data ends and the clock ends of the two processors are connected in series through the two connecting devices, so that the bandwidth of the four-way server is increased, the communication rate is improved, and the data access delay is reduced.
Referring to fig. 5, a flow chart of an initialization method of a four-way server according to an embodiment of the present application is shown.
In an embodiment, the method for initializing the four-way server is applicable to the four-way server described in the above embodiment.
In an embodiment, different four-way servers need to configure different files for initialization processing, so as to accurately perform initialization processing according to placement positions of each processor in the four-way servers, where, as an example, the method for initializing the four-way servers may include:
s11, after the level detection signals of the CPU slots of the four-way server are obtained, the installation state of the CPU slots is determined according to the level detection signals, and the installation type comprises an in-place state and a type state.
An interface capable of collecting signals is designed on the CPU slot (CPU SOCKET), the level detection signal of the CPU slot (CPU SOCKET) can be detected, and whether the CPU slot (CPU SOCKET) is provided with an installation processor or a connection device is determined through the level detection signal; still alternatively, it may be determined by the level detection signal that the CPU SOCKET (CPU SOCKET) is currently mounted with a processor or a connection device.
Wherein the in-place state refers to whether a processor or a connecting device is installed; the type state means that the CPU SOCKET (CPU SOCKET) is currently installed with a processor or a connection device.
In one implementation, a level detection signal may be sent to a CPU SOCKET (CPU SOCKET), and then a level detection signal may be collected at an output terminal, and the bit state and the type state may be determined by determining whether the level detection signal is at a high level or a low level.
It should be noted that, the detection signals of the bit state and the type state may be connected to the GPIO of the CPU0 to enable the BIOS to obtain the installation information of other SOCKET.
In an alternative embodiment, the determination of the bit state may include the following sub-steps:
and S21, if the level detection signal is at a low level, determining that the in-place state is a mounting processor or a mounting connection device.
And S22, if the level detection signal is at a high level, determining that the bit state is a state that the processor is not installed or the connecting device is not installed.
Specifically, a detection signal for detecting an in-place state can be sent to a main board of the four-way server, the main board can pull up the in-place detection signal to be high level through a pull-up resistor, and if a processor or a connecting device is not installed in a CPU slot (CPU SOCKET), the signal is still high level at the moment; when the CPU SOCKET (CPU SOCKET) is provided with a processor or a connecting device, the processor or the connecting device strongly pulls down the bit signal, and the signal is at a low level. So that it can be determined whether the CPU SOCKET (CPU SOCKET) has the mounted processor or the connection means by the high and low level.
In an alternative embodiment, the determining the type state includes:
and S31, if the level detection signal is at a low level, determining that the type state is a CPU slot installation processor.
S32, if the level detection signal is at a high level, determining that the type state is the CPU slot installation connection device.
Specifically, the detection signal for performing the type state detection may also be sent to the motherboard of the four-way server, and the motherboard may pull the type detection signal high to a high level through a pull-up resistor. When the CPU slot (CPU SOCKET) installs the CPU, the CPU strongly pulls the signal low, and the type detection signal is at low level; when the connection means are installed, the connection means do not process the signal, which is still high. The technical effect of quickly determining the type of the device mounted in the CPU SOCKET (CPU SOCKET) is achieved through the high and low levels.
Referring to the following table, showing the state detection result, if a high level is represented by 1 and a low level is represented by 0, the bit state and the type state are as shown in the following table 1:
status detection result In-situ detection signal Type detection signal Code
SOCKET installs CPU 0 0 00
SOCKET mounting and connecting device 0 1 01
Not mounted with any devices 1 1 11
TABLE 1
The on-site state detection and the type state detection may be performed simultaneously, or may be performed separately, or may be performed first according to a user's need, and then the type state detection may be performed first, or may be performed first, and then the on-site state detection may be performed.
And S12, sending a corresponding configuration file to the four-way server based on the installation state so that the four-way server can be initialized by adopting the configuration file.
In an embodiment, the corresponding configuration file may be sent to the four-way server according to different states, so that the four-way server performs the server initialization operation according to the configuration file.
In an embodiment, the BIOS may store XML configuration files for different configurations, and the BIOS may perform configuration according to the different XML configuration files when starting to complete system startup.
In one implementation, the configuration files corresponding to the different states are shown in table 2 below:
TABLE 2
In this embodiment, the embodiment of the present application provides a method for initializing a four-way server, which has the following beneficial effects: the application can detect the installation condition, the installation position and the type of the installed device of each CPU slot in the four-way server through the level detection signal, further determine the corresponding configuration file according to different conditions and send the configuration file to the four-way server for the four-way server to initialize so as to adapt to the work of the four-way server.
The embodiment of the application also provides an initializing device of the four-way server, and referring to fig. 6, a schematic structural diagram of the initializing device of the four-way server is shown.
As an example, the initializing device of the four-way server may include:
a determining module 601, configured to determine an installation state of a CPU socket of a four-way server according to a level detection signal after obtaining the level detection signal of the CPU socket, where the installation type includes an in-place state and a type state;
and an initialization module 602, configured to send a corresponding configuration file to the four-way server based on the installation state, so that the four-way server can initialize with the configuration file.
Optionally, the determining manner of the in-place state includes:
if the level detection signal is at a low level, determining that the in-place state is an installation processor or an installation connecting device;
and if the level detection signal is at a high level, determining that the bit state is that the processor is not installed or the connecting device is not installed.
Optionally, the determining manner of the type state includes:
if the level detection signal is at a low level, determining that the type state is a CPU slot installation processor;
and if the level detection signal is at a high level, determining that the type state is a CPU slot installation connection device.
It will be clearly understood by those skilled in the art that, for convenience and brevity, the specific working process of the apparatus described above may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
Further, an embodiment of the present application further provides an electronic device, including: the system comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the processor realizes the initialization method of the four-way server according to the embodiment when executing the program.
Further, the embodiment of the application also provides a computer-readable storage medium storing a computer-executable program for causing a computer to execute the four-way server initialization method according to the above embodiment.
While the foregoing is directed to the preferred embodiments of the present application, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the application, such changes and modifications are also intended to be within the scope of the application.

Claims (10)

1. A connection device, the connection device comprising: the device comprises a connector, a redrive chip and three A-BUS interfaces;
the first A-BUS interface is connected with the third A-BUS interface, the second A-BUS interface is respectively connected with the redrive chip and the connector, and the redrive chip is connected with the connector; the connection mode comprises a data signal and a clock signal.
2. A four-way server, the four-way server comprising: two processors and two connecting means according to claim 1;
the three A-BUS interfaces of the first processor are respectively connected with one A-BUS interface of the second processor and one A-BUS interface corresponding to the two connecting devices respectively, the other two A-BUS interfaces of the second processor are respectively connected with the other A-BUS interfaces corresponding to the two connecting devices respectively, the other A-BUS interfaces of the two connecting devices are connected in series, so that the two processors are connected in series, and the two connecting devices are connected in series.
3. The four-way server according to claim 2, wherein the four-way server is provided with four CPU slots, a first one of the processors is provided in a first one of the CPU slots, a first one of the connection devices is provided in a second one of the CPU slots, a second one of the connection devices is provided in a third one of the CPU slots, and a second one of the processors is provided in a fourth one of the CPU slots;
the first A-BUS interface of the first processor is connected with the third A-BUS interface of the second processor, the second A-BUS interface of the first processor is connected with the second A-BUS interface of the second connecting device, and the third A-BUS interface of the first processor is connected with the first A-BUS interface of the first connecting device;
the second A-BUS interface of the second processor is connected with the second A-BUS interface of the first connecting device, and the first A-BUS interface of the second processor is connected with the third A-BUS interface of the second processor;
the third A-BUS interface of the first connecting device is connected with the first A-BUS interface of the second connecting device;
the second A-BUS interface of the first connecting device is connected with the second A-BUS interface of the second connecting device through a cable.
4. The four-way server according to claim 2, wherein the four-way server is provided with four CPU slots, a first one of the processors being provided in a first one of the CPU slots, a second one of the processors being provided in a second one of the CPU slots, a first one of the connection devices being provided in a third one of the CPU slots, a second one of the connection devices being provided in a fourth one of the CPU slots;
the first A-BUS interface of the first processor is connected with the third A-BUS interface of the second connecting device, the second A-BUS interface of the first processor is connected with the second A-BUS interface of the first connecting device, and the third A-BUS interface of the first processor is connected with the first A-BUS interface of the second processor;
the second A-BUS interface of the second processor is connected with the second A-BUS interface of the second connecting device, and the third A-BUS interface of the second processor is connected with the first A-BUS interface of the first connecting device;
the third A-BUS interface of the first connecting device is connected with the first A-BUS interface of the second connecting device;
the second A-BUS interface of the first connecting device is connected with the second A-BUS interface of the second connecting device through a cable.
5. A method for initializing a four-way server, the method comprising:
after the level detection signals of the CPU slots of the four-way server are obtained, determining the installation state of the CPU slots according to the level detection signals, wherein the installation type comprises an in-place state and a type state;
and sending a corresponding configuration file to the four-way server based on the installation state so that the four-way server can be initialized by adopting the configuration file.
6. The method for initializing a four-way server according to claim 5, wherein the determining manner of the in-place status includes:
if the level detection signal is at a low level, determining that the in-place state is an installation processor or an installation connecting device;
and if the level detection signal is at a high level, determining that the bit state is that the processor is not installed or the connecting device is not installed.
7. The method for initializing a four-way server according to claim 5, wherein the determining manner of the type state comprises:
if the level detection signal is at a low level, determining that the type state is a CPU slot installation processor;
and if the level detection signal is at a high level, determining that the type state is a CPU slot installation connection device.
8. An initializing device of a four-way server, the device comprising:
the system comprises a determining module, a judging module and a judging module, wherein the determining module is used for determining the installation state of a CPU slot according to the level detection signal after the level detection signal of the CPU slot of the four-way server is obtained, and the installation type comprises an in-place state and a type state;
and the initialization module is used for sending a corresponding configuration file to the four-way server based on the installation state so that the four-way server can be initialized by adopting the configuration file.
9. An electronic device, comprising: memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method for initializing a four-way server according to any one of claims 5-7 when executing the computer program.
10. A computer-readable storage medium storing a computer-executable program for causing a computer to execute the four-way server initialization method according to any one of claims 5 to 7.
CN202310764643.2A 2023-06-26 2023-06-26 Connection device, four-way server, and initialization method and device of four-way server Pending CN116737641A (en)

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