CN107436860A - A kind of 8 road server UPI interconnection topology devices - Google Patents
A kind of 8 road server UPI interconnection topology devices Download PDFInfo
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- CN107436860A CN107436860A CN201710680365.7A CN201710680365A CN107436860A CN 107436860 A CN107436860 A CN 107436860A CN 201710680365 A CN201710680365 A CN 201710680365A CN 107436860 A CN107436860 A CN 107436860A
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- upi
- calculate node
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- mezz
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17362—Indirect interconnection networks hierarchical topologies
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention discloses a kind of 8 road server UPI interconnection topology devices, including calculate node NODE0, calculate node NODE1, backboard, UPI mezz, 4 intel Skylake processors are disposed above calculate node.4 processors are arranged in corner in square shape, and 4 processors form an annular in a calculate node.8 tunnels can be interconnected UPI passages and be divided into forward and backward two parts by this topology, and UPI is exported respectively before and after calculate node, avoids exporting from side and taking more spaces, so as to reduce calculate node width.
Description
Technical field
The present invention relates to server technology field, especially a kind of 8 road server UPI interconnection topology devices.
Background technology
Intel Purley platform Skylake multiprocessors interconnections upgrade to UPI from QPI1.1, and speed is reachable
11.2Gbps.Processor based on UPI equally has 3 port, and highest can support 8 processor interconnections.UPI is by 20lane groups
Into i.e. TX, RX respectively have 20 groups of high-speed differential signals.Different with QPI interconnection techniques, UPI clock mechanisms are embedded clocks, similar
In these I/O standards of PCIe, USB.
With the raising of UPI speed, the requirement to hardware design is also stricter.In specific design, line length control, connect
Connect device type selecting, sheet material type selecting, UPI topological layouts are required for comprehensive consideration because these factors have to signal error rate, Insertion Loss
And directly affect.
Prior art is to use 4 pieces of calculate nodes, and 2 processors are disposed in each calculate node.Pass through one piece
Backplate interconnects the UPI of 4 pieces of calculate nodes.The shortcomings that prior art is the interconnection that realize 4 pieces of calculate nodes,
Hardware design implements more complicated.UPI track lengths are longer, so as to which signal quality can not be protected.And 4 pieces calculate section
The heap overlay cabinet requirement for height of point is higher, increases cabinet cost.
The content of the invention
It is an object of the invention to provide a kind of 8 road server UPI interconnection topology devices, the length of UPI buses can be optimized
And cabling, so as to reach optimization signal quality and save the purpose of PCB layer number.
To achieve the above object, the present invention uses following technical proposals：
A kind of 8 road server UPI interconnection topology devices, including calculate node NODE0, calculate node NODE1, backboard, UPI
Four CPU are disposed on mezz, calculate node NODE0 and calculate node NODE1 respectively：Calculate node NODE0 deployment CPU0,
CPU1, CPU2, CPU3, CPU0, CPU1, CPU2, CPU3 are attached to form the first link circuit successively, calculate node NODE1
CPU4, CPU5, CPU6, CPU7 are disposed, CPU4, CPU5, CPU6, CPU7 are attached to form the second link circuit successively；UPI
Mezz provides the UPI forward connection passages of interconnection：CPU2 is attached with CPU6, and CPU3 is attached with CPU7；Backboard provides
The backward interface channel of UPI interconnection：CPU0 is attached with CPU5, and CPU1 is attached with CPU4.
Further, the UPI mezz include two pieces of UPI intermediate layers connectors：First UPI intermediate layers connector provides
Interface channel between CPU2 and CPU6, the 2nd UPI intermediate layers connector provide the interface channel between CPU3 and CPU7.
Further, the UPI mezz include one piece of UPI intermediate layers connector, and UPI intermediate layers connector provides
The interface channel between interface channel, CPU3 and CPU7 between offer CPU2 and CPU6.
Further, the corresponding connector of the UPI of corresponding three ports of the CPU, each UPI, the one of the CPU0
Individual port UP I is connected by the first high speed connector with CPU5；The a port UPI of the CPU1 passes through the second high speed connector
It is connected with CPU4.
The invention has the advantages that
1st, 8 road UPI topological structures of the invention can optimize the length and cabling of UPI buses, so as to reach optimization signal matter
Amount and the purpose for saving PCB layer number.The stacking of two layers of calculate node can be effectively reduced cabinet height, reduce cabinet cost and throw
Enter.
2nd, NODE0, NODE1 are calculate node parts.Its hardware composition is identical, and 4 are disposed above calculate node
Intel Skylake processors.4 processors are arranged in corner in square shape, and 4 processors form in a calculate node
One annular.8 tunnels can be interconnected UPI passages and be divided into forward and backward two parts by this topology, and UPI divides before and after calculate node
Do not export, avoid exporting from side and taking more spaces, so as to reduce calculate node width.
3rd, the application one embodiment sets two pieces of UPI intermediate layers connectors, and UPI on the one hand is distributed into two UPI
High speed connector quantity on mezz, so each UPI mezz halves.In dismounting, contact engaging and separating force can reduce half, more save
Power, it is easy to operation.UPI buses above second, two UPI mezz connect two CPU respectively, and UPI can be adjusted flexibly
Mezz position, it is most short to reach UPI buses line length.
Brief description of the drawings
Accompanying drawing described herein is used for providing that the present invention is explained further, and forms the part of the application, this hair
Bright schematic description and description is used to explain the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is the UPI interconnection topology connection relationship diagrams using 4 pieces of calculate nodes；
Fig. 2 is the UPI interconnection topological connection relation schematic diagrames of the embodiment of the present invention one；
Fig. 3 is the UPI interconnection topological connection relation schematic diagrames of the embodiment of the present invention two.
Embodiment
For the technical characterstic for illustrating this programme can be understood, below by embodiment, and its accompanying drawing is combined, to this hair
It is bright to be described in detail.Following disclosure provides many different embodiments or example is used for realizing the different knots of the present invention
Structure.In order to simplify disclosure of the invention, hereinafter the part and setting of specific examples are described.In addition, the present invention can be with
Repeat reference numerals and/or letter in different examples.This repetition is that for purposes of simplicity and clarity, itself is not indicated
Relation between various embodiments are discussed and/or set.It should be noted that part illustrated in the accompanying drawings is not necessarily to scale
Draw.Present invention omits the description to known assemblies and treatment technology and process to avoid being unnecessarily limiting the present invention.
As shown in figure 1, prior art is to use 4 pieces of calculate nodes, 2 processors are disposed in each calculate node,
The UPI of 4 pieces of calculate nodes is interconnected by one piece of Backplate.4 pieces of calculate nodes are used in the prior art, due to realize 4
The stacking of block calculate node, backboard size is bigger, and the connector above backboard with calculate node docking is more.Due to the back of the body
Board size increases, and cabinet height can also increase, and can bring the increase of cost.Due to realize the UPI of 4 pieces of calculate nodes in backboard
Upper interconnection, UPI buses are more scattered, therefore PCB design difficulty also can accordingly increase.
Embodiment one
As shown in Fig. 28 road server UPI interconnection topology devices, including calculate node NODE0, calculate node NODE1, the back of the body
Four CPU are disposed on plate, UPI mezz, calculate node NODE0 and calculate node NODE1 respectively：Calculate node NODE0 is disposed
CPU0, CPU1, CPU2, CPU3, CPU0, CPU1, CPU2, CPU3 are attached to form the first link circuit, calculate node successively
NODE1 disposes CPU4, CPU5, CPU6, CPU7, and CPU4, CPU5, CPU6, CPU7 are attached to form the second link circuit successively；
UPI mezz provide the UPI forward connection passages of interconnection：CPU2 is attached with CPU6, and CPU3 is attached with CPU7；Backboard
The UPI backward interface channels of interconnection are provided：CPU0 is attached with CPU5, and CPU1 is attached with CPU4.
4 intel Skylake processors are disposed above calculate node.4 processors are arranged in corner in square shape, and 4
Processor forms an annular in a calculate node.This topology can by 8 tunnels interconnect UPI passages be divided into it is preceding to it is rear
To two parts, UPI is exported respectively before and after calculate node, avoids exporting from side and taking more spaces, so as to reduce meter
Operator node width.
The UPI mezz include two pieces of UPI intermediate layers connectors：First UPI intermediate layers connector provides CPU2 and CPU6
Between interface channel, the 2nd UPI intermediate layers connector provides the interface channel between CPU3 and CPU7.Set in two pieces of UPI
The benefit of interbed connector is as follows：One, UPI is distributed to two UPI mezz, the high speed connection on so each UPI mezz
Device quantity halves.In dismounting, contact engaging and separating force can reduce half, more laborsaving, easy to operation.Above two, two UPI mezz
UPI buses connect two CPU respectively, and UPI mezz position can be adjusted flexibly, most short to reach UPI buses line length.
The corresponding connector of the UPI of corresponding three ports of the CPU, each UPI, a port UPI of the CPU0
It is connected by the first high speed connector with CPU5；The a port UPI of the CPU1 is connected by the second high speed connector and CPU4
Connect.
Embodiment two
As shown in figure 3,
The difference of embodiment two and embodiment one is that UPI mezz include one piece of UPi intermediate layers connector, described
The interface channel between interface channel, CPU3 and CPU7 between UPI intermediate layers connector offer offer CPU2 and CPU6.
Although above-mentioned the embodiment of the present invention is described with reference to accompanying drawing, model not is protected to the present invention
The limitation enclosed, one of ordinary skill in the art should be understood that on the basis of technical scheme those skilled in the art are not
Need to pay various modifications or deformation that creative work can make still within protection scope of the present invention.
Claims (4)
1. a kind of 8 road server UPI interconnection topology devices, it is characterized in that, including calculate node NODE0, calculate node NODE1,
Four CPU are disposed on backboard, UPI mezz, calculate node NODE0 and calculate node NODE1 respectively：Calculate node NODE0 is disposed
CPU0, CPU1, CPU2, CPU3, CPU0, CPU1, CPU2, CPU3 are attached to form the first link circuit, calculate node successively
NODE1 disposes CPU4, CPU5, CPU6, CPU7, and CPU4, CPU5, CPU6, CPU7 are attached to form the second link circuit successively；
UPI mezz provide the UPI forward connection passages of interconnection：CPU2 is attached with CPU6, and CPU3 is attached with CPU7；Backboard
The UPI backward interface channels of interconnection are provided：CPU0 is attached with CPU5, and CPU1 is attached with CPU4.
2. 8 road server UPI interconnection topology devices of one kind as claimed in claim 1, it is characterized in that, the UPI mezz include
Two pieces of UPI intermediate layers connectors：First UPI intermediate layers connector provides the interface channel between CPU2 and CPU6, in the 2nd UPI
Interbed connector provides the interface channel between CPU3 and CPU7.
3. 8 road server UPI interconnection topology devices of one kind as claimed in claim 1, it is characterized in that, the UPI mezz include
One piece of UPI intermediate layers connector, UPI intermediate layers connector provide interface channel, the CPU3 between CPU2 and CPU6
Interface channel between CPU7.
4. 8 road server UPI interconnection topology devices of one kind as claimed in claim 1, it is characterized in that, the CPU is corresponding three
The corresponding connector of the UPI of port, each UPI, a port UPI of the CPU0 pass through the first high speed connector and CPU5
Connection；The a port UPI of the CPU1 is connected by the second high speed connector with CPU4.
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| CN201710680365.7A CN107436860A (en) | 2017-08-10 | 2017-08-10 | A kind of 8 road server UPI interconnection topology devices |
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| CN110389927A (en) * | 2019-06-18 | 2019-10-29 | 苏州浪潮智能科技有限公司 | A kind of four road servers |
| US10489341B1 (en) * | 2018-06-25 | 2019-11-26 | Quanta Computer Inc. | Flexible interconnect port connection |
| US10559904B1 (en) | 2019-03-19 | 2020-02-11 | Cisco Technology, Inc. | Link module for a scalable multiprocessor system |
| CN111090967A (en) * | 2019-11-29 | 2020-05-01 | 苏州浪潮智能科技有限公司 | PCB layout structure, PCB layout method, PCB wiring method and server mainboard |
| CN113626370A (en) * | 2021-07-29 | 2021-11-09 | 苏州浪潮智能科技有限公司 | Multi-path CPU interconnection system |
| CN116737641A (en) * | 2023-06-26 | 2023-09-12 | 合芯科技有限公司 | Connection device, four-way server, and initialization method and device of four-way server |
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Application publication date: 20171205 |