CN114153784A

CN114153784A - UPI signal interconnection device and N-path server

Info

Publication number: CN114153784A
Application number: CN202111338664.5A
Authority: CN
Inventors: 王玉山
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-03-08

Abstract

The invention discloses a UPI signal interconnection device and an N-path server, wherein a processing module controls a controllable switch module corresponding to an in-place and to-be-communicated CPU module to be conducted to realize data transmission when judging that the CPU modules are in place and any two CPU modules in the in-place CPU modules are to be communicated; when the CPU module is judged not in place, the controllable switch module corresponding to the CPU module which is not in place is controlled to be switched off, at the moment, for the CPU module which is in place, N UPI signal lines can be used for transmitting data when the CPU module which is in place is in a condition of waiting for communication, the problem of UPI signal resource waste when the N CPU modules are not full in the prior art is solved, and the data transmission throughput between the CPUs which are in place and wait for communication is improved.

Description

UPI signal interconnection device and N-path server

Technical Field

The invention relates to the field of server design, in particular to a UPI signal interconnection device and an N-path server.

Background

The N-way server includes N CPUs (central processing units), each CPU includes N UPI (Ultra Path Interconnect) signal transmission pins, each CPU is connected to a UPI signal line through the UPI signal transmission pin to implement UPI signal interconnection, and N is 1 or an even number greater than 1. In the design of the multi-path server, a plurality of CPUs and UPI signal routing thereof are all arranged on one main board, wherein at least one UPI signal line is connected between any two CPUs in the plurality of CPUs to realize data transmission, and the total number of the UPI signal lines connected with each CPU is N. However, in the use process of the multi-path server, a situation that a plurality of CPUs are not fully configured, that is, one or more CPUs are not in place may occur, at this time, because the topological structure is fixed, a plurality of UPI signal lines connected with the CPU which is not in place cannot be used for data transmission, which results in the waste of UPI signal resources and limits the data transmission throughput between the CPUs in place.

Specifically, referring to fig. 1, fig. 1 is a topology structure of a four-way server in the prior art, each CPU includes 4 UPI signal lines, and at least one UPI signal line is connected between any two of the 4 CPUs, where UPI _01 indicates that it is only used for signal transmission between the CPU0 and the CPU 1. When the 4 CPUs are not fully matched, for example, the CPU0 is not in place and the

CPUs

1, 2 and 3 are in place, 4 UPI signal lines connected with the CPU0 cannot be used for data transmission, at this time, for the CPU1 in place, since the four-way topology is fixed and cannot be changed, the UPI _01 connected with the CPU0 cannot be used, so that only three UPI signal lines of the CPU1 can be used for data transmission, and similarly, the

CPUs

2 and 3 limit the data transmission throughput among the CPUs 1, the CPUs 2 and the CPUs 3. Therefore, in the prior art, no matter which topology structure is adopted to connect a plurality of CPUs to realize the UPI signal interconnection, the UPI signal resource waste caused by the fact that the plurality of CPUs are not satisfied in the use process after the topology structure is fixed is caused by the mode.

Disclosure of Invention

The invention aims to provide a UPI signal interconnection device and an N-path server, which are used for interconnecting N UPI signal output ends of N CPU modules through the UPI signal interconnection device, solving the problem of UPI signal resource waste when the N CPU modules are not full in the prior art and improving the data transmission throughput between on-site CPUs to be communicated.

In order to solve the technical problem, the invention provides a UPI signal interconnection device which is applied to an N-path server, wherein the N-path server comprises N CPU modules, a mainboard and the UPI signal interconnection device arranged on the mainboard; the UPI signal interconnection device comprises a board card, and a processing module, N connectors and N controllable switch modules which are arranged on the board card, wherein N is 1 or an even number greater than 1;

the N in-place detection ends of the processing module are respectively connected with the in-place transmission ends of the N connectors in a one-to-one corresponding manner, and the N control ends of the processing module are respectively connected with the control ends of the N controllable switch modules in a one-to-one corresponding manner and are used for controlling the controllable switch modules corresponding to the CPU modules which are in place and are to be communicated to be switched on when the in-place transmission ends of the connectors judge that the CPU modules are in place and any two CPU modules in the CPU modules which are in place are to be communicated, and controlling the controllable switch modules corresponding to the CPU modules which are not in place to be switched off when the CPU modules are judged to be not in place;

the I controllable switch module comprises a connector, a I controllable switch module, N UPI signal transmission ends of the I controllable switch module are correspondingly connected with N UPI signal output ends of the I CPU module through the I connector, the I connector is connected with the I CPU module in-place transmission end, any two controllable switch modules are connected through N UPI signal lines, and i is more than or equal to 1 and less than or equal to N.

Preferably, the ith controllable switch module comprises N-1 groups of N sub-switches and a control module connected with the control ends of the N-1 groups of N sub-switches;

the first ends of N subswitches in each of N-1 groups of N subswitches of the ith controllable switch module are correspondingly connected with N UPI signal output ends of the ith CPU module through the ith connector; the second ends of two groups of N sub-switches between any two controllable switch modules are correspondingly connected one by one through N UPI signal lines;

the control module is used for controlling the conduction and the disconnection of each sub-switch in the N-1 groups of the N sub-switches according to the control signal which is sent by the processing module and used for controlling the conduction and the disconnection of the ith controllable switch module.

Preferably, the N CPU modules are disposed on any two or more side surfaces of four side surfaces of the chassis of the N-way server;

the ith CPU module comprises a CPU, a power supply and a memory bank, wherein N UPI signal transmission pins of the CPU are used as N UPI signal output ends of the CPU module.

Preferably, the processing module is a CPLD.

Preferably, the storage module on the N-way server is arranged outside the chassis of the N-way server;

and the N CPU modules are connected with the storage module.

Preferably, the system also comprises a prompt module;

the prompting module is connected with the processing module and is used for prompting the in-place conditions of the N CPU modules judged by the processing module.

Preferably, the prompt module includes indicator lights corresponding to the N CPU modules one to one, and is configured to light up when the processing module determines that the ith CPU module is in place, and light off when the processing module determines that the ith CPU module is not in place.

Preferably, the board card is a multilayer board card;

when N first UPI signal lines between two controllable switch modules are crossed with N second UPI signal lines between any other two controllable switch modules, the crossed N first UPI signal lines and the crossed N second UPI signal lines are arranged on different signal layers of the board card.

In order to solve the technical problem, the invention further provides an N-way server, which comprises N CPU modules, a motherboard, and the UPI signal interconnection apparatus described above, wherein the UPI signal interconnection apparatus is disposed on the motherboard.

The invention provides a UPI signal interconnection device and an N-path server, which are used for interconnecting N UPI signal output ends of N CPU modules through the UPI signal interconnection device. Specifically, when the processing module judges that any two CPU modules in the CPU modules are in place and in place are to be communicated, the processing module controls the controllable switch modules corresponding to the CPU modules in place and to be communicated to be conducted so as to realize data transmission; when the CPU module is judged not to be in place, the controllable switch module corresponding to the CPU module which is not in place is controlled to be switched off, at the moment, for the CPU module which is in place, N UPI signal lines can be used for transmitting data when the CPU module which is in place is in a condition of waiting for communication, the condition that the UPI signal line connected with the CPU module which is not in place in the N UPI signal lines of the CPU module which is in place and waits for communication in the prior art is occupied can not be avoided, the problem of UPI signal resource waste when the N CPU modules are not full in the prior art is solved, and the data transmission throughput between the CPUs which are in place and wait for communication is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a topology of a four-way server in the prior art;

fig. 2 is a schematic structural diagram of a UPI signal interconnection apparatus provided in the present invention;

fig. 3 is a schematic structural diagram of another UPI signal interconnection apparatus provided by the present invention.

Detailed Description

The core of the invention is to provide a UPI signal interconnection device and an N-path server, which realize interconnection of N UPI signal output ends of N CPU modules through the UPI signal interconnection device, solve the problem of UPI signal resource waste when N CPU modules are not full in the prior art, and improve the data transmission throughput between on-site CPUs to be communicated.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a UPI signal interconnection apparatus provided in the present invention, wherein a four-way server with N being 4 is taken as an example.

The UPI signal interconnection device is applied to an N-path server, wherein the N-path server comprises N CPU modules, a mainboard and the UPI signal interconnection device arranged on the mainboard; the UPI signal interconnection device comprises a board card, and a processing module 1, N connectors 2 and N controllable switch modules 3 which are arranged on the board card, wherein N is 1 or an even number more than 1;

the N in-place detection ends of the processing module 1 are respectively and correspondingly connected with the in-place transmission ends of the N connectors 2, and the N control ends of the processing module 1 are respectively and correspondingly connected with the control ends of the N controllable switch modules 3, so that when the in-place transmission ends of the connectors 2 judge that any two CPU modules in the CPU modules are in place and are to be communicated, the controllable switch modules 3 corresponding to the CPU modules in place and to be communicated are controlled to be switched on, and when the CPU modules are judged not in place, the controllable switch modules 3 corresponding to the CPU modules not in place are controlled to be switched off;

n UPI signal transmission ends of the ith controllable switch module 3 are correspondingly connected with N UPI signal output ends of the ith CPU module through the ith connector 2, the in-place transmission end of the ith connector 2 is connected with the in-place output end of the ith CPU module, any two controllable switch modules 3 are connected through N UPI signal lines, wherein i is more than or equal to 1 and is less than or equal to N.

In this embodiment, in consideration of the fact that N CPUs are likely to be not fully configured in the actual use process of the N-way server in the prior art, at this time, since the topology structure of the N-way server is already fixed, a plurality of UPI signal lines connected to off-site CPUs cannot be used for data transmission, which results in waste of UPI signal resources and limits data transmission throughput between on-site CPUs. The application provides a UPI signal interconnection device, which interconnects N UPI signal output ends of N CPU modules through the UPI signal interconnection device.

The UPI signal interconnection device comprises a board card, a processing module 1 arranged on the board card, N connectors 2 and N controllable switch modules 3, wherein an ith CPU module transmits an in-place signal representing whether the ith CPU module is in place to an in-place transmission end of the ith connector 2 through an in-place output end of the ith CPU module, the ith CPU module is transmitted to an in-place detection end of the processing module 1 through the ith connector 2, the processing module 1 judges whether the ith CPU module is in place through the in-place signal transmitted by the in-place transmission end of the ith connector 2, and i is more than or equal to 1 and less than or equal to N. It should be noted that the bit signal may be low when the ith CPU module is not in bit, and may be high when the ith CPU module is in bit, and the connector 2 may be a high-speed connector capable of transmitting a high-speed UPI signal, which is not particularly limited herein. Then, in combination with the connection mode between the UPI signal output ends of the N CPU modules and the UPI signal interconnection apparatus and the connection mode between the N controllable switch modules 3, the processing module 1 controls the controllable switch module 3 corresponding to the CPU module in place and to be communicated to be turned on when it determines that there is a CPU module in place and that communication is to be performed between any two CPU modules in the CPU modules in place through the in-place transmission ends of the N connectors 2; when the CPU module is judged not to be in place, the controllable switch module 3 corresponding to the CPU module not in place is controlled to be turned off, wherein the mode of controlling the controllable switch module 3 to be turned on can be that an enabling signal is sent to the controllable switch module 3, and the enabling signal is at a high level; the manner of controlling the controllable switch module 3 to turn off may be to send a turn-off signal to the controllable switch module 3, where the turn-off signal is at a low level, and the present application is not limited thereto. Therefore, the UPI signal interconnection device can realize the UPI signal interconnection among the N CPU modules, and the condition that the UPI signal line connected with the CPU module which is not in place in the N UPI signal lines of the CPU module which is in place and is to be communicated in the prior art is occupied can not occur.

Specifically, taking a four-way server as an example, as shown in fig. 2, the four-way server includes four CPU modules, which are respectively a CPU module 0, a CPU module 1, a CPU module 2, and a CPU module 3, and each CPU module includes four UPI signal output ends and one on-site output end. Taking the CPU module 0 as an example to explain the meaning of each connection line in fig. 2, the four UPI signal output ends of the CPU module 0 are CPU _ UPI0, CPU _ UPI1, CPU _ UPI2 and CPU _ UPI3, and one in-place output end of the CPU module 0 is PRSNT _ 0. The connection line between the CPU module 0 and the connector 2 at the upper left corner may be a cable in practice, and the thickening line between the connector 2 at the upper left corner and the controllable switch module 3 at the upper left corner actually includes four UPI signal lines, in this embodiment, for simplicity and convenience of description, a thickening line is drawn in fig. 2, and the thickening line between the connector 2 at the lower left corner and the controllable switch module 3 at the lower left corner, the thickening line between the connector 2 at the upper right corner and the controllable switch module 3 at the upper right corner, and the thickening line between the connector 2 at the lower right corner and the controllable switch module 3 at the lower right corner also may be used. The processing module 1 receives an in-place signal transmitted by an in-place output end of the CPU module 0 through the connector 2 at the upper left corner through the in-place detection pin PRSNT _0 to determine whether the CPU module 0 is in place, and sends a control signal to the controllable switch module 3 at the upper left corner through a control end, i.e., a SEL _0 pin, connected to the controllable switch module 3 at the upper left corner to control on and off of the controllable switch module 3 at the upper left corner. Therefore, when the processing module 1 judges that the four CPU modules are full through the PRSNT _ [0-3] signal, the four UPI signal transmission ends of the four CPU modules realize the UPI interconnection through the UPI signal transmission device; when the processing module 1 determines that the four CPU modules are not full through the PRSNT _ [0-3] signal, the following is further described by taking the example of configuring the CPU module 0 and the CPU module 2 in place and waiting for communication: at this time, the processing module 1 determines that the CPU module 0 and the CPU module 2 are in place and are to be communicated, controls the controllable switch module 3 at the upper left corner and the controllable switch module 3 at the lower left corner to be turned on, and controls the controllable switch module 3 at the upper right corner and the controllable switch module 3 at the lower right corner to be turned off, so that four UPI signal transmission terminals of the CPU module 0 and four UPI signal transmission terminals of the CPU module 2 are interconnected, in the prior art, as shown in fig. 1, when the CPU0 and the CPU2 are configured in place and are to be communicated, only 2 UPI signal transmission terminals of the CPU0 and 2 UPI signal transmission terminals of the CPU2 are interconnected at this time, that is, the UPI _02_1 and the UPI _02_2, waste of UPI signal resources is caused, and data transmission throughput between the CPU0 and the CPU2 which are in place and are to be communicated is limited.

It should be noted that, in the practical application of the N-way server, at the same time, even if there are more than two CPU modules in place, there may be only two CPU modules that actually perform UPI signal transmission at the same time, so when the processing module 1 determines, through the in-place transmission ends of the N connectors 2, that there is a CPU module in place and that communication is to be performed between any two CPU modules in the CPU modules in place, the controllable switch module 3 corresponding to the CPU module in place and to be communicated is controlled to be turned on.

It should be noted that the processing module 1 herein may be a CPLD (Complex Programmable Logic Device), and the application is not limited thereto.

In addition, the UPI signal interconnection apparatus can also be applied to other high-density servers with centralized power supply, and the application is not limited in particular.

In summary, the present application provides a UPI signal interconnection apparatus, which interconnects N UPI signal output terminals of N CPU modules through the UPI signal interconnection apparatus. The method and the device ensure that N UPI signal lines can be used for transmitting data when the CPU module in place is in a condition of waiting for communication, the condition that the UPI signal line connected with the CPU module out of the N UPI signal lines of the CPU module in place and waiting for communication in the prior art is occupied can not be avoided, the problem of UPI signal resource waste when the N CPU modules are not full in the prior art is solved, and the data transmission throughput between the CPUs in place and waiting for communication is improved.

On the basis of the above-described embodiment:

as a preferred embodiment, the ith controllable switch module 3 includes N-1 groups of N sub-switches and a control module connected to control terminals of the N-1 groups of N sub-switches;

the first ends of each N sub-switches of the N-1 groups of N sub-switches of the ith controllable switch module 3 are correspondingly connected with N UPI signal output ends of the ith CPU module one by one through an ith connector 2; the second ends of the two groups of N sub-switches between any two controllable switch modules 3 are correspondingly connected one by one through N UPI signal lines;

the control module is used for controlling the conduction and the disconnection of each sub-switch in the N-1 groups of the N sub-switches according to the control signal which is sent by the processing module 1 and used for controlling the conduction and the disconnection of the ith controllable switch module 3.

In this embodiment, the ith controllable switch module 3 may be a control module including N-1 groups of N sub-switches and a control terminal connected to the control terminal of the N-1 groups of N sub-switches, and the control module may control the on and off of each sub-switch in the N-1 groups of N sub-switches according to a control signal sent by the processing module 1 to control the on and off of the ith controllable switch module 3.

Specifically, when the ith CPU module is not in place, the processing module 1 may control the ith controllable switch module 3 corresponding to the ith CPU module to be turned off, and when the control module in the ith controllable switch module 3 receives a control signal indicating turn-off sent by the processing module 1, the control module may control each of N-1 sets of N subswitches in the ith controllable switch module 3 to be turned off;

when the ith CPU module is in place and is to be communicated, the processing module 1 may control the ith controllable switch module 3 corresponding to the ith CPU module to be turned on, and when the control module in the ith controllable switch module 3 receives the control signal indicating turn-on sent by the processing module 1, the control module may control turn-on and turn-off of each of the N-1 sets of N sub-switches according to the control signal. Specifically, the control module may control all of the sub-switches in the N-1 sets of N sub-switches to be turned on, or may control the N sub-switches in the N-1 sets of N sub-switches corresponding to the CPU module that is not in place to be turned off and control the N sub-switches in the sets corresponding to the CPU module that is in place to be turned on; further, the group of N subswitches corresponding to the CPU module in place and to be communicated may be fully turned on or partially turned on, and the present application is not particularly limited herein and is determined according to the UPI signal transmission performance requirement during the actual use process of the customer.

It should be further noted that, for the case that the ith CPU module is in place but temporarily does not wait for communication, the processing module 1 may control the ith controllable switch module 3 corresponding to the ith CPU module to be turned on, and when the control module in the ith controllable switch module 3 receives the control signal indicating on sent by the processing module 1, the control module may control on and off of each sub-switch in the N-1 groups of N sub-switches according to the control signal. Specifically, the control module may control all of the sub-switches in the N-1 sets of N sub-switches to be turned on, or may control the N sub-switches in the N-1 sets of N sub-switches corresponding to the CPU module that is not in place to be turned off and control the N sub-switches in the sets corresponding to the CPU module that is in place to be turned on.

It can be seen that in this way the control logic of the N controllable switch modules 3 can be implemented efficiently and reliably.

Referring to fig. 3, fig. 3 is a schematic structural diagram of another UPI signal interconnection apparatus provided in the present invention.

As a preferred embodiment, the N CPU modules are disposed on any two or more sides of four sides of the chassis of the N-way server;

In this embodiment, the inventor further considers that in the prior art, N CPUs are all disposed on a motherboard, which may cause an oversize of the motherboard, and the motherboard may be disposed on only one of four sides of a chassis of an N-way server, which may cause an oversize of the chassis. In this application, N CPU modules in the prior art are modularized, that is, for the ith CPU module, the CPU module includes a CPU, a power supply and a memory bank, N UPI signal transmission pins of the CPU are used as N UPI signal output ends of the CPU module to be connected with the connector 2 corresponding to the CPU module, an in-place output pin arranged on the CPU is used as an in-place output end of the CPU module, and the N modularized CPU modules can be arranged on any two or more sides of four sides of a chassis of an N-way server.

Specifically, still taking a four-way server as an example, as shown in fig. 3, the four-way server includes four CPU modules, which are CPU module 0, CPU module 1, CPU module 2, and CPU module 3, where CPU module 0 is placed on the left side of the chassis, CPU module 1 is placed on the upper side of the chassis, CPU module 2 is placed on the lower side of the chassis, and CPU module 3 is placed on the right side of the chassis.

It should be noted that, in order not to affect the signal transmission performance between the N CPU modules, the N CPU modules may be flexibly disposed on any two or more side surfaces of the four side surfaces of the chassis of the N-way server, but should not be too far apart.

Therefore, the flexibility of the structural design of the case of the N-path server can be improved in the mode, the size of the case is reduced to a certain extent, convenience and practicability are realized, and the use experience of customers is improved.

As a preferred embodiment, the processing module 1 is a CPLD.

In this embodiment, the processing module 1 may be a CPLD, N on-site detection ends of the CPLD are respectively connected to on-site transmission ends of the N connectors 2 in a one-to-one correspondence manner, N control ends of the CPLD are respectively connected to control ends of the N controllable switch modules 3 in a one-to-one correspondence manner, and the CPLD is configured to control the controllable switch modules 3 corresponding to the CPU modules that are on-site and are to be communicated to be turned on when it is determined that any two CPU modules in the CPU modules that are on-site and are on-site are to be communicated through the on-site transmission ends of the connectors 2, and control the controllable switch modules 3 corresponding to the CPU modules that are not on-site to be turned off when it is determined that the CPU modules are not on-site.

Therefore, the control logic of the processing module 1 in the application can be realized in the mode, the integration level of the CPLD is high, the reliability is high, and developers can flexibly design the control logic according to actual needs.

As a preferred embodiment, the storage module on the N-way server is arranged outside the chassis of the N-way server;

the N CPU modules are connected with the storage module.

In this embodiment, in order to further reduce the size of the chassis, in this application, the storage module originally disposed inside the chassis of the N-way server is disposed outside the chassis, and the N CPU modules are connected to the storage module to implement data transmission.

The CPU module and the memory module may be connected by a high-speed connector capable of transmitting a high-speed signal, and the present application is not limited thereto.

Therefore, the size of the case can be further reduced by the mode, and the placement space of the case can be flexibly used according to the size of the N-path server required by the client to meet the requirements of different clients.

As a preferred embodiment, the system further comprises a prompt module;

the prompting module is connected with the processing module 1 and is used for prompting the in-place conditions of the N CPU modules judged by the processing module 1.

In the application, the UPI signal interconnection device further comprises a prompt module, the prompt module can prompt the in-place situation of the N CPU modules according to the in-place situation of the N CPU modules judged by the processing module 1, the display mode is more visual, and developers can conveniently know the configuration situation of the N CPU modules and perform follow-up actions.

As a preferred embodiment, the prompting module includes indicator lights corresponding to the N CPU modules one to one, and is configured to light up when the processing module 1 determines that the ith CPU module is in place, and light off when the processing module 1 determines that the ith CPU module is not in place.

In the application, the prompting module can be indicator lights corresponding to the N CPU modules one to one, and when the processing module 1 determines that the ith CPU module is in place, the indicator light corresponding to the ith CPU module is lighted; when the processing module 1 judges that the ith CPU module is not in place, the indicator lamp corresponding to the ith CPU module is turned off, the display mode is more visual and reliable, and developers can conveniently know the configuration conditions of the N CPU modules and perform subsequent actions.

As a preferred embodiment, the board card is a multilayer board card;

when there are N first UPI signal lines between two controllable switch modules 3 crossing N second UPI signal lines between any other two controllable switch modules 3, the crossing N first UPI signal lines and N second UPI signal lines are disposed on different signal layers of the board card.

In this embodiment, it is considered that in the prior art, a plurality of CPUs and the UPI signals thereof are wired on one motherboard, and the motherboard further includes devices for implementing other functions, which results in that the devices are difficult to place and difficult to wire. And the topological structure that the UPI signal of a plurality of CPUs can be walked is limited, and the routing of other devices on the mainboard and the routing of the UPI signal of a plurality of CPUs are easy to produce alternately, and the routing of the UPI signal of a plurality of CPUs also is likely to produce alternately when the number of CPUs is large, and does not meet the UPI signal transmission requirement, thereby influencing the data transmission performance and causing the high-speed signal interconnection bottleneck. To solve the above technical problem, the prior art generally adopts increasing the number of layers of the motherboard or moving other circuits on the motherboard to a relatively far position. However, the manner of increasing the number of layers of the main board is limited by the size of the main board card and the upper limit value of the number of layers of the main board which can be increased, and the design cost is increased; when the number of the CPUs is large, the possibility of crossing the wires is still existed by removing other circuits on the mainboard, and the related performance of the moved circuits is sacrificed. The utility model provides a UPI signal interconnection device includes the integrated circuit board be multilayer integrated circuit board, when having N first UPI signal line between two controllable switch modules 3 and N second UPI signal line between other arbitrary two controllable switch modules 3 to intersect, will intersect N first UPI signal line and N second UPI signal line set up in the different signal layers of integrated circuit board, can solve among the prior art UPI signal and walk the criss-cross problem of line.

Specifically, still taking the four-way server as an example, please further refer to fig. 2, there are 4 UPI signal lines between the controllable switch module 3 at the upper left corner and the controllable switch module 3 at the lower right corner, i.e., UPI _03_0, UPI _03_1, UPI _03_2, and UPI _03_3, and there are 4 UPI signal lines between the controllable switch module 3 at the upper right corner and the controllable switch module 3 at the lower left corner, i.e., UPI _12_0, UPI _12_1, UPI _12_2, and UPI _12_3, and if UPI _03_ [0-3] and UPI _12_ [0-3] are disposed on the same signal layer of the board, the UPI _03_ [0-3] and UPI _12_ [0-3] of the crossed traces are disposed on different signal layers of the board.

Therefore, the problem of crossing UPI wiring in the prior art is effectively solved through the mode, the number of layers of the mainboard does not need to be increased or other circuits on the mainboard do not need to be moved to relatively far positions, wiring problems of devices on the mainboard are optimized, and stability of connecting circuits is improved.

The invention also provides an N-path server which comprises N CPU modules, a mainboard and the UPI signal interconnection device, wherein the UPI signal interconnection device is arranged on the mainboard.

For the introduction of the N-way server provided in the present invention, please refer to the above embodiment of the UPI signal interconnection apparatus, which is not described herein again.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A UPI signal interconnection device is characterized by being applied to an N-path server, wherein the N-path server comprises N CPU modules, a mainboard and a UPI signal interconnection device arranged on the mainboard; the UPI signal interconnection device comprises a board card, and a processing module, N connectors and N controllable switch modules which are arranged on the board card, wherein N is 1 or an even number greater than 1;

2. The UPI signal interconnect device of claim 1, wherein the ith controllable switch module comprises N-1 groups of N sub-switches and a control module connected to control terminals of the N-1 groups of N sub-switches;

3. The UPI signal interconnection device according to claim 1, wherein N of the CPU modules are disposed on any two or more of four sides of the chassis of the N-way server;

4. The UPI signal interconnect device of claim 1, wherein the processing module is a CPLD.

5. The UPI signal interconnection device of claim 1, wherein the memory module on the N-way server is disposed outside of the chassis of the N-way server;

and the N CPU modules are connected with the storage module.

6. The UPI signal interconnection apparatus of claim 1, further comprising a prompt module;

7. The UPI signal interconnect device according to claim 6, wherein said prompt module includes indicator lights in one-to-one correspondence with N of said CPU modules for illuminating when said processing module determines that the ith said CPU module is in place and for extinguishing when the processing module determines that the ith said CPU module is not in place.

8. The UPI signal interconnect device according to any of claims 1 to 7, wherein the board is a multi-layer board;

9. An N-way server, comprising N CPU modules and a motherboard, and further comprising the UPI signal interconnection apparatus according to any one of claims 1 to 8, the UPI signal interconnection apparatus being disposed on the motherboard.