CN116736677A - Synchronous metronome, data acquisition synchronization device and double-machine hot standby system - Google Patents

Synchronous metronome, data acquisition synchronization device and double-machine hot standby system Download PDF

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Publication number
CN116736677A
CN116736677A CN202310283457.7A CN202310283457A CN116736677A CN 116736677 A CN116736677 A CN 116736677A CN 202310283457 A CN202310283457 A CN 202310283457A CN 116736677 A CN116736677 A CN 116736677A
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signal
clock
synchronous
frame
metronome
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李伟
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Alibaba China Co Ltd
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Alibaba China Co Ltd
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F5/00—Apparatus for producing preselected time intervals for use as timing standards
    • G04F5/02—Metronomes
    • G04F5/025—Electronic metronomes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware

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  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The application discloses a synchronous metronome, a data acquisition and synchronization device and a double-machine hot standby system, and relates to the technical field of double-machine hot standby, wherein the synchronous metronome comprises a frame signal clock generation module, a signal detection module and a frame synchronous signal generation module, wherein the frame signal clock generation module is used for carrying out frequency mixing processing on a first clock signal and a second clock signal to obtain a frequency mixing signal, and processing the frequency mixing signal into a first frame signal clock with preset frequency; the signal detection module is used for outputting a synchronous starting signal when the second clock signal and the first clock signal are detected; the frame synchronization signal generation module is used for generating a frame synchronization pulse signal according to a first frame signal clock under the condition that the synchronization start signal is detected. The application solves the problems that in the high availability scheme of the double-machine, the real-time precision of the software implementation depends on an operating system and the consistency of the working beats of the double-machine is difficult to ensure.

Description

Synchronous metronome, data acquisition synchronization device and double-machine hot standby system
Technical Field
The application relates to the technical field of dual-computer hot standby, in particular to a synchronous metronome, a data acquisition synchronization device and a dual-computer hot standby system.
Background
This section is intended to provide a background or context to the embodiments of the application that are recited in the claims. It is not admitted to be prior art by inclusion of this description in this section.
The dual-computer hot standby scheme is required to be applied to scenes such as edge calculation, edge data acquisition and the like in the industrial field, and the cost efficiency is realized while the acquisition, the distribution and the storage of high-availability data are realized. In the industry of edge computing, the service synchronization is somewhat implemented by software, such as: the distributed lock realizes synchronization of multiple machine service states through software, but the real-time precision of the software implementation depends on an operating system, for example, a linux operating system cannot guarantee real-time of signal synchronization after IO load is increased, the synchronization precision can be reduced, and consistency of working beats of a double machine is difficult to ensure.
Disclosure of Invention
The embodiment of the application provides a synchronous metronome, a data acquisition and synchronization device and a dual-machine hot standby system, which at least solve the problems that in a dual-machine high-availability scheme in the prior art, the real-time precision realized by software depends on an operating system, and the consistency of the working beats of the dual-machine is difficult to ensure.
According to an aspect of the present application, there is also provided a synchronous metronome including:
the frame signal clock generation module is used for carrying out frequency mixing processing on a first clock signal and a second clock signal to obtain a frequency mixing signal, processing the frequency mixing signal into a first frame signal clock with preset frequency, wherein the first clock signal is a clock signal generated by the synchronous metronome, and the second clock signal is a clock signal generated by another synchronous metronome;
the signal detection module is used for outputting a synchronous starting signal when the second clock signal and the first clock signal are detected;
and the frame synchronization signal generation module is used for generating a frame synchronization pulse signal according to the first frame signal clock under the condition that the synchronization start signal is detected.
In some of these embodiments, the synchronous metronome further comprises:
and the signal gating circuit is used for inputting the first frame signal clock into the frame synchronous signal generating module when the signal detecting module detects the second clock signal.
In some embodiments, the signal detection module is further configured to process the first clock signal into a second frame signal clock with a preset frequency when the second clock signal is not detected but the first clock signal is detected, and the signal gating circuit is further configured to input the second frame signal clock into the frame synchronization signal generation module, so that the frame synchronization signal generation module generates the frame synchronization pulse signal according to the second frame signal clock.
In some of these embodiments, the frame signal clock generation module comprises:
the mixer is used for receiving the first clock signal and the second clock signal, and carrying out mixing processing on the first clock signal and the second clock signal to obtain a mixed signal, wherein the mixed signal comprises a high-frequency signal and a low-frequency signal;
the input end of the signal processing unit is connected with the output end of the mixer, the output end of the signal processing unit is connected with the input end of the frame synchronization signal generation module, and the signal processing unit is used for filtering the low-frequency signal, processing the high-frequency signal into the first frame signal clock with the preset frequency and inputting the first frame signal clock into the frame synchronization signal generation module.
In some of these embodiments, the signal processing unit comprises:
the input end of the high-pass filter is connected with the output end of the mixer and is used for filtering the low-frequency signal and outputting the high-frequency signal;
the input end of the frequency dividing circuit is connected with the output end of the high-pass filter, the output end of the frequency dividing circuit is connected with the input end of the frame synchronizing signal generating module, and the frequency dividing circuit is used for processing the high-frequency signal into the first frame signal clock with the preset frequency and inputting the first frame signal clock into the frame synchronizing signal generating module.
In some of these embodiments, the frequency dividing circuit includes:
the input end of the first frequency divider is connected with the output end of the high-pass filter, and the first frequency divider is used for processing the frequency of the high-frequency signal to be the same as the frequency of the first clock signal;
the input end of the second frequency divider is connected with the output end of the first frequency divider, the output end of the second frequency divider is connected with the input end of the frame synchronizing signal generating module, and the second frequency divider is used for processing the high-frequency signal divided by the first frequency divider into the first frame signal clock with preset frequency and inputting the first frame signal clock into the frame synchronizing signal generating module.
In some of these embodiments, the synchronous metronome further comprises:
and the synchronous signal output module is used for inputting the first clock signal into the other synchronous metronome to serve as a second clock signal of the other synchronous metronome.
In some of these embodiments, the signal detection module comprises:
an internal signal detector for outputting a first detection signal when detecting the first clock signal;
An external signal detector for outputting a second detection signal when the second clock signal is detected;
and the output ends of the external signal detector and the internal signal detector are respectively connected with the input end of the AND gate, the output end of the AND gate is connected with the input end of the frame synchronization signal generation module, and the AND gate inputs the synchronization start signal to the frame synchronization signal generation module when receiving the first detection signal and the second detection signal.
According to another aspect of the present application, there is also provided a data acquisition synchronization apparatus including:
a first synchronous metronome;
a second synchronous metronome;
the first synchronous metronome and the second synchronous metronome are structured as the synchronous metronome;
the first synchronous metronome is connected with the second synchronous metronome, a first clock signal of the first synchronous metronome is sent to the second synchronous metronome to serve as a second clock signal of the second synchronous metronome, and the first synchronous metronome receives the first clock signal from the second synchronous metronome to serve as the second clock signal of the first synchronous metronome.
According to another aspect of the present application, there is also provided a dual hot standby system, including:
a first server;
a second server;
a data acquisition synchronization device;
the first synchronous metronome in the data acquisition and synchronization device is connected with the first server, the second synchronous metronome is connected with the second server, and the first server and the second server ensure synchronous service operation through the frame synchronous pulse signals generated by the data acquisition and synchronization device.
According to the synchronous metronome provided by the embodiment of the application, the hardware calculation module is adopted to generate the frame synchronous pulse signal by realizing the fusion calculation of the double-machine synchronous clock signal, the real-time precision does not need to depend on an operating system, the consistency of the working beats of the double-machine is ensured, and a third party carrier is not required to be introduced when the synchronous metronome is used as the peripheral equipment of the double-machine edge equipment, so that the cost and the system complexity are reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
fig. 1 is a schematic structural diagram of a synchronous metronome according to an embodiment of the present application;
Fig. 2 is a schematic structural diagram of a frame synchronization signal generating module according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a data acquisition synchronization device according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an embodiment of an external signal detector and an internal signal detector according to the present application;
fig. 5 is a schematic structural diagram of a dual hot standby system according to an embodiment of the present application.
In the figure:
10. a frame signal clock generation module; 11. a mixer; 12. a high pass filter; 13. a first frequency divider; 14. a selector switch; 15. a second frequency divider; 16. a local oscillator clock; 17. a third frequency divider; 20. a signal detection module; 21. an internal signal detector; 22. an external signal detector; 23. an AND gate circuit; 30. a frame synchronization signal generation module; 31. a register; 32. a counter; 33. a comparator; 34. a trigger; 35. or gate circuit; 40. a synchronous signal output module; 101. a first synchronous metronome; 102. a second synchronous metronome; 103. a first server; 104. and a second server.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order other than that illustrated herein.
A first embodiment of the present invention provides a synchronous metronome including a frame signal clock generation module 10, a signal detection module 20, and a frame synchronization signal generation module 30, as shown in fig. 1. The frame signal clock generation module 10 is configured to perform mixing processing on the first clock signal and the second clock signal to obtain a mixed signal, and process the mixed signal into a first frame signal clock with a preset frequency. As shown in fig. 1, the first clock signal is a clock signal generated by the synchronous metronome itself (i.e., an internal clock signal as shown in fig. 1), and the second clock signal is a clock signal generated by another synchronous metronome (i.e., an external clock signal as shown in fig. 1). The signal detection module 20 is configured to output a synchronization start signal when the second clock signal and the first clock signal are detected. The frame synchronization signal generation module 30 is configured to generate a frame synchronization pulse signal according to a first frame signal clock when the synchronization start signal is detected.
In the embodiment of the invention, when the second clock signal and the first clock signal coexist, the signal detection module 20 outputs a synchronization start signal, and the frame synchronization signal generation module 30 generates a frame synchronization pulse signal according to the first frame signal clock obtained by fusion calculation of the frame signal clock generation module 10 when detecting the synchronization start signal. Since the frame synchronization pulse Signal (i.e., signal shown in fig. 1) is generated by the frame Signal clock calculated from the internal and external clock signals of the two synchronous metronomes, the frame Signal clocks of the two synchronous metronomes are completely identical at this time, and there is no large accumulated error even if the two synchronous metronomes are operated for a long time.
Thus, the synchronous metronome provided by the embodiment of the present invention adopts the hardware calculation module (i.e. the frame signal clock generation module 10, the signal detection module 20, the frame synchronization signal generation module 30, etc.) to generate the frame synchronization pulse signal by implementing the fusion calculation of the two-machine synchronization clock signals. The real-time precision does not need to depend on an operating system, the consistency of working beats of the double-machine is ensured, and when the double-machine peripheral equipment is used as a peripheral equipment of the double-machine peripheral equipment, a third party carrier is not required to be introduced, so that the cost and the complexity of the system are reduced.
Because the existing software implementation schemes such as the distributed lock and the like cannot solve the abnormal situation of the brain fracture at the moment after the double-machine chain breakage, the existing software implementation schemes need to be manually involved in recovery, otherwise, the frame synchronization signal is out of step. In this regard, when the synchronous metronome provided in the embodiment of the present invention is used as a peripheral device of the dual-edge device, the synchronous metronome further includes a signal gating circuit, where the signal gating circuit is configured to clock the first frame signal into the frame synchronization signal generating module 30 when the signal detecting module 20 detects the second clock signal. The signal detection module 20 is further configured to process the first clock signal into a second frame signal clock with a preset frequency when the second clock signal is not detected, but the first clock signal is detected, that is, when the dual-machine chain breaking occurs, where the frame signal clock generation module 10 is further configured to input the second frame signal clock into the frame synchronization signal generation module 30, so that the frame synchronization signal generation module 30 generates a frame synchronization pulse signal according to the second frame signal clock.
Thus, the signal gating circuit provided by the embodiment of the invention can provide the frame signal clock generating module 10 with the first frame signal clock obtained by fusion calculation to the frame synchronizing signal generating module 30 under the condition that the dual-machine link is normal, so that the frame synchronizing signal generating module 30 generates the frame synchronizing pulse signal which ensures the consistent working beat of the dual-machine. In the case of abnormal double-machine linkage (namely, brain fracture generation), each synchronous metronome can be ensured to provide a second frame signal clock based on the first clock signal, and the second frame signal clock is used for enabling the frame synchronous signal generation module 30 to generate a frame synchronous pulse signal with an error within a control range, so that the problem of double-machine brain fracture is avoided, namely, the synchronous metronome can still continue to operate under the condition of double-machine chain breakage, and the error is controllable.
The frame signal clock generation module 10 provided by the embodiment of the invention comprises a mixer 11 and a signal processing unit. The mixer 11 is configured to receive the first clock signal and the second clock signal, and perform mixing processing on the first clock signal and the second clock signal to obtain a mixed signal, where the mixed signal includes a high frequency signal and a low frequency signal. Specifically, the frame signal clock generating module 10 further includes a local oscillator clock 16 and a third frequency divider 17, where the local oscillator clock 16 is used to generate an original clock signal, the original clock signal is subjected to frequency division processing by the third frequency divider 17 to obtain a first clock signal, and the second clock signal (i.e. the external clock signal shown in fig. 1) is obtained by generating the local oscillator clock 16 and the third frequency divider 17 of another synchronous metronome. The mixer 11 performs the mixing processing of the first clock signal and the second clock signal as follows:
first clock signal (with s 1 Indicated) is: s is(s) 1 ＝cos(ω 1 t+θ 1 ) Wherein omega 1 Representing a first clock signal s 1 Frequency of θ 1 Representing a first clock signal s 1 Is used to determine the initial phase of the phase.
Second clock signal (with s 2 Indicated) is:
s 2 ＝cos(ω 2 t+θ 2 ) Wherein omega 2 Representing the second clock signal s 2 Frequency of θ 2 Representing the second clock signal s 2 Is used to determine the initial phase of the phase.
The mixing process formula is as follows:
s 1 ×s 2 ＝f 1 +f 2 wherein f 1 Is a high frequency signal f 2 Is a low frequency signal, i.e. the mixed signal of the first clock signal and the second clock signal corresponds to f 1 And f 2 A sum of two signals, wherein:
f 1 ＝1/2cos((ω 1 +ω 2 )t+θ 1 +θ 2 )。
f 2 ＝1/2cos((ω 1 -ω 2 )t+θ 1 -θ 2 )。
after mixing, two signals, namely a high frequency signal f, are obtained 1 And a low frequency signal f 2 . Because the parameters of the local oscillator clocks 16 of the two synchronous metronomes which are generally selected to be synchronous with each other are basically consistent, the first clock signal is the signal obtained by dividing the local oscillator clock 16 by the third frequency divider 17, the second clock signal is the signal obtained by dividing the local oscillator clock 16 of the opposite synchronous metronome by the third frequency divider 17, and the frequencies of the two signals have smaller device errors, so that the frequencies omega of the first clock signal and the second clock signal 1 ≈ω 2 Due to omega 1 About equal to omega 2 For ease of calculation, embodiments of the present invention will be described herein with ω 1 And omega 2 The values of (a) are denoted by ω, so the high frequency signal f 1 Is about 2 omega, a low frequency signal f 2 The frequency is about 0. If the signal detection module 20 does not detect the second clock signal, the high frequency signal f 1 The frequency is about ω, the low frequency signal f 2 The frequency is 0.
It can be seen that f calculated above 2 Is calculated by (a) is calculated by (b)If f2 is also verified to be a low-frequency signal, the low-frequency signal f is obtained by processing the calculation basis provided for the subsequent calculation of the first frame signal clock or the second frame signal clock 2 Filtering. In this regard, the input end of the signal processing unit is connected to the output end of the mixer 11, the output end is connected to the input end of the frame synchronization signal generating module 30, and the signal processing unit is configured to filter the low frequency signal, process the high frequency signal into a first frame signal clock with a preset frequency, and input the first frame signal clock into the frame synchronization signal generating module 30. The frame synchronization signal generating module 30 can generate a frame synchronization pulse signal according to the first frame signal clock under the condition of detecting the synchronization start signal, so as to ensure the consistency of the double-machine synchronization.
Wherein the signal processing unit comprises a high pass filter 12 and a frequency dividing circuit. The input end of the high-pass filter 12 is connected with the output end of the mixer 11, and is used for filtering low-frequency signals and outputting high-frequency signals. The input end of the frequency dividing circuit is connected with the output end of the high-pass filter 12, the output end of the frequency dividing circuit is connected with the input end of the frame synchronization signal generating module 30, and the frequency dividing circuit is used for processing the high-frequency signal into a first frame signal clock with a preset frequency and inputting the first frame signal clock into the frame synchronization signal generating module 30. Filtering the low frequency signal f by the high pass filter 12 2 Only the high frequency signal f is retained 1 . Can ensure two synchronous metronome high-frequency signals f 1 The high consistency of the synchronous beats of the two machines is further ensured.
Specifically, the frequency dividing circuit provided by the embodiment of the invention comprises a first frequency divider 13 and a second frequency divider 15. The input of the first frequency divider 13 is connected to the output of the high pass filter 12, and the first frequency divider 13 is configured to process the frequency of the high frequency signal to be the same as the frequency of the first clock signal. Specifically, the first frequency divider 13 is a frequency divider, mainly because of the high frequency signal f 1 Is substantially twice the frequency of the internal and external clock signals (i.e. the high frequency signal f 1 About 2ω), the frequency of the high frequency signal can be processed to be the same (i.e., ω) as the frequency of the first clock signal by the divide-by-two divider. The input of the second frequency divider 15 is connected to the first frequency divider 13The output end is connected, the output end is connected with the input end of the frame synchronization signal generation module 30, and the second frequency divider 15 is used for processing the high-frequency signal divided by the first frequency divider 13 into a first frame signal clock with a preset frequency, and inputting the first frame signal clock into the frame synchronization signal generation module 30. I.e. the required first frame Signal clock is divided by the second frequency divider 15, the frequency of which can be set between Kilohertz (KHZ) level and Megahertz (MHZ) level, the first frame Signal clocks of the two synchronous metronomes (Signal as shown in fig. 1) remaining identical.
In the embodiment of the present invention, the signal gating circuit is a selector switch 14 (Mux shown in fig. 1) connected between the first frequency divider 13 and the second frequency divider 15, and the selector switch 14 is used to enable the synchronous metronomes to independently generate the frame synchronization pulse signals only through the local oscillation clock 16 when the synchronization lines of the two synchronous metronomes are disconnected.
Specifically, as shown in fig. 1, the routing signal of the selector switch 14 is generated by monitoring the second clock signal, and when the signal detection module 20 detects that the second clock signal is valid, the selector switch 14 selects the 0-way on, that is, selects the high-frequency signal that will be mixed by the mixer 11 and then output through the first frequency divider 13, so that the second frequency divider 15 is used to process the high-frequency signal divided by the second frequency divider 15 into the first frame signal clock with the preset frequency. At this time, since the frame synchronization pulse signal is generated by the first frame signal clock calculated by the internal clock signal and the external clock signal of the two synchronous metronomes, the frame signal clocks of the two synchronous metronomes are completely identical, and the device errors of the local oscillator clocks 16 of the two synchronous metronomes are eliminated, and even if the synchronous metronomes run for a long time, large accumulated errors do not exist. If the signal detection module 20 does not detect the second clock signal, the selector switch 14 selects 1-way conduction, i.e. the high-frequency signal of the first clock signal obtained by the synchronous metronome through the local oscillator clock 16 and the third frequency divider 17 is directly input into the second frequency divider 15, and the second frame signal clock processed by the second frequency divider 15 into the preset frequency is input into the frame synchronization signal generation module 30, so that the frame synchronization signal generation module 30 generates the frame synchronization pulse signal according to the second frame signal clock, i.e. when the two-machine chain is broken, the synchronous metronome can also independently generate the frame synchronization pulse signal, thereby the synchronous metronome (i.e. the frame synchronization pulse signal) can still be stably output without artificial participation for a long time after the two-machine chain is broken.
In the embodiment of the present invention, the synchronous metronome further includes a synchronous signal output module 40, and the synchronous signal output module 40 is configured to input the first clock signal into another synchronous metronome as the second clock signal of the other synchronous metronome. Therefore, the frame synchronization pulse signals are generated by the first frame signal clock obtained by calculating the internal clock signals and the external clock signals of the two synchronous metronomes, the frame signal clocks of the two synchronous metronomes are completely consistent, and even if the frame synchronization pulse signals run for a long time, large accumulated errors do not exist.
In the embodiment of the present invention, the signal detection block 20 includes an internal signal detector 21, an external signal detector 22, AND an AND circuit 23 (AND shown in fig. 1). The internal signal detector 21 is configured to output a first detection signal when detecting the first clock signal. The external signal detector 22 is configured to output a second detection signal when the second clock signal is detected. The output terminals of the external signal detector 22 and the internal signal detector 21 are respectively connected with the input terminal of the and circuit 23, the output terminal of the and circuit 23 is connected with the input terminal of the frame synchronization signal generating module 30, and when the and circuit 23 receives the first detection signal and the second detection signal, a synchronization start signal is input to the frame synchronization signal generating module 30, and the frame synchronization signal generating module 30 is triggered to work by the synchronization start signal to generate a frame synchronization pulse signal.
As shown in fig. 2, the frame synchronization signal generation module 30 in the embodiment of the present invention includes a register 31, a counter 32, a comparator 33, and a trigger 34. Wherein the register 31 stores a synchronization period parameter set by a user. An input of the counter 32 is connected to an output of the frame signal clock generation module for counting the number of clocks of the received first frame signal clock or second frame signal clock. The input end of the comparator 33 is connected to the output ends of the register 31 and the counter 32, and is used for judging whether the clock number calculated by the counter 32 is equal to the synchronization period parameter, if yes, outputting a high level, otherwise outputting a low level. The input of the flip-flop 34 is connected to the output of the comparator 33 for outputting the frame sync pulse signal when a high level is received, otherwise not outputting the frame sync pulse signal. So that the frame synchronization signal generating module 30 periodically outputs a frame synchronization pulse signal, and can output the sequence number data of the frame synchronization pulse signal along with the frame synchronization pulse signal, and the frame synchronization pulse signals of the two frame synchronization metronomes keep the consistency of time sequences when the two frame synchronization metronomes synchronize, and the sequence numbers data of the frame synchronization pulse signals also keep the consistency.
In addition, the frame synchronization signal generating module 30 further includes an or circuit 35, and one of input terminals of the or circuit 35 is connected to the output terminal of the signal detecting module, for receiving the synchronization start signal. The output of the or circuit 35 is connected to the RST (reset) terminals of the counter 32 and the comparator 33, which can trigger the counter 32 and the comparator 33 to restart counting and comparing when receiving the high level of the or circuit 35. The or circuit 35 outputs the high-level start counter 32 and the comparator 33 when receiving the synchronization start signal, which is a rising edge trigger signal, and the signal detection module 20 outputs a synchronization start signal when both the first clock signal and the second clock signal are active, and the frame synchronization signal generation module 30 starts outputting the frame synchronization pulse signal. The other input terminal of the or circuit 35 is further configured to receive an external signal (the external signal is a trigger signal that is manually input), and when the or circuit 35 receives the external signal, it outputs a high level trigger counter 32 and a comparator 33 to restart the count comparison, that is, the trigger synchronization of the trigger 34 in the frame synchronization signal generating module is achieved by manually inputting a signal and simultaneously notifying the counter 32 and the comparator 33 of the zero clearing count.
Finally, it can be seen that, according to the synchronous metronome provided by the embodiment of the present invention, the frame signal clock generating module 10 can calculate the first clock signal and the second clock signal to obtain the first frame signal clock or the second frame signal clock under the condition of double-broken chain. Upon detecting the first clock signal and the second clock signal, the output synchronization start signal triggers the frame synchronization signal generation module 30 to periodically output a frame synchronization pulse signal according to the first frame signal clock or the second frame signal clock. The synchronous metronome is a hardware device, so that the problems of increased cost and system complexity caused by introducing a third-party carrier can be avoided when the synchronous metronome is used as a peripheral of the dual-machine edge equipment, and compared with the existing signal generator which can only be used by a single machine, the synchronous metronome solves the problem of synchronous output of dual-machine interconnection. The first clock signal generated by the frame signal clock generating module 10 is a high-speed signal obtained by adopting the local oscillator clock 16 and the third frequency divider 17 to generate and process, and the frequency of the local oscillator clock 16 can range from gigahertz (GHz) to hundreds of Megahertz (MHZ), so that the real-time performance and high precision of the frame synchronization pulse signal are ensured. The hardware calculation module is used for generating a frame synchronization pulse signal by realizing the fusion calculation of the double-machine synchronization clock signals, so that the synchronization of beat signals is ensured.
In addition, the signal detection module 20 determines the validity of the duplex link, and the high precision of the high-frequency clock ensures real-time detection of the broken link condition, so that the signal gating circuit realizes rapid switching of the frame signal clock, thereby, the frame synchronization signal generation module 30 realized based on the high-speed signal can ensure that each synchronous metronome can provide the frame signal clock based on the local oscillator clock 16 even in the case of the disconnection of the duplex link, and is used for generating the frame synchronization pulse signal with the error within the control range.
The second embodiment of the present invention further provides a data acquisition synchronization device, as shown in fig. 3, where the data acquisition synchronization device includes a first synchronous metronome 101 and a second synchronous metronome 102, and the structures of the first synchronous metronome 101 and the second synchronous metronome 102 are the synchronous metronomes provided by the first embodiment of the present invention. The first synchronous metronome 101 and the second synchronous metronome 102 are connected, the first clock signal of the first synchronous metronome 101 is sent to the second synchronous metronome 102 to serve as the second clock signal of the second synchronous metronome 102, and the first synchronous metronome 101 receives the first clock signal from the second synchronous metronome 102 to serve as the second clock signal of the first synchronous metronome 101. Specifically, the first synchronous metronome 101 and the second synchronous metronome 102 are connected through the synchronous signal output module 40 to mutually receive the first clock signal of the other side.
As can be seen from the structural composition of the synchronous metronome provided in connection with the first embodiment of the present invention, the data acquisition synchronization device provided in the embodiment of the present invention is a hardware device that can be used for interconnection of two computers, and the signal synchronization of the first synchronous metronome 101 and the second synchronous metronome 102 is maintained by the interconnection synchronization signal. The clock signals of the two synchronous metronomes have the same frequency, and each synchronous metronome can realize signal synchronization by adding the first clock signal of the synchronous metronome to the frame signal clock calculated by the first clock signal of the other synchronous metronome (for example, for the first synchronous metronome 101, the first clock signal of the second synchronous metronome 102 is the second clock signal of the first synchronous metronome 101). Meanwhile, the user sets a frame synchronization signal period (i.e., a synchronization period parameter) in the frame synchronization signal generation module 30, so that the frame synchronization signal generation module 30 periodically outputs a frame synchronization pulse signal (signal) based on a frame signal clock. In the field of industrial data sampling, the set synchronization period parameter is short in millisecond (ms) level and long in second level. Each of the synchronous metronomes continuously outputs a frame synchronization pulse signal in accordance with its own first clock signal even if the first synchronous metronome 101 and the second synchronous metronome 102 are disconnected based on the design of the signal gating circuit, and there is no large accumulated error even if it is operated for a long period of time.
The generation of the synchronous clock (i.e. the frame signal clock) in the embodiment of the present invention is mainly achieved by mixing the first clock signal and the second clock signal, and the local oscillator clock 16 and the third frequency divider 17 of the two synchronous metronomes are set to the same parameters, so as to ensure that the second clock signal and the first clock signal are substantially consistent. The steps of mixing the first clock signal and the second clock signal by the mixer 11 are as follows:
first clock signal (with s 1 Indicated) is: s is(s) 1 ＝cos(ω 1 t+θ 1 ) Wherein omega 1 Representing a first clock signal s 1 Frequency of θ 1 Representing a first clock signal s 1 Is used to determine the initial phase of the phase.
Second clock signal (with s 2 Indicated) is:
s 2 ＝cos(ω 2 t+θ 2 ) Wherein omega 2 Representing the second clock signal s 2 Frequency of θ 2 Representing the second clock signal s 2 Is used to determine the initial phase of the phase.
The mixing process formula is as follows:
s 1 ×s 2 ＝f 1 +f 2 wherein f 1 Is a high frequency signal f 2 Is a low frequency signal, i.e. the mixed signal of the first clock signal and the second clock signal corresponds to f 1 And f 2 A sum of two signals, wherein:
f 1 ＝1/2cos((ω 1 +ω 2 )t+θ 1 +θ 2 )。
f 2 ＝1/2cos((ω 1 -ω 2 )t+θ 1 -θ 2 )。
after mixing, two signals, namely a high frequency signal f, are obtained 1 And a low frequency signal f 2 . Because the parameters of the local oscillator clocks 16 of the two synchronous metronomes which are generally selected to be synchronous with each other are basically consistent, the first clock signal is the signal obtained by dividing the local oscillator clock 16 by the third frequency divider 17, the second clock signal is the signal obtained by dividing the local oscillator clock 16 of the opposite synchronous metronome by the third frequency divider 17, and the frequencies of the two signals have smaller device errors, so that the frequencies omega of the first clock signal and the second clock signal 1 ≈ω 2 Due to omega 1 About equal to omega 2 For ease of calculation, embodiments of the present invention will be described herein with ω 1 And omega 2 The values of (a) are denoted by ω, so the high frequency signal f 1 Is about 2 omega, a low frequency signal f 2 The frequency is about 0. If the signal detection module 20 does not detect the second clock signal, the high frequency signal f 1 The frequency is about ω, the low frequency signal f 2 The frequency is 0.
It can be seen that f calculated above 2 Also verifies that f2 is a low frequency signal for subsequent computation of the first frame signal clock orThe second frame signal clock provides the calculation basis, and when the first frame signal clock or the second frame signal clock is obtained through processing, the low-frequency signal f 2 Filtering. For this purpose, the synchronous metronomes filter out the low-frequency signal f by means of a high-pass filter 12 2 Only the high frequency signal f is retained 1 Can ensure two synchronous metronome high-frequency signals f 1 Is a high degree of consistency. Specifically, the input terminal of the first frequency divider 13 of each synchronous metronome is connected to the output terminal of the high-pass filter 12, and the first frequency divider 13 processes the frequency of the high-frequency signal to be the same as the frequency of the first clock signal. The first frequency divider 13 is a frequency divider, mainly because of the high frequency signal f 1 Is substantially twice the frequency of the internal and external clock signals (i.e. the high frequency signal f 1 About 2ω), the frequency of the high frequency signal can be processed to be the same (i.e., ω) as the frequency of the first clock signal by the divide-by-two divider. The input end of the second frequency divider 15 is connected with the output end of the signal gating circuit, the input end of the signal gating circuit is connected with the output end of the first frequency divider 13, the output end of the second frequency divider 15 is connected with the input end of the frame synchronization signal generation module 30, the second frequency divider 15 processes the high-frequency signal divided by the first frequency divider 13 into a first frame signal clock with a preset frequency, and the first frame signal clock is input into the frame synchronization signal generation module 30. I.e. the required first frame Signal clock is divided by the second frequency divider 15, the frequency of the first frame Signal clock is typically between a few hundred K and a few M, the first frame Signal clocks of the two synchronous metronomes (Signal as shown in fig. 1) remain identical.
In the embodiment of the present invention, the signal gating circuit is a selector switch 14, and the selector switch 14 is used to enable the synchronous metronomes to independently generate the frame synchronization pulse signal only through the local oscillator clock 16 when the synchronous lines of the two synchronous metronomes are disconnected. Specifically, as shown in fig. 1, the routing signal of the selector switch 14 is generated by monitoring the second clock signal, and when the signal detection module 20 detects that the second clock signal is valid, the selector switch 14 selects the 0-way on, that is, selects the high-frequency signal that will be mixed by the mixer 11 and then output through the first frequency divider 13, so that the second frequency divider 15 is used to process the high-frequency signal divided by the second frequency divider 15 into the first frame signal clock with the preset frequency. At this time, since the frame synchronization pulse signal is generated by the first frame signal clock calculated by the internal clock signal and the external clock signal of the two synchronous metronomes, the frame signal clocks of the two synchronous metronomes are completely identical, and the device errors of the local oscillator clocks 16 of the two synchronous metronomes are eliminated, and even if the synchronous metronomes run for a long time, large accumulated errors do not exist.
If the signal detection module 20 does not detect the second clock signal, the selector switch 14 selects 1-way conduction, i.e. the high-frequency signal of the first clock signal obtained by the synchronous metronome through the local oscillator clock 16 and the third frequency divider 17 is directly input into the second frequency divider 15, and the second frame signal clock processed by the second frequency divider 15 into the preset frequency is input into the frame synchronization signal generation module 30, so that the frame synchronization signal generation module 30 generates the frame synchronization pulse signal according to the second frame signal clock, i.e. when the two-machine chain is broken, the synchronous metronome can also independently generate the frame synchronization pulse signal, thereby the synchronous metronome (i.e. the frame synchronization pulse signal) can still be stably output without artificial participation for a long time after the two-machine chain is broken.
The signal detection module 20 judges the signal state by detecting whether the second clock signal and the first clock signal exist, that is, by detecting rising edges of the internal clock signal and the external clock signal and the number thereof, and outputs a high level if the signal detection is normal, and otherwise outputs a low level. If the rising edge levels of N identical periods are continuously detected, the detection signal outputs a high level to indicate a normal state (i.e. a 1 state), otherwise, outputs a low level to indicate a 0 state. Here N is a fixed value built in, set according to the debug experience, this parameter being the same in all synchronous metronomes.
The external signal detector 22 detects the second detection signal output generated by the second clock signal as a routing signal for the selector switch 14, i.e. Mux selects 0 when the second clock signal is active, otherwise selects 1.
The second clock signal detection output (i.e., the second detection signal output from the external signal detector 22) and the first clock signal detection output (i.e., the first detection signal output from the internal signal detector 21) output a synchronization start signal as a start flag of the frame synchronization signal generation module 30 through an and circuit 23.
The implementation of signal detection by the internal signal detector 21 and the external signal detector 22 in the embodiment of the present invention may utilize the repeatable monostable trigger 34, as shown in fig. 4, and the function of signal detection may be implemented by selecting appropriate parameters so that Tw time is greater than the input period T. When the input signal is present, i.e., a periodic clock signal is continuously input, the output is high. When the input signal is not present, i.e., the input is a single level signal, the output is low.
As shown in fig. 2, the frame synchronization signal generation modules 30 of the first and second synchronous metronomes 101 and 102 in the embodiment of the present invention each include a register 31, a counter 32, a comparator 33, and a flip-flop 34. Wherein the register 31 stores a synchronization period parameter set by a user. An input of the counter 32 is connected to an output of the frame signal clock generation module for counting the number of clocks of the received first frame signal clock or second frame signal clock. The input end of the comparator 33 is connected to the output ends of the register 31 and the counter 32, and is used for judging whether the clock number calculated by the counter 32 is equal to the synchronization period parameter, if yes, outputting a high level, otherwise outputting a low level. The input of the flip-flop 34 is connected to the output of the comparator 33 for outputting the frame sync pulse signal when a high level is received, otherwise not outputting the frame sync pulse signal. So that the frame synchronization signal generating module 30 periodically outputs a frame synchronization pulse signal, and can output the sequence number data of the frame synchronization pulse signal along with the frame synchronization pulse signal, and the frame synchronization pulse signals of the two frame synchronization metronomes keep the consistency of time sequences when the two frame synchronization metronomes synchronize, and the sequence numbers data of the frame synchronization pulse signals also keep the consistency.
In addition, the frame synchronization signal generating module 30 further includes an or circuit 35, and one of input terminals of the or circuit 35 is connected to the output terminal of the signal detecting module, for receiving the synchronization start signal. The output of the or circuit 35 is connected to the RST terminals of the counter 32 and the comparator 33, which can trigger the counter 32 and the comparator 33 to restart counting and comparing when receiving the high level of the or circuit 35. The or circuit 35 outputs the high-level start counter 32 and the comparator 33 when receiving the synchronization start signal, which is a rising edge trigger signal, and the signal detection module 20 outputs a synchronization start signal when both the first clock signal and the second clock signal are active, and the frame synchronization signal generation module 30 starts outputting the frame synchronization pulse signal. The other input terminal of the or circuit 35 is further configured to receive an external signal (the external signal is a trigger signal that is manually input), and when the or circuit 35 receives the external signal, it outputs a high level trigger counter 32 and a comparator 33 to restart the count comparison, that is, the trigger synchronization of the trigger 34 in the frame synchronization signal generating module is achieved by manually inputting a signal and simultaneously notifying the counter 32 and the comparator 33 of the zero clearing count.
According to the data acquisition synchronization device provided by the embodiment of the invention, the first clock signal and the second clock signal can be calculated through the frame signal clock generation module 10 of each synchronous metronome to obtain the first frame signal clock or the second frame signal clock under the condition of double-broken chain. Upon detecting the first clock signal and the second clock signal, the output synchronization start signal triggers the frame synchronization signal generation module 30 to periodically output a frame synchronization pulse signal according to the first frame signal clock or the second frame signal clock. The synchronous metronome is a hardware device, so that the problems of increased cost and system complexity caused by introducing a third-party carrier can be avoided when the synchronous metronome is used as a peripheral of the dual-machine edge equipment, and compared with the existing signal generator which can only be used by a single machine, the synchronous metronome solves the problem of synchronous output of dual-machine interconnection. The first clock signal generated by the frame signal clock generating module 10 is a high-speed signal obtained by adopting the local oscillator clock 16 and the third frequency divider 17 to generate and process, and the frequency of the local oscillator clock 16 can range from gigahertz (GHz) to hundreds of Megahertz (MHZ), so that the real-time performance and high precision of the frame synchronization pulse signal are ensured. The hardware calculation module is used for generating a frame synchronization pulse signal by realizing the fusion calculation of the double-machine synchronization clock signals, so that the synchronization of beat signals is ensured.
In addition, each synchronous metronome in the embodiment of the present invention determines the validity of the duplex link through the signal detection module 20, and ensures that the real-time detection of the broken link condition is ensured due to the high precision of the high-frequency clock, and further, the rapid switching of the frame signal clock is realized through the signal gating circuit, so that the frame synchronization signal generation module 30 realized based on the high-speed signal can ensure that each synchronous metronome can also provide the frame signal clock based on the local oscillation clock 16 even in the case of the disconnection of the duplex link, and is used for generating the frame synchronization pulse signal with the error within the control range.
Therefore, the data acquisition synchronization device provided by the embodiment of the invention has accurate double-machine synchronous beat, can still continue to operate under the condition of double-machine chain breakage, has controllable error, and avoids the problem of double-machine brain fracture. The method can be realized under double machines without referring to three devices or equipment, and has the characteristics of strong real-time performance, high precision and the like.
The third embodiment of the present invention further provides a dual-machine hot standby system, as shown in fig. 5, which includes a first server 103, a second server 104, and a data acquisition synchronization device provided in the second embodiment of the present invention, where the structure of the data acquisition synchronization device is specifically referred to the content provided in the second embodiment of the present invention, and the embodiments of the present invention are not repeated herein. The first synchronous metronome 101 in the data acquisition synchronization device is connected with the first server 103, the second synchronous metronome 102 is connected with the second server 104, and the first server 103 and the second server 104 ensure synchronous service operation through frame synchronous pulse signals generated by the data acquisition synchronization device.
Because the dual-computer hot standby system uses the data acquisition synchronization device as the data acquisition synchronization device, the problems of increased cost and system complexity caused by introducing a third-party carrier can be avoided, and compared with a signal generator which can only be used by a single computer, the dual-computer hot standby system solves the problem of synchronous output of dual-computer interconnection. The first clock signal generated by the frame signal clock generation module 10 of each synchronous metronome under the data acquisition and synchronization device is a high-speed signal obtained by adopting local oscillator clock 16 and third frequency divider 17 to generate and process, and the frequency range of the local oscillator clock 16 signal can be from gigahertz (GHz) to hundreds of Megahertz (MHZ), so that the real-time performance and high precision of the frame synchronous pulse signal are ensured. The hardware calculation module is used for generating a frame synchronization pulse signal by realizing the fusion calculation of the double-machine synchronization clock signal, so that the synchronization of beat signals of the double-machine hot standby system is ensured.
In addition, in the dual-computer hot standby system in the embodiment of the invention, the signal detection module 20 of each synchronous metronome under the data acquisition synchronization device can judge the validity of dual-computer link, because of the high precision of the high-frequency clock, the real-time detection of the broken link condition is ensured, and further, the rapid switching of the frame signal clock is realized through the signal gating circuit, so that even under the condition that the dual-computer link is broken, each synchronous metronome can be ensured to provide the frame signal clock based on the local oscillation clock 16 and used for generating the frame synchronous pulse signal with the error in the control range, and even if the dual-computer hot standby system runs for a long time, no larger accumulated synchronous error exists, and the synchronous operation of the dual-computer hot standby system is ensured.
Therefore, in the dual-machine hot standby system, the synchronous metronome provided by the data acquisition and synchronization device is used for synchronizing the service work rhythm of the dual machines and is used for determining success or failure and real-time hot standby switching. The synchronous metronome is mainly used for synchronously calculating working beats of the double computers by the edges, and performing all actions according to the beat rhythm from data sampling and data distribution of the edges of the digital factory to data storage, and once the beat of one machine is not completed, the other machine can be connected seamlessly.
It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or fully authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards of the related country and region, and provide corresponding operation entries for the user to select authorization or rejection.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.

Claims (10)

1. A synchronous metronome, comprising:
the frame signal clock generation module (10) is used for carrying out mixing processing on a first clock signal and a second clock signal to obtain a mixed signal, processing the mixed signal into a first frame signal clock with preset frequency, wherein the first clock signal is a clock signal generated by the synchronous metronome, and the second clock signal is a clock signal generated by another synchronous metronome;
a signal detection module (20) for outputting a synchronization start signal when the second clock signal and the first clock signal are detected;
and the frame synchronization signal generation module (30) is used for generating a frame synchronization pulse signal according to the first frame signal clock under the condition that the synchronization start signal is detected.
2. The synchronized metronome of claim 1, further comprising:
and a signal gating circuit for clocking the first frame signal into the frame synchronization signal generation module (30) when the signal detection module (20) detects the second clock signal.
3. The synchronous metronome according to claim 2, wherein the signal detection module (20) is further configured to, when the second clock signal is not detected but the first clock signal is detected, process the first clock signal into a second frame signal clock of a preset frequency, and the signal gating circuit is further configured to input the second frame signal clock into the frame synchronization signal generation module (30), so that the frame synchronization signal generation module (30) generates the frame synchronization pulse signal according to the second frame signal clock.
4. The synchronous metronome according to claim 1, wherein the frame signal clock generation module (10) includes:
a mixer (11), where the mixer (11) is configured to receive the first clock signal and the second clock signal, and perform a mixing process on the first clock signal and the second clock signal to obtain the mixed signal, where the mixed signal includes a high frequency signal and a low frequency signal;
the input end of the signal processing unit is connected with the output end of the mixer (11), the output end of the signal processing unit is connected with the input end of the frame synchronous signal generating module (30), and the signal processing unit is used for filtering the low-frequency signal, processing the high-frequency signal into the first frame signal clock with the preset frequency and inputting the first frame signal clock into the frame synchronous signal generating module (30).
5. The synchronous metronome according to claim 4, wherein the signal processing unit includes:
the input end of the high-pass filter (12) is connected with the output end of the mixer (11) and is used for filtering the low-frequency signal and outputting the high-frequency signal;
the input end of the frequency dividing circuit is connected with the output end of the high-pass filter (12), the output end of the frequency dividing circuit is connected with the input end of the frame synchronizing signal generating module (30), and the frequency dividing circuit is used for processing the high-frequency signal into the first frame signal clock with preset frequency and inputting the first frame signal clock into the frame synchronizing signal generating module (30).
6. The synchronous metronome of claim 5, wherein the frequency dividing circuit comprises:
a first frequency divider (13), an input end of the first frequency divider (13) is connected with an output end of the high-pass filter (12), and the first frequency divider (13) is used for processing the frequency of the high-frequency signal to be the same as the frequency of the first clock signal;
the input end of the second frequency divider (15) is connected with the output end of the first frequency divider (13), the output end of the second frequency divider (15) is connected with the input end of the frame synchronization signal generation module (30), and the second frequency divider (15) is used for processing the high-frequency signal divided by the first frequency divider (13) into the first frame signal clock with the preset frequency and inputting the first frame signal clock into the frame synchronization signal generation module (30).
7. The synchronized metronome of claim 1, further comprising:
and a synchronization signal output module (40), wherein the synchronization signal output module (40) is used for inputting the first clock signal into another synchronization metronome to serve as a second clock signal of the other synchronization metronome.
8. The synchronous metronome according to claim 1, characterized in that the signal detection module (20) includes:
An internal signal detector (21), the internal signal detector (21) being configured to output a first detection signal when detecting the first clock signal;
an external signal detector (22), the external signal detector (22) being configured to output a second detection signal when the second clock signal is detected;
and an and circuit (23), wherein the output ends of the external signal detector (22) and the internal signal detector (21) are respectively connected with the input end of the and circuit (23), the output end of the and circuit (23) is connected with the input end of the frame synchronization signal generation module (30), and the and circuit (23) inputs the synchronization start signal to the frame synchronization signal generation module (30) when receiving the first detection signal and the second detection signal.
9. A data acquisition synchronization device, comprising:
a first synchronous metronome (101);
a second synchronous metronome (102);
the first synchronous metronome (101) and the second synchronous metronome (102) are structured as described in any one of claims 1 to 8;
the first synchronous metronome (101) is connected with the second synchronous metronome (102), a first clock signal of the first synchronous metronome (101) is sent to the second synchronous metronome (102) to serve as a second clock signal of the second synchronous metronome (102), and the first synchronous metronome (101) receives the first clock signal from the second synchronous metronome (102) to serve as the second clock signal of the first synchronous metronome (101).
10. A dual hot standby system, comprising:
a first server (103);
a second server (104);
the data acquisition synchronization device of claim 9;
the first synchronous metronome (101) in the data acquisition synchronization device is connected with the first server (103), the second synchronous metronome (102) is connected with the second server (104), and the first server (103) and the second server (104) ensure synchronous service operation through frame synchronous pulse signals generated by the data acquisition synchronization device.
CN202310283457.7A 2023-03-16 2023-03-16 Synchronous metronome, data acquisition synchronization device and double-machine hot standby system Pending CN116736677A (en)

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