JP2013183403A - Clock phase synchronization device and clock phase synchronization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock phase synchronization technique preventing a phase difference from being generated on a clock switched from an active-system clock oscillator to a standby-system clock oscillator.SOLUTION: A clock phase synchronization device includes: standby-system clock oscillation means; an active-system clock input terminal; phase amount measurement means for measuring a phase difference between the active-system clock and the standby-system clock; first storage means for storing the phase difference; and delay means for delaying a clock by the phase difference stored in the first storage means in response to the standby-system clock. A clock phase synchronization method includes: oscillating a standby-system clock; measuring a phase difference between the active-system clock and the stand-by system clock in response to the active-system clock used in the system; storing the phase difference; and delaying a clock by the phase difference stored in the first storage means with respect to the standby-system clock; and outputting the clock as a standby-system synchronization clock.

Description

  The present invention relates to a signal synchronization apparatus, and more particularly to an apparatus for synchronizing a time clock when operating by switching a plurality of clock oscillators.

  The clock generator described in Patent Document 1 includes an oscillator that generates a reference clock, a selector that selects an active or standby reference clock, and the same phase in synchronization with the phase of the reference clock input from the selector. And a PLL circuit that outputs a reference clock locked in the above. The clock generation device is a clock generation device having a duplex configuration of an active system and a standby system that includes a system switching control circuit that detects a failure of the own system and switches to another system. When a failure occurs in the active system and the standby system is switched to the active system, the PLL circuit outputs a reference clock having the same phase as before the system switching even after a reference clock having a different phase is input from the selector. However, the PLL circuit thereafter outputs a reference clock that is locked following a different phase gradually.

JP 2003-198430 PR

  In the clock generator described in Patent Document 1, when switching from the active clock oscillator to the standby clock oscillator, the phases of the clocks coincide at the instant of switching. However, since the reference oscillation source is switched at the same time, the PLL circuit that outputs the clock changes the rising timing of the pulse to match the phase of the oscillation source of the new clock. As a result, a clock phase difference occurs before and after switching. The phase difference between the clocks generated in this way has an effect on the host device, resulting in a system failure.

  The present invention provides a clock phase synchronization apparatus that does not generate a clock phase difference before and after switching even when switching between the active clock oscillator and the standby clock oscillator.

  The clock phase synchronization apparatus of the present invention receives a standby clock oscillation means for oscillating a standby clock and an operational clock used in the system, and the standby clock described above with reference to the operational clock. The phase amount measuring means for measuring the phase difference of how far the phase is advanced, the first storage means for storing the phase difference obtained by the phase amount measuring means, and the standby system clock are input. And delay means for outputting a standby synchronization clock having a delay equal to the phase difference stored in the first storage means.

  The clock phase synchronization method of the present invention oscillates a standby clock, inputs an operational clock used in the system, and how much the phase of the standby clock advances with respect to the operational clock described above. The phase difference is measured, the phase difference is stored, the delay equal to the phase difference stored in the first storage unit is performed with respect to the standby system clock, and output as a standby system synchronization clock. To do.

  The present invention has an effect that the phase of the clock does not change with respect to a device using the clock even when the active clock oscillator is switched to the standby clock oscillator.

It is a basic block block diagram of the clock phase synchronization apparatus of the 1st Embodiment of this invention. It is a block block diagram of one Example of the delay part in this invention. It is a basic block block diagram of the clock phase synchronization apparatus of the 2nd Embodiment of this invention. It is an operation | movement timing waveform diagram of the switching of the clock phase synchronizer in this invention. It is a basic block block diagram of the clock phase synchronization system using the clock phase synchronization apparatus of this invention. It is a basic block block diagram of a clock phase synchronization system using a plurality of clock phase synchronization devices of the present invention.

FIG. 1 is a basic block configuration diagram of a clock phase synchronization apparatus according to a first embodiment of the present invention.
The clock phase synchronization device 5 includes a standby clock oscillation unit 1, a phase amount measurement unit 2, a first storage unit 3, and a delay unit 4.

  The standby clock oscillation unit 1 is a dedicated oscillation circuit that oscillates a pulse. The standby clock oscillation unit 1 may be a clock oscillation circuit or an external oscillation device that operates a control processor in the clock phase synchronization device. The standby system clock oscillation unit 1 inputs the standby system clock to the phase amount measurement unit 2 and the delay unit 4.

  The phase amount measuring unit 2 is a time measuring circuit using a counter. The counter starts measuring after receiving the rising edge of the standby system clock and ends after receiving the rising edge of the operating system clock, thereby measuring the time difference between the rising edges of both clocks, that is, the phase difference between both clocks. The phase amount measuring unit 2 performs phase comparison using a flip-flop, converts a pulse signal obtained from the output of the above-described flip-flop into a DC signal by an integration circuit, and measures a phase difference from the voltage value Etc.

  The first storage unit 3 is a dedicated register. The first storage unit 3 may be a RAM area in the processor used for control inside the clock phase synchronization apparatus 5 or a RAM that is external storage of the processor. The first storage unit 3 temporarily stores the phase difference measured by the phase amount measurement unit 2. The delay unit 4 receives the above-described phase difference from the above-described first storage unit 3. The delay unit 4 calculates a delay amount from the above-described phase difference. The delay unit 4 delays the standby system clock input from the standby system clock oscillation unit 1 based on the delay amount described above, and outputs a standby system synchronization clock. Therefore, the phase of the standby system synchronization clock matches the operation system clock.

  FIG. 2 is a block diagram of an embodiment of the delay unit 4 in the clock phase synchronization apparatus shown in FIG. The operation will be described with reference to FIG.

  The delay unit 4 includes a delay element group 404, a phase difference data conversion unit 402, and a selector 403.

  The delay element group 404 includes n (plural) delay elements 401 (delay elements 1 to n). The delay element 401 may be, for example, an analog delay element such as a delay line or a delay circuit using a shift register. Each delay element is connected in series, and each output terminal is connected to the input terminal of the next stage. The standby clock oscillator 1 shown in FIG. 1 inputs the standby clock to the input of the delay element 1 arranged at the first stage of the delay element group 404. Each delay element from the delay element 1 and the delay element 2 arranged in the subsequent stage to the delay element n-1 inputs the received standby system clock to the next stage. As a result, each delay element from the delay element 1 to the delay element n outputs a standby clock having a delay corresponding to the number of stages of the respective delay elements.

  The output terminal of each delay element from the delay element 401 to the delay element n is connected to the output terminal of the delay element group 404. Each output terminal of the delay element group 404 is connected to each input terminal of the selector 403. The delay element group 404 inputs each of the delayed standby clocks to the selector 403. The first storage unit 3 shown in FIG. 1 inputs the phase difference to the phase difference data conversion unit 402 shown in FIG. The phase difference data conversion unit 402 calculates the number of delay elements corresponding to the number of delay elements corresponding to the above-described phase difference, with the delay amount corresponding to one delay element as a basic unit. The phase difference data conversion unit 402 inputs a selection signal representing the number of stages of the delay elements to the control input terminal of the selector 403. The selector 403 selects one of the delayed standby clocks from the input of the selector 403 based on the received selection signal, and outputs it as a standby synchronization clock.

  As described above, the clock phase synchronization apparatus 5 of the present invention stores the phase difference measured by the phase amount measuring unit 2 in the first storage unit 3, and the delay unit 4 performs a delay operation based on the stored phase difference. Thus, a standby system synchronization clock synchronized with the operation system clock can be generated. For this reason, the clock phase synchronization apparatus 5 of the present invention can synchronize the standby synchronization clock following the operation clock even if the phase of the operation clock changes.

  FIG. 3 is a basic block configuration diagram of the clock phase synchronization apparatus 5 according to the second embodiment of the present invention.

  The clock phase synchronization apparatus 5 includes a standby clock oscillation unit 1, a frequency ratio measurement unit 301, a second storage unit 302, a frequency divider 303, a phase amount measurement unit 2, a first storage unit 3, and a delay unit 4. Is provided.

  The standby clock oscillation unit 1 is a dedicated oscillation circuit that oscillates a pulse. The standby clock oscillation unit 1 may be a clock oscillation circuit or an external oscillation device that operates a control processor in the clock phase synchronization device 5.

Standby system clock oscillator 1 inputs a standby system clock to frequency divider 303 and frequency measuring unit 301. The frequency ratio measurement unit 301 measures the frequency ratio of how many times the frequency of the standby system clock oscillation unit 1 is based on the operation system clock, and inputs the value to the second storage unit 302.

  The second storage unit 302 stores the frequency ratio described above and inputs the frequency ratio described above to the frequency divider 303.

  The frequency divider 303 divides the standby clock received from the standby clock oscillator 1 by a frequency equal to the frequency ratio and outputs a standby frequency synchronization clock. At this time, the operating system clock and the standby system frequency synchronization clock have the same frequency.

  Next, the phase amount measurement unit 2 receives the standby system frequency synchronization clock and the operation system clock, measures how much the phase of the standby system frequency synchronization clock is advanced with reference to the operation system clock, The phase difference is input to the storage unit 3.

  The first storage unit 3 stores the above phase difference and inputs the above phase difference to the delay unit 4.

  The delay unit 4 calculates a delay amount from the above-described phase difference. The delay unit 4 delays the standby system frequency synchronization clock received from the frequency division unit 303 based on the calculated delay amount, and outputs the standby system synchronization clock.

  FIG. 4 is a timing waveform diagram of the delay operation of the clock phase synchronization apparatus according to the present invention. The operation timing for synchronizing the phases will be described with reference to FIG.

  FIG. 4A shows the waveform of the pulse shown in FIG. 4A shows the waveform of the operation clock input to one end of the phase amount measuring unit 2 by the system.

  4B shows the waveform of the pulse shown in FIG. 4B shows the waveform of the standby clock that is input to the other input terminal of the phase amount measurement unit 2 and the input terminal of the delay unit 4 by the standby clock oscillation unit 1.

  In the period before phase synchronization in FIG. 4, comparing the pulse waveform of the standby clock (B) with the pulse waveform of the operational clock (A) shows that the standby clock (B) is in the lead phase. ing. 1 measures the phase difference from the rising edge of the standby system clock (B) to the rising edge of the operation system clock (A), and the obtained phase difference t1 is stored in the first memory. Input to part 3. The phase difference t1 (D) in FIG. 4 indicates the phase difference from the rising edge of the standby system clock (B) pulse to the rising edge of the operation system clock (A).

  Next, the first storage unit 3 stores the phase difference t1 during the synchronization period of FIG. The first storage unit 3 inputs the phase difference t1 to the delay unit 4. The delay unit 4 delays the delay operation t1 equal to the phase difference t1 with respect to the standby system clock (B). The delay operation t1 (E) in FIG. 4 is a waveform obtained by delaying the standby clock (B) by the delay operation t1. By this operation, the delay unit 4 generates a standby system synchronization clock (C) whose phase is synchronized with the operation system clock (A). 4 shows a state in which the phases of the active system clock (A) and the standby system synchronization clock (C) are synchronized in the period after phase synchronization in FIG.

  Thus, in the clock phase synchronization apparatus 5 of the present invention, the frequency measuring unit 301 measures the frequency ratio, stores it in the second storage unit 302, and the frequency dividing unit 303 calculates the frequency based on the stored frequency ratio. The delay unit 4 performs a delay operation based on the phase difference measured by the phase amount measurement unit 2 after the change. Thereby, the clock phase synchronization apparatus 5 of the present invention can generate a standby system synchronization clock synchronized with the operation system clock. For this reason, the clock phase synchronization apparatus 5 of the present invention allows the standby system synchronization clock to follow the frequency change of the operation system clock even if the frequency of the operation system clock changes according to the request of the host system or the arithmetic unit. There is an effect that the frequency and phase can be synchronized.

  FIG. 5 is a basic block diagram of a clock phase synchronization system using the clock phase synchronization device 5 of the present invention.

  The clock phase synchronization system 100 of FIG. 5 includes a clock phase synchronization device 5, an active clock oscillation unit 7, and a changeover switch 6.

  The active clock oscillation unit 1 is a dedicated oscillation circuit that oscillates a pulse. The active clock oscillation unit 1 may be a clock oscillation circuit or an external oscillation device that operates a control processor in the clock phase synchronization system.

  The changeover switch 6 is an electronic circuit that selects any one of a plurality of input terminals and connects to the output terminal. The changeover switch 6 may be a switch having a mechanical contact.

  The working clock oscillator 7 oscillates the working clock and inputs the working clock to one of the input terminals of the changeover switch 6. The changeover switch 6 selects the active clock and outputs it as the operational clock. The clock phase synchronizer 5 and the arithmetic unit 8 receive the aforementioned operational clock. The arithmetic unit operates based on the input operational clock.

  The delay unit 4 of the clock phase synchronization device 5 inputs the standby system synchronization clock to the other input terminal of the changeover switch 6. At this time, as described in the explanation of the operation of the clock phase synchronization apparatus 5 in FIG. 1, the phase of the standby system synchronization clock output from the delay unit 4 of the clock phase synchronization apparatus 5 is equal to the phase of the operation system clock. I'm doing it.

  Next, a case where a failure occurs in the active clock oscillation unit 7 will be described.

  When a failure occurs in the active clock oscillation unit 7, the failure notification signal output by the active clock oscillation unit 7 is input to the changeover switch 6. The changeover switch 6 that has received the failure notification signal disconnects the connection between the input terminal of the changeover switch 6 to which the output of the active clock oscillation unit 7 is connected and the output terminal of the changeover switch 6. The other input terminal of the changeover switch 6 to which the output of the delay unit 4 is connected is connected to the output terminal of the changeover switch 6. The changeover switch 6 outputs the standby system synchronization clock as the operation system clock. Thus, since the clock phase synchronization system 100 of the present invention is switched when the phases of the active clock and the standby synchronization clock are in a synchronized state, the clock phase synchronization system 100 includes the arithmetic unit 8. In contrast, it is possible to supply an operational clock having no phase disturbance. The clock phase synchronization device 5 may be the same as that of the second embodiment.

  FIG. 6 is a basic block diagram of a clock phase synchronization system 100 using a plurality of clock phase synchronization devices 5 of the present invention.

  The clock phase synchronization system 100 includes an active clock oscillation unit 7, a plurality of clock phase synchronization devices 5 (clock phase synchronization device 5-1 and clock phase synchronization device 5-2), a changeover switch 6, and a switching command unit 9. The fault notification unit 10 and one or more arithmetic units 8 (the arithmetic unit 8-1 and the arithmetic unit 8-2) are provided.

  The active clock oscillation unit 7 is a dedicated oscillation circuit that oscillates a pulse. The active clock oscillation unit 7 may be a clock oscillation circuit or an external oscillation device that operates a control processor in the clock phase synchronization system 100.

The working clock oscillator 7 oscillates the working clock, and inputs the working clock to one of the input terminals of the changeover switch 6.
The changeover switch 6 selects the active clock and outputs the operational clock. The changeover switch 6 inputs operational clocks to the arithmetic unit 8-1, the arithmetic unit 8-2, and the clock phase synchronizers 5-1 and 5-2. At this time, as described in the explanation of the operation of the clock phase synchronization device 5 in FIG. 1, the phase and operation of the standby system synchronization clock output by the clock phase synchronization device 5-1 and the clock phase synchronization device 5-2 The phase of the system clock matches.

  Next, a case where a failure occurs in the active clock oscillation unit 7 will be described.

  When a failure occurs in the active clock oscillation unit 7, the failure notification signal output by the active clock oscillation unit 7 is transmitted to the failure notification unit 10, the clock phase synchronization device 5-1, and the clock phase synchronization device 5-2. To the arithmetic unit 8-1 and the arithmetic unit 8-2.

  The clock phase synchronization device 5-1 and the clock phase synchronization device 5-2 receive the failure notification signal output from the active clock oscillation unit 7 and outputs its own survival signal to the failure notification unit 10.

  The failure notification unit 10 collects the failure notification signal output from the active clock oscillation unit 7 and the survival signal output from the clock phase synchronization device 5-1 and the clock phase synchronization device 5-2. The failure notification unit 10 generates device survival information that shows the availability status of each device in a list or the like based on the collected failure notification signal and survival signal. The failure notification unit 10 inputs device survival information to the switching command unit 9. The switching command unit 9 selects the surviving clock synchronization device 5 based on the device survival information received from the failure notification unit 10 and generates a switching command signal. The change command unit 9 outputs a change command signal to the change switch 6.

  The changeover switch 6 disconnects the connection between the input terminal receiving the active clock from the output of the active clock oscillator 7 and the output terminal of the changeover switch 6 based on the received switching command signal. The changeover switch 6 selects either one of the clock phase synchronizer 5-1 and the clock phase synchronizer 5-2. Here, it is assumed that the clock phase synchronization device 5-1 is selected. The input terminal of the changeover switch 6 that receives the output of the clock phase synchronization device 5-1 is connected to the output terminal of the changeover switch 6. As a result, the changeover switch 6 outputs the standby system synchronization clock received from the clock phase synchronization device 5-1 as the operation system clock. The arithmetic unit 8-1 and the arithmetic unit 8-2 continue to operate by continuously receiving the switched operation system clock.

  Further, a case where a failure has occurred in the clock phase synchronization apparatus 5-1 will be described. At this time, it is assumed that the active clock oscillation unit 7 in which the failure has occurred first is in a state where the failure has occurred.

  The standby clock oscillation unit 1 in the clock phase synchronization device 5-1 outputs the failure notification signal output by itself to the failure notification unit 10. The active clock oscillator 7, clock phase synchronizer 5-2, arithmetic unit 8-1 and arithmetic unit 8-2 are the standby system clock oscillator 1 in the above-described clock phase synchronizer 5-1. Receives the failure notification signal output by.

  The failure notification unit 10 collects the failure notification signal of the active clock oscillation unit 7, the failure notification signal of the clock phase synchronization device 5-1, and the device survival signal of the clock phase synchronization device 5-2. The failure notification unit 10 inputs device survival information to the switching command unit 9 that displays the availability status of each device in a list or the like based on the collected failure notification signal and survival signal.

  The switching command unit 9 selects the surviving clock phase synchronization device 5 from the device survival information received from the failure notification unit 10 and generates a switching command signal. The switching command unit 9 outputs the above-described switching command signal to the switch 6.

  Based on the change command signal received by the changeover switch 6 from the changeover command unit 9, the connection between the input terminal receiving the standby system synchronization clock from the output of the clock phase synchronization device 5-1 and the output terminal of the changeover switch 6 is established. The input terminal receiving the output of the clock phase synchronizer 5-2 is disconnected and connected to the output terminal of the changeover switch 6. The arithmetic unit 8-1 and the arithmetic unit 8-2 continue to operate by continuously receiving the switched operation system clock.

  In this way, even if the operating clock is switched, there is no phase disturbance before and after switching, so that the clock phase synchronization system 100 can continue to operate stably.

  1, 2, 3, 5, and 6, the delay element may be an analog delay element such as a delay line or a delay circuit using a shift register. 3 may be a frequency divider using a PLL circuit, a frequency divider using a counter, or the like.

  As described above, the clock phase synchronization system 100 of the present invention has a plurality of clock phase synchronization devices 5 that output the standby system synchronization clocks synchronized with the phase of the operation system clock, and there is a failure in the clock generation source in the system. Even if it occurs, these clock generation sources can be sequentially switched in a state where the cycle is not disturbed. Therefore, the clock phase synchronization system 100 of the present invention has an effect that the operation can be continued without stopping even if a failure occurs in one clock generation source.

  Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Standby system clock oscillation part 2 Phase amount measurement part 3 First memory | storage part 4 Delay part 5 Clock phase synchronizer 5-1 Clock phase synchronizer 5-2 Clock phase synchronizer 6 Changeover switch 7 Active clock oscillation Unit 8 Arithmetic Unit 8-1 Arithmetic Unit 8-2 Arithmetic Unit 9 Switching Command Unit 10 Fault Notification Unit 100 Clock Phase Synchronization System 301 Frequency Ratio Measuring Unit 302 Second Storage Unit 303 Dividing Unit 401 Delay Element 402 Phase Difference Data Conversion unit 403 selector 404 delay element group

Claims (8)

A standby clock oscillation means for oscillating a standby clock;
A phase amount measuring means for inputting an operational clock used in the system and measuring a phase difference indicating how much the phase of the standby clock is advanced with respect to the operational clock;
First storage means for storing the phase difference obtained by the phase amount measuring means;
A delay unit that inputs the standby system clock and outputs a standby system synchronization clock having a delay equal to the phase difference stored in the first storage unit;
A clock phase synchronization apparatus comprising: The delay means has a plurality of delay elements connected in series so as to sequentially delay the input clock, the standby clock is input, and the number of stages connected from each output terminal of the plurality of delay elements A delay element group for outputting the standby system clock delayed by minutes;
A phase difference data conversion unit that calculates the number of delay elements corresponding to the number of delay elements based on the delay amount corresponding to one stage of the delay elements as the basic unit, and outputs a selection signal that represents the number of stages of the delay elements;
Selecting one of the output terminals of each of the plurality of delay elements according to the selection signal, selecting as the standby system synchronization clock, and having a selector for outputting,
The clock phase synchronization apparatus according to claim 1. Frequency ratio measuring means for measuring a frequency ratio between the operational clock and the standby clock;
Second storage means for storing the frequency ratio obtained by the frequency ratio measuring means;
The standby system clock is further input, and frequency dividing means for performing frequency division equal to the previous frequency ratio stored in the second storage means and outputting a standby system frequency synchronization clock is further provided, Instead, the standby system frequency synchronization clock is input to the delay unit and the phase amount measurement unit, the operation system clock is input to the phase amount measurement unit, and the standby system synchronization clock is output from the delay unit. To do,
The clock phase synchronization apparatus according to claim 1 or 2, wherein A working clock oscillation means for oscillating a working clock;
A clock phase synchronization device according to any one of claims 1 to 3;
A change-over switch that switches between the active clock and the standby synchronization clock and outputs an operational clock to the arithmetic unit and the phase amount measuring means;
A clock phase synchronization system comprising: 4. A plurality of the present invention includes an active clock oscillator that oscillates an active clock and that can detect its own fault, and a standby clock oscillator that can detect its own fault. A clock phase synchronization device of
An arithmetic unit that operates using an operational clock; and
Provide an output terminal for outputting the operational clock, input a failure notification signal from the current clock generation means connected to the output terminal, disconnect from the output terminal of the active clock generation means, either An output terminal of a first clock phase synchronization device that is one of the standby system synchronization clock generation means is connected to the output terminal, and further from a standby system clock oscillation means in the first clock phase synchronization device. A fault notification signal is input, the first clock phase synchronization device is disconnected from the output terminal, and any remaining clock phase synchronization device is connected to the output terminal and the operation clock is output. A switch,
A clock phase synchronization system consisting of: Oscillate the standby clock,
Input the operational clock used in the system, measure the phase difference how much the phase of the standby clock is advanced with respect to the operational clock,
Storing the phase difference;
A delay equal to the phase difference stored in the first storage unit is performed with respect to the standby system clock,
A clock phase synchronization method characterized by outputting as a standby system synchronization clock. A plurality of delay elements are connected in series so as to sequentially delay the input clock, to form a delay element group,
Input the standby clock to the first stage of the delay element group,
From each output terminal of the plurality of delay elements, output the standby system clock delayed by the number of connected stages,
The phase difference is calculated based on the delay amount of one stage of the delay element as a basic unit, and the number of delay elements corresponding to the delay is calculated and a selection signal representing the number of stages of the delay element is output,
7. The clock phase synchronization method according to claim 6, wherein one of the output terminals of each of the plurality of delay elements corresponding to the selection signal is selected, selected as the standby system synchronization clock, and output. Measure the frequency ratio between the operational clock and the standby clock,
Storing the frequency ratio;
Input the standby system clock, perform a frequency division equal to the ratio of the stored frequency, and output as a standby system frequency synchronization clock,
8. The clock phase synchronization method according to claim 6, wherein the standby system synchronization clock is output by delaying a phase difference between the standby system frequency synchronization clock and the operation system clock.

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