JPH06224749A - Frequency clock device - Google Patents

Abstract

PURPOSE:To simplify the configuration and to obtain a highly accurate frequency clock by using one of output frequencies of three frequency standard devices or over for a reference frequency to obtain a frequency deviation and using a majority decision computing element to decide a reference frequency and selecting the output frequency through majority comparison. CONSTITUTION:Output frequencies from three atom frequency standard devices 1a-1c or the like are given to a frequency comparator 14, in which relative deviations 15a, 15b of the standard devices 1a, 1c based on the output frequency from the standard device 1b or the like are obtained and fed to a majority decision arithmetic operation section 17. The relative deviation of the output frequency of the standard device 1b is obtained by the arithmetic operation section 17 with respect to the relative deviations 15a, 15b, and three relative deviations are subject to majority decision. One output frequency of one standard device among the 15a, 15b standard devices 1a-1c is selected by a changeover device 18 based on the result of majority decision. The clock with a highly accurate frequency is obtained through simple configuration that employs only one frequency comparator.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency clock device for outputting a clock signal having a very accurate frequency, and more particularly, to a highly accurate frequency clock device by minimizing the number of expensive frequency comparators. The present invention relates to a frequency clock device that can obtain a frequency clock signal at low cost.

[0002]

2. Description of the Related Art In general, space communication and digital optical fiber communication require an extremely accurate frequency clock device. 2. Description of the Related Art In recent years, there has been known a frequency clock device that uses an atomic frequency standard device that utilizes the resonance vibration of atomic nuclei as a frequency source, and that takes a majority decision of the outputs of the atomic frequency standard devices of a plurality of systems in order to improve the accuracy.

FIG. 4 shows an example of such a conventional frequency clock device, FIG. 4 (a) is an overall configuration diagram, and FIG. 4 (b) is an internal configuration diagram of a frequency comparator.

As shown in FIG. 4 (a), this conventional frequency clock device is provided with triple atomic frequency standards 1a, 1b and 1c, and the output frequencies 2a, 2b and 2 of these three are provided.
c by 3 frequency comparators 3a, 3b, 3c
The relative frequency deviation of each of the two is measured.
That is, the frequency comparator 3a outputs the output frequencies 2a and 2b.
, The relative frequency deviation between the output frequencies 2b and 2c is obtained by the frequency comparator 3b, and the relative frequency deviation between the output frequencies 2a and 2c is obtained by the frequency comparator 3c. Then, three majority comparisons of the measurement data 4a, 4b, 4c are carried out by the majority logic unit 5, and the switching unit 7 is switched by the signal 6 for selecting one from the atomic frequency standard devices of the three parties according to the majority comparison result. Drive to obtain the selected frequency output 8.

The frequency comparator 3 used here
a, 3b, and 3c are used exclusively for the atomic frequency standard, and as shown in FIG. 4B, the frequency synthesizer 9,
It is composed of a frequency difference expansion unit by the beat method, which is a combination of the mixer 10 and the doubling unit 12a, a frequency counter 11, and a doubling unit 12b. The frequency synthesizer 9 is for increasing the expansion rate of the frequency difference, and a PLL using a crystal oscillator is used. This crystal oscillator is composed of a low phase noise crystal oscillator in order to prevent the additive noise of the PLL from affecting the measurement frequency, and it is necessary to process the measurement result of the frequency counter by the filtering method using the cyclic moving average. That is, the frequency comparators 3a, 3b, 3 for the high precision atomic frequency standard
c has a specially complicated and expensive equipment configuration, which exceeds the price of the atomic frequency standard and is a cause of high cost.

[0006]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a frequency clock device capable of obtaining a highly accurate frequency clock signal at low cost.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention obtains a relative frequency deviation between output frequencies from at least three frequency standards and performs a majority decision comparison, and according to the result of the majority decision comparison, the plurality of frequency standards are compared. In a frequency clock device for selecting and outputting one of the output frequencies from the output device, at least one arbitrary output frequency of the above output frequencies is used as a reference, and between this reference and the other two output frequencies. It is characterized by comprising means for obtaining two relative frequency deviations and means for calculating the remaining one relative frequency deviation from the two relative frequency deviations and performing a majority comparison of the three relative frequency deviations in total.

[0008]

The present invention will be described below based on the illustrated embodiments. FIG. 1A is a block diagram showing an embodiment of a frequency clock device according to the present invention.

In FIG. 1 (a), this frequency clock device effectively uses a small number of frequency comparators, and the output frequency 2a from three atomic frequency standards 1a, 1b, 1c, One frequency comparator 14 that measures two relative frequency deviation data of 2b and 2c and two relative frequency deviation data 15a and 15b output from this frequency comparator 14 are processed to perform majority comparison. , 3 atomic frequency standards 1a according to the majority comparison result,
A majority arithmetic unit 17 for outputting a command signal 16 for selecting one of 1b and 1c, and a switch for outputting one of the output frequencies 2a, 2b, 2c in accordance with the command signal from the majority arithmetic unit 17. It consists of a vessel 18.

Next, the frequency comparator 1 which is the main part of the present invention
4 and the majority decision calculator 17 will be described.

As shown in FIG. 1B, the frequency comparator 14 is a combination of first and second frequency synthesizers 20 and 21, an invertor 22, and first and second mixers 23 and 24. And a frequency difference expanding unit, first and second frequency counters 25 and 26, and an doubling unit 27. Then, using the output frequency 2b of the atomic frequency standard 1b as a reference, the relative frequency deviation from the output frequency 2a of the atomic frequency standard 1a is actually measured with respect to this reference, and as a result deviation data 15a is obtained, and at the same time, The relative frequency deviation from the output frequency 2c of the atomic frequency standard 1c is actually measured with respect to the above reference, and as a result, deviation data 15b is obtained.

Next, the majority operator 17 uses the two deviation data 15a and 15b to determine the frequency comparator 1
The relative frequency deviation data 15c between the output frequency 2a from the atomic frequency standard 1a and the output frequency 2c from the atomic frequency standard 1c which are not measured in 4 is calculated, and the two measured deviations 15a and 15b are calculated. A majority logic is constructed based on the three deviation data of the one deviation data 15c thus generated, and the logic result is output to the switch 18 as a selection command signal 16.

The deviation data 15a and 15b are actually measured by the output frequency 2 from the atomic frequency standard 1a.
a is f ₀ + Δf _a , the output frequency 2b from the atomic frequency standard 1b is f ₀ + Δf _b, and the output frequency 2c from the atomic frequency standard 1c is f ₀ + Δf _c ,
If f _b is treated as a temporarily determined frequency, the deviation data 15a becomes | Δf _a −Δf _b | → | Δf _a |, and the deviation data 15b becomes | Δf _b −Δf _c | → |
Δf _c | The calculation of the deviation data 15c can be easily obtained by calculating | Δf _c −Δf _a |. Then, the deviation data 15a, 15b,
When the relationship of 15c is specifically shown in the graph, there are six possible cases as shown in FIG.

Next, a modification of the above embodiment will be described with reference to FIG.

In this modification, as shown in FIG. 3, the output frequency 2a is used instead of the one frequency comparator 14 described above.
Is provided with a frequency comparator 30a for obtaining relative frequency deviation data 15a between the output frequency 2b and the output frequency 2b, and a frequency comparator 30b for obtaining relative frequency deviation data 15b between the output frequency 2b and the output frequency 2c. The configuration is the same as that of the above-described embodiment, and thus the description thereof is omitted.

[0016]

As described above, the present invention provides an expensive and complicated frequency comparison and measurement system for relative frequency deviation, which is half that of the conventional system.
It is configured to supplement the frequency comparison and measurement system by reducing the number to 1/3 and adding the arithmetic function to the majority logic unit, thus simplifying the configuration of the frequency clock device equipped with the atomic frequency standard device. It is possible to improve the reliability and reduce the price.

[Brief description of drawings]

1A and 1B are a block diagram of an embodiment of a frequency clock device according to the present invention and a block diagram of a frequency comparator thereof.

FIG. 2 is a graph showing a relationship between deviation data 15a, 15b, 15c in the embodiment of the frequency clock device shown in FIG.

FIG. 3 is a configuration diagram of a modification of the embodiment of the frequency clock device shown in FIG.

4A and 4B are a block diagram of a conventional frequency clock device and a block diagram of a frequency comparator thereof.

[Explanation of symbols]

1a, 1b, 1c ......... Atomic frequency standard 2a, 2b, 2c ... Output frequency 3a, 3b, 3c, 14, 30a, 30b ..... Frequency comparator 4a, 4b, 4c, 15a, 15b. … Relative frequency deviation data 5 …… .Majority logic device 6,16 ………… Selection command signal 7,18 ………… Switcher 8 ………… Frequency output 9,20,21 ………… Frequency synthesizer 10,23, 24 ... Mixer 11, 25, 26 ... Frequency counter 12a, 12b, 22, 27 ... Multiplier

Claims (2)

[Claims] 1. A relative majority deviation between output frequencies from at least three frequency standards is calculated and a majority comparison is performed, and one of the output frequencies from the three frequency standards is determined according to the result of the majority comparison. A frequency clock device for selecting and outputting, wherein means for determining two relative frequency deviations between at least one arbitrary output frequency among the above output frequencies as a reference and between the reference and the other two output frequencies is provided. And a means for calculating the remaining one relative frequency deviation from the two relative frequency deviations and performing a majority comparison of a total of three relative frequency deviations. 2. The means for obtaining two relative frequency deviations between the reference of the arbitrary output frequency and the other two output frequencies comprises one frequency comparator. The described frequency clock device.