CN1167123C - Semiconductor package whose package sealant possesses shoulder portion and mould for packaging said semiconductor package - Google Patents
Semiconductor package whose package sealant possesses shoulder portion and mould for packaging said semiconductor package Download PDFInfo
- Publication number
- CN1167123C CN1167123C CNB001324365A CN00132436A CN1167123C CN 1167123 C CN1167123 C CN 1167123C CN B001324365 A CNB001324365 A CN B001324365A CN 00132436 A CN00132436 A CN 00132436A CN 1167123 C CN1167123 C CN 1167123C
- Authority
- CN
- China
- Prior art keywords
- substrate
- mould
- shoulder
- semiconductor package
- packing colloid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention relates to a semiconductor packaging piece with a packaging glue body which is provided with a shoulder. The semiconductor packaging piece which is provided with a basal plate for bearing a crystal wafer, wherein a packaging glue body, which is shaped with packaging resin in a solidification mode, covers the crystal wafer and the surface of the partial basal plate after the basal plate and the crystal wafer are electrically connected. The packaging glue body is formed by the moulding of a mould with an upper mould and a lower mould; the upper mould is provided with a mould cavity, and the circumference of the opening of the mould cavity extends outwards to form a concave part; consequently, the connecting position of the packaging glue body and the basal plate forms a shoulder which extends outwards after the packaging glue body is shaped. The concave part forms a narrow channel structure after the upper mould and the lower mould are combined, and a phenomenon that small cracks are generated on the surface of the basal plate because a mould combining pressure is too large is reduced.
Description
Technical field
The present invention relates to a kind of semiconductor package part, particularly relating to a kind of is the carrier of carries chips and with the semiconductor package part of packing colloid coating chip with the substrate.
Background technology
Traditionally, with substrate (Substrate) is the semiconductor device of the carrier (Chip Carrier) of carries chips, (Ball Grid Array, BGA) semiconductor device stick on the surface of putting for chip in this substrate with the packing colloid coating chip often as ball grid array.This packing colloid generally then is the mould compression molding person with tool patrix and counterdie, as shown in Figure 6, in mold pressing (Molding) process, gluing has the substrate 11 of chip 10 to be folded in 13 of patrix 12 and counterdies, and this patrix 12 has a die cavity 14 in order to the potting resin that solidify to form this packing colloid 15 from injecting glue road (not shown) streamer wherein.
But, because being used for the substrate finished product of BGA semiconductor device tends to because of the precision deficiency, and have ± thickness difference of 0.05mm, cause patrix 12 and counterdie 13 that substrate 11 is inserted and put therebetween and behind the matched moulds, can produce following point because of uneven thickness: when just like clamping pressure is big, hallrcuts (Micro-Crack) takes place because of the layer (SolderMask) of refusing that improper pressurized makes substrate 11 surfaces go up coating in substrate 11 thicker parts, and the generation of hallrcuts then will have influence on the reliability on the manufactured goods Electronic Performance; If two avoid excessive causing of clamping pressure hallrcuts to occur on the substrate 11, and when clamping pressure reduced, tend on the position of substrate 11 thinner thicknesses, cause and form excessive gap between the bottom surface of substrate 11 upper surfaces and patrix 12 and the potting resin mould is flowed in mold process, infiltrate in this gap, make substrate 11 the glue (Flash) that overflows not take place on the surface of covering for packing colloid 15 covers, glue can be removed after mold process is finished though overflow, but can increase manufacturing cost and process, and also easily undermine the qualification rate reduction that substrate 11 or packing colloid 15 itself make manufactured goods accidentally because of handling; Be installed in (Floating) institutional adjustment of floating on the mould though three clamping pressures are available, produce the excessive or not enough problem of local clamping pressure in the time of only still can't avoiding substrate 11 uneven thickness fully.So, how effectively to solve the hallrcuts that causes because of clamping pressure is improper in the mold process or the generation of excessive glue, be to become an industry big problem to be solved.
Summary of the invention
A purpose of the present invention is to provide a kind of glue of effectively avoiding overflowing to take place and the packing colloid that must reduce clamping pressure has the semiconductor package part of shoulder.
Another object of the present invention is to provide a kind of and can reduce clamping pressure and unlikely when causing substrate surface generation hallrcuts, the packing colloid that the glue that still can prevent to overflow takes place has the semiconductor package part of shoulder.
A further object of the present invention is to provide a kind of semiconductor package part of packing colloid tool shoulder that can improve the manufactured goods qualification rate and need not remove the subsequent treatment (Post-Treatment) of the glue that overflows.
For reaching above-mentioned and other purpose of the present invention, the semiconductor package part of packing colloid tool shoulder of the present invention comprises: a substrate, the one glutinous chip that places on this substrate and electrically connect with this substrate, and the packing colloid in order to the surface that coats this chip and part substrate, and this packing colloid is in extending outward a shoulder with the substrate joint.
The formation of this shoulder is because go out in the patrix (Upper Mold) of the mould of this packing colloid with compression molding, be outward extended with recess (Recess) on the opening edge of its die cavity of offering (Cavity), the Ccope closing machine that makes mould to counterdie (Lower Mold) go up with clamping (Clamp) live this substrate and injecting glue to the die cavity of patrix after, the potting resin mould of melting flows when flowing into this recess can quicken to absorb the heat of mould because of runner narrows, cause the viscosity of mould stream to become big and its flow velocity is slowed down, thereby avoid resin mold slime flux glue between the composition surface of substrate and patrix; After mold process finished, the potting resin that flows in this recess was that curing molding is the shoulder that outwards stretches out from the bottom of this packing colloid.
The formation of this recess also can be staircase, make concave depth from interior (with the die cavity joint) and outside (away from die cavity) successively decrease gradually, the potting resin mould stream heat absorption speed that flows in the injecting glue operation in this recess that is staircase is speeded and further moderate flow velocity, and more can effectively avoid resin mold stream that the situation of excessive glue takes place.
Description of drawings
Below now to be described in further detail characteristics of the present invention and effect than Cui concrete example conjunction with figs..
Fig. 1 is the generalized section of the semiconductor package part of first embodiment of the invention;
Fig. 2 is the vertical view of the semiconductor package part of first embodiment of the invention;
Fig. 3 is that the gluing of first embodiment of the invention has the substrate of chip to be clamped on generalized section in the mould;
Fig. 4 is the generalized section of the semiconductor package part of second embodiment of the invention;
Fig. 5 is that the gluing of second embodiment of the invention has the substrate of chip to be clamped on generalized section in the mould; And
Fig. 6 is the generalized section that known semiconductor package part places mould.
The drawing symbol description
10 chips, 11 substrates
12 patrixes, 13 counterdies
14 die cavitys, 15 packing colloids
2,2 ' semiconductor package part 3,3 ' substrate
30 upper surfaces, 31 lower surfaces
4 chips, 5 gold threads
6 packing colloids 60,60 ' shoulder
7 soldered balls 8,8 ' patrix
80,80 ' die cavity 81,81 ' recess
9 counterdies
Embodiment
As shown in Figure 1, the semiconductor package part 2 of first embodiment of the invention comprises: a substrate 3, the glutinous chip of being located on this substrate 34, in order to electrically connect the many piece gold threads 5 of this chip 4 to the substrate 3, in order to the packing colloid 6 of the part of the upper surface 30 that coats this chip 4, gold thread 5 and substrate 3, and produce the medium that electrically connects and plant a plurality of soldered balls 7 on the lower surface 31 that is welded in this substrate 3 with extraneous as chip 4.These substrate 3 structures and prior art are as broad as long, so do not give unnecessary details for literary composition in addition at this.The BGA semiconductor package part of first embodiment of the invention is only released structure characteristic of the present invention in order to example, but not limit the category that the present invention is suitable for this, in fact, the BGA semiconductor package part of other type also is suitable for, as CSP (Chip Scale Package) semiconductor package part, TFT (Thin Fine Tape) BGA semiconductor package part, LOC BGA semiconductor package part or Cavity-up-type BGA semiconductor package part etc.
The encapsulation process of first embodiment of the invention is electrically connect this chip 4 and substrate 3 in this chip 4 of gluing on the substrate 3 and with gold thread 5 after, has the substrate 3 of chip 4 to be clamped between the patrix 8 and counterdie 9 that mold pressing uses, to carry out mold pressing, as shown in Figure 3 this gluing.This patrix 8 has a die cavity 80 in order to form this packing colloid 6, and is outward extended with a recess 81 on the opening edge of die cavity 80, in order to form a Road narrows structure of leading to die cavity 80 at this patrix 8 and 3 of substrates.After mold process begins, when the potting resin mould of injection die cavity 80 flows in the Road narrows structure that this recess 81 of inflow is limited, can accelerate heat absorption speed because of runner narrows, thereby the viscosity that makes potting resin mould stream becomes big, and then slow down the flow velocity of mould stream, satisfy to such an extent that avoid mould slime flux glue to the surface that substrate 3 covers for packing colloid 6.Because encapsulating mould used in the present invention must be avoided the generation of excessive glue, so the clamping pressure of patrix 8 institute's palpus during with counterdie 9 matched moulds is minimized, the clamping pressure of the substrate that puts on 3 is unlikely excessive, can prevent that then substrate 3 from having the generation of hallrcuts because of pressurized, so the semiconductor package part made from patrix 8 and counterdie 9 has higher qualification rate, than the reliability of Cui, and needn't remove the subsequent treatment of the glue that overflows, thus can the simplification process and reduce manufacturing cost.
After above-mentioned molding operation was finished, the potting resin in the recess 81 of this inflow patrix 8 promptly can be solidified into the shoulder (Flange) 60 that outwards is stretched on these packing colloid 6 bottoms, as shown in Figures 1 and 2.
The person is the generalized section of the semiconductor package part of the second embodiment of the present invention as shown in Figure 4.Roughly be same as first embodiment on the semiconductor package part 2 ' structure of this second embodiment, after difference only was the packing colloid 6 ' curing molding of this second embodiment, the shoulder 60 ' that links to each other of one was stepped with it.The moulding of this stepped shoulder 60 ' makes the opening edge of the die cavity 80 ' of patrix 8 ' form the stepped recess 81 ' of outside stretching, extension, as shown in Figure 5; Thereby, the degree of depth of this recess 81 ' is outwards successively decreased gradually from die cavity 80 ', with in the mold pressing processing procedure, the speed that flows into the potting resin mould stream heat absorption in this recess 81 ' can increase progressively gradually, the flow velocity that makes potting resin mould stream successively decreases with the degree of depth of recess 81 ' and slows down gradually, avoids the effect of glue of overflowing so can further increase, and reduce clamping pressure and prevent that effectively the surface of substrate 3 ' from producing hallrcuts.
Above-mentioned specific embodiment is only in order to describe characteristics of the present invention and effect in detail, but but not in order to qualification practical range of the present invention, do not breaking away under the disclosed technical scope and spirit, the equivalence that any utilization the present invention is finished changes and modifies, and is all still contained by claim of the present invention.
Claims (10)
1. a packing colloid has the semiconductor package part of shoulder, comprising:
One substrate;
The one glutinous chip that places on this substrate and electrically connect with this substrate; And
One packing colloid, and this packing colloid and be outward extended with a shoulder in itself and substrate join in order to the part surface that coats this chip and substrate.
2. semiconductor package part as claimed in claim 1, wherein, this shoulder is that the recess that forms that stretches out on the opening edge in order to the die cavity that forms this packing colloid by mould is formed.
3. semiconductor package part as claimed in claim 1, wherein, this shoulder has uniform thickness.
4. semiconductor package part as claimed in claim 1, wherein, this shoulder becomes stepped.
5. mould that encapsulates usefulness comprises:
One patrix has a die cavity, and stretches out in the opening edge of this die cavity and to form a recess; And
One counterdie, in order to this Ccope closing machine after carry out mold process.
6. mould as claimed in claim 5, wherein, this recess has uniform depth.
7. mould as claimed in claim 5, wherein, this recess forms stepped.
8. a packing colloid has the manufacture method of the semiconductor package part of shoulder, and its step comprises:
Prepare a substrate;
On this substrate, stick and put a chip, and electrically connect this chip and this substrate;
This glutinous substrate that is equipped with chip is clamped between the patrix and counterdie that mold pressing uses, and carrying out mold pressing, and the die cavity opening edge of this patrix stretches out and forms a recess;
Mould stream with a packing colloid injects this die cavity, and makes the mould stream of this packing colloid inject this recess and the formed space of substrate; And
Finish mold pressing, so that the interior mould stream of die cavity forms a cure package colloid, and the shoulder that interior mould stream this packing colloid of formation of this recess and this substrate join are stretched out.
9. manufacture method as claimed in claim 8, wherein, this shoulder has uniform thickness.
10. manufacture method as claimed in claim 8, wherein, this shoulder becomes stepped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001324365A CN1167123C (en) | 2000-11-17 | 2000-11-17 | Semiconductor package whose package sealant possesses shoulder portion and mould for packaging said semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001324365A CN1167123C (en) | 2000-11-17 | 2000-11-17 | Semiconductor package whose package sealant possesses shoulder portion and mould for packaging said semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1354511A CN1354511A (en) | 2002-06-19 |
| CN1167123C true CN1167123C (en) | 2004-09-15 |
Family
ID=4595164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001324365A Expired - Fee Related CN1167123C (en) | 2000-11-17 | 2000-11-17 | Semiconductor package whose package sealant possesses shoulder portion and mould for packaging said semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1167123C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3689694B2 (en) * | 2002-12-27 | 2005-08-31 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
| CN105269758B (en) * | 2014-07-15 | 2018-01-02 | 清华大学 | Semiconductor packaging mold, encapsulating structure and method for packing |
| CN105244292B (en) * | 2015-11-04 | 2018-07-20 | 上海凯虹电子有限公司 | The method of plastic package die and removal excessive glue with irregular shape tooth socket |
| CN111029265B (en) * | 2019-12-26 | 2021-11-23 | 珠海格力电器股份有限公司 | Plastic package mold and method for preventing QFN (quad Flat No lead) mold package frame from warping |
-
2000
- 2000-11-17 CN CNB001324365A patent/CN1167123C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1354511A (en) | 2002-06-19 |
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Granted publication date: 20040915 Termination date: 20141117 |
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