CN116707497A - Tunable low-speed clock duty cycle skew trimming circuit, method and timing circuit - Google Patents
Tunable low-speed clock duty cycle skew trimming circuit, method and timing circuit Download PDFInfo
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- CN116707497A CN116707497A CN202310986956.2A CN202310986956A CN116707497A CN 116707497 A CN116707497 A CN 116707497A CN 202310986956 A CN202310986956 A CN 202310986956A CN 116707497 A CN116707497 A CN 116707497A
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- 238000006243 chemical reaction Methods 0.000 description 5
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- 230000009286 beneficial effect Effects 0.000 description 1
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- 230000010076 replication Effects 0.000 description 1
- 230000003362 replicative effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The application discloses a tunable low-speed clock duty cycle deflection trimming circuit, a method and a timing circuit, wherein the trimming circuit comprises a variable proportion current mirror, a comparator, an inverter, a driving module, a PMOS (P-channel metal oxide semiconductor) switching tube, a first NMOS (N-channel metal oxide semiconductor) switching tube, a second NMOS switching tube and a capacitor, wherein a signal input end of the variable proportion current mirror is connected with a control signal, a signal output end is connected with a grid electrode of the PMOS switching tube, a source electrode of the PMOS switching tube is connected with working voltage, and a drain electrode of the PMOS switching tube is connected with a source electrode of the first NMOS switching tube, a non-inverting input end of the comparator and a first end of the capacitor; the grid electrode of the first NMOS switch tube is connected with a clock input signal, the inverting input end of the comparator is connected with a reference voltage, the signal output end of the inverter is connected with the signal input end of the driving module, and the signal output end of the driving module outputs a clock output signal with a duty ratio subjected to trimming. The application can adjust the skew trim ratio and strength to achieve the desired duty cycle.
Description
Technical Field
The application relates to the technical field of clock chip design, in particular to a tunable low-speed clock duty cycle deflection trimming circuit, a method and a timing circuit.
Background
The low-speed clock has more common application in analog circuits, and the low power consumption of the simple mechanism can be applied to circuits with low requirement on clock signals, such as modules of direct current converters (DC/DC).
The application patent CN110830009B discloses a control device and a control method of a multipath DC/DC converter, and relates to the technical field of electronic control, wherein the device comprises: each output end of the second number of output ends of the PWM module is respectively connected with the third number of delay modules of the first number of delay modules in series, each output end of the second number of output ends of the PWM module and each output end of the first number of delay modules are respectively connected with the fourth number of switches of the multi-channel DC/DC converter, the PWM module is used for outputting the second number of clock signals with the same frequency and different phases, and the delay modules are used for delaying the clock signals output by the output ends of the PWM module connected in series with the delay modules to obtain delay signals.
The patent CN102739248B discloses a clock signal generating circuit, and an object thereof is to provide a clock signal generating circuit which is started at a high speed from the power-on time and can continue generation of a clock signal even if external disturbance occurs. In the present application, when a low-speed clock signal and a high-speed clock signal are generated, respectively, a 1 st oscillation clock signal generated in a 1 st oscillation circuit which is an oscillation source of the high-speed clock signal is outputted as the high-speed clock signal. When the 2 nd oscillation clock signal is transmitted from the 2 nd oscillation circuit serving as the oscillation source of the low-speed clock signal, the 2 nd oscillation clock signal is output as the low-speed clock signal, and when the 2 nd oscillation clock signal is not transmitted, the frequency-divided clock signal obtained by dividing the 1 st oscillation clock signal is output as the low-speed clock signal.
The application patent CN105245203B discloses a high-precision low-speed clock duty ratio detection system and a method, wherein the system comprises a synchronous unit, a pulse conversion unit and a pulse conversion unit, wherein the synchronous unit is used for synchronously processing an asynchronously input duty ratio signal and outputting a processing result to the pulse conversion unit; a pulse conversion unit for performing pulse conversion on an input duty ratio signal; a frequency judging unit dividing an input duty ratio signal into a high frequency signal and a low frequency signal; a duty sampling unit sampling the duty signal according to whether the input duty signal is a high frequency signal or a low frequency signal; a divider for obtaining the duty ratio and outputting the duty ratio; and a clock frequency dividing unit for providing clock signals to the system.
However, the duty cycle of the clock signal is skewed with a high probability after passing through the driving circuit or logic circuit. As shown in fig. 1, in a timing circuit in an analog circuit, an Oscillator (OSC) is generally used to generate a triangular wave, and the triangular wave passes through a digital Logic gate (Logic) to generate a clock square wave signal, and after passing through an N-stage driving circuit (Drivers), the duty cycle of the clock signal generates a large skew (for example, 50% of the duty cycle drops to 30% and even disappears), and at this time, the clock is sent to a direct current converter (DC/DC) as the clock signal, which greatly affects the operating state and performance of the direct current converter (DC/DC).
Disclosure of Invention
In order to solve the problems, the application provides a tunable low-speed clock duty cycle skew trimming circuit, a method and a timing circuit, wherein the proportion and the intensity of skew trimming can be arbitrarily changed to obtain an ideal duty cycle.
The technical scheme adopted by the application is as follows:
a tunable low-speed clock duty cycle skew trimming circuit comprises a variable proportion current mirror, a comparator, an inverter, a driving module, a PMOS switching tube, a first NMOS switching tube, a second NMOS switching tube and a capacitor, wherein:
the signal input end of the variable proportion current mirror is connected with a control signal, the signal output end is connected with the grid electrode of the PMOS switching tube, the source electrode of the PMOS switching tube is connected with working voltage, and the drain electrode of the PMOS switching tube is connected with the source electrode of the first NMOS switching tube, the non-inverting input end of the comparator and the first end of the capacitor;
the grid electrode of the first NMOS switch tube is connected with a clock input signal CLK_PRE, and the drain electrode and the second end of the capacitor are grounded;
the inverting input end of the comparator is connected with the reference voltage V REF The signal output end is connected with the signal input end of the inverter and the source electrode of the second NMOS switch tube, the grid electrode of the second NMOS switch tube is also connected with the clock input signal CLK_PRE, and the drain electrode is grounded; the inverter is provided withThe signal output end is connected with the signal input end of the driving module, and the signal output end of the driving module outputs a clock output signal CLK_OUT subjected to duty cycle trimming.
Further, when the duty ratio of the clock output signal clk_out is not equal to the target value, the duty ratio is adjusted to the target value by a preset method including adjusting the reference voltage V of the comparator REF 。
Further, the preset method further comprises adjusting the scaling factor of the variable-ratio current mirror.
Further, the preset method further comprises adjusting the current output by the PMOS switching tube.
Further, when the duty ratio of the clock output signal CLK_OUT is less than the target value, the reference voltage V of the comparator is increased REF Decreasing the scaling factor of the variable ratio current mirror or decreasing the current output by the PMOS switching transistor to increase the high level time, thereby increasing the duty cycle, wherein the increased high level time is:
T ON_add =C1*V REF /(N*I1)
wherein, C1 is the capacitance of the capacitor, N is the proportionality coefficient of the variable proportionality current mirror, and I1 is the current output by the PMOS switch tube.
A tunable low-speed clock duty cycle skew trimming method comprising the steps of:
s1, when a clock input signal CLK_PRE is at a high level, the first NMOS switch tube and the second NMOS switch tube are conducted, and the signal output end of the comparator is grounded, so that the clock output signal CLK_OUT output by the driving module is at the high level;
s2, when the clock input signal CLK_PRE becomes low level, the first NMOS switch tube and the second NMOS switch tube are closed, the charges of the capacitor begin to accumulate gradually, the voltage V1 at the same phase end of the comparator rises gradually, but is still smaller than the reference voltage V at the opposite phase end REF So the clock output signal clk_out is still high; when the in-phase terminal voltage V1 of the comparator increases to exceed the reference voltage V REF At this time, the comparator output goes high and the clock output signal CLK_OUT goes low until the clock inputThe input signal clk_pre goes high again;
s3, judging whether the duty ratio of the clock output signal CLK_OUT is equal to a target value, and if so, repeating the step S1 and the step S2; otherwise, the duty cycle is made equal to the target value by a preset method including adjusting the reference voltage V of the comparator REF Step S1 and step S2 are repeated again.
Further, in step S3, the preset method further includes adjusting a scaling factor of the variable-ratio current mirror.
Further, in step S3, the preset method further includes adjusting the current output by the PMOS switching transistor.
Further, when the duty ratio of the clock output signal CLK_OUT is less than the target value, the reference voltage V of the comparator is increased REF Decreasing the scaling factor of the variable ratio current mirror or decreasing the current output by the PMOS switching transistor to increase the high level time, thereby increasing the duty cycle, wherein the increased high level time is:
T ON_add =C1*V REF /(N*I1)
wherein, C1 is the capacitance of the capacitor, N is the proportionality coefficient of the variable proportionality current mirror, and I1 is the current output by the PMOS switch tube.
The timing circuit comprises the low-speed clock duty cycle deflection trimming circuit, and further comprises an oscillator, a digital logic gate circuit, a multi-stage driving circuit and a direct current converter, wherein the oscillator, the digital logic gate circuit, the multi-stage driving circuit, the low-speed clock duty cycle deflection trimming circuit and the direct current converter are electrically connected in sequence.
The application has the beneficial effects that:
the low-speed clock duty cycle deflection trimming circuit, the low-speed clock duty cycle deflection trimming method and the timing circuit can change the proportion and the intensity of duty cycle trimming through various methods, for example, the reference voltage of a comparator, the proportion coefficient of a variable proportion current mirror or the current output by a PMOS switching tube and the like are adjusted, and finally the ideal duty cycle is obtained.
Drawings
Fig. 1 is a schematic diagram of a timing circuit for generating a skew in the duty cycle of a clock signal.
Fig. 2 is a schematic diagram of a low-speed clock duty cycle skew trimming circuit according to embodiment 1 of the present application.
Fig. 3 is a schematic diagram of a timing circuit according to embodiment 2 of the present application.
Description of the drawings: OSC-oscillator, logic-digital Logic gate, driver-multistage driver circuit, trimming-Duty cycle skew Trimming circuit, DC/DC-DC converter, duty-Duty cycle; the power supply circuit comprises a CM-variable proportion current mirror, a COMP-comparator, an INV-inverter, a Driver-driving module, an NMOS 1-first switching tube, an NMOS 2-second switching tube, a PMOS-third switching tube, a C1-capacitor and a V1-comparator in-phase terminal voltage.
Detailed Description
Specific embodiments of the present application will now be described in order to provide a clearer understanding of the technical features, objects and effects of the present application. It should be understood that the particular embodiments described herein are illustrative only and are not intended to limit the application, i.e., the embodiments described are merely some, but not all, of the embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
Example 1
As shown in fig. 1, in the timing circuit in the analog circuit, the oscillator OSC is generally used to generate a triangular wave, and the triangular wave passes through the digital Logic gate Logic to generate a clock square wave signal, and after passing through the N-stage driving circuit Drivers, the duty cycle of the clock signal generates a larger skew (for example, 50% of the duty cycle drops to 30% and even disappears), and at this time, the clock is sent to the DC/DC converter as the clock signal, so that the working state and performance of the DC/DC converter are greatly affected.
Therefore, the embodiment provides a tunable low-speed clock duty cycle skew trimming circuit, as shown in fig. 2, including a variable ratio current mirror CM, a comparator COMP, an inverter INV, a driving module Driver, a first switching transistor NMOS1, a second switching transistor NMOS2, a third switching transistor PMOS, and a capacitor C1, which are specifically described below.
The variables involved in fig. 2, such as signal, voltage, etc., include: clock input signal CLK_PRE, clock output signal CLK_OUT, control signal Control<1:N>Control voltage V control Comparator in-phase terminal voltage V1, increased high level time T ON_add 。
The variable proportion current mirror CM is a mirror constant current source with an adjustable current replication proportion, and is used for replicating an input current according to a Control signal Control <1:n > and a scaling factor N to generate a bias current n×i1. The signal input end of the variable proportion current mirror CM is connected with a control signal, the signal output end is connected with the grid electrode of a third switching tube PMOS, the source electrode of the third switching tube PMOS is connected with working voltage, and the drain electrode of the third switching tube PMOS is connected with the source electrode of the first switching tube NMOS1, the non-inverting input end of the comparator COMP and the first end of the capacitor C1.
The gate of the first switch NMOS1 is connected to the clock input signal CLK_PRE, and the drain and the second end of the capacitor C1 are grounded. The inverting input terminal of the comparator COMP is connected to the reference voltage V REF The signal output end is connected with the signal input end of the inverter INV and the source electrode of the second switching tube NMOS2, the grid electrode of the second switching tube NMOS2 is also connected with the clock input signal CLK_PRE, and the drain electrode is grounded; the signal output end of the inverter INV is connected with the signal input end of the driving module Driver, and the signal output end of the driving module Driver outputs a clock output signal CLK_OUT subjected to duty cycle trimming.
Correspondingly, the embodiment also provides a tunable low-speed clock duty cycle skew trimming method, which comprises the following steps:
s1, when a clock input signal CLK_PRE is at a high level, a first switching tube NMOS1 and a second switching tube NMOS2 are conducted, and a signal output end of a comparator COMP is grounded, so that a clock output signal CLK_OUT output by a driving module Driver is at the high level;
s2 when the clock input signal CLK_PRE goes low, the first and second switching transistors NMOS1 and NMOS2 are turned off, so that the charge of the capacitor C1 begins to accumulate gradually, resulting in the voltage V1 at the non-inverting terminal of the comparator COMP rising gradually, but still being smaller than the reference voltage V at the inverting terminal REF Thus the clock output signal CLK_OUT is still high; when the in-phase terminal voltage V1 of the comparator COMP increases to exceed the reference voltage V REF At this time, the comparator COMP output goes high, the clock output signal clk_out goes low, until the clock input signal clk_pre goes high again;
s3, judging whether the duty ratio of the clock output signal CLK_OUT is equal to a target value, and if so, repeating the step S1 and the step S2; otherwise, the duty ratio is equal to the target value through a preset method, and the steps S1 and S2 are repeated.
Preferably, in step S3, the preset method includes adjusting the reference voltage V of the comparator COMP REF、 The scaling factor of the variable scaling current mirror CM or the current output by the third switching tube PMOS.
Preferably, the reference voltage V of the comparator COMP is increased when the duty cycle of the clock output signal CLK_OUT is less than the target value REF Decreasing the scaling factor of the variable ratio current mirror CM or decreasing the current output by the third switching transistor PMOS to increase the high level time, thereby increasing the duty cycle, wherein the increased high level time is:
T ON_add =C1*V REF /(N*I1)
wherein, C1 is the capacitance of the capacitor C1, N is the proportionality coefficient of the variable proportionality current mirror CM, and I1 is the current output by the third switch tube PMOS.
Example 2
This example is based on example 1:
as shown in fig. 3, the present embodiment provides a timing circuit, which includes the duty cycle skew Trimming circuit triming of embodiment 1, and further includes an oscillator OSC, a digital Logic gate Logic, a multi-stage driving circuit driver, and a DC converter DC/DC, where the oscillator OSC, the digital Logic gate Logic, the multi-stage driving circuit driver, the duty cycle skew Trimming circuit triming, and the DC converter DC/DC are electrically connected in sequence.
In the embodiment, a duty cycle skew Trimming circuit Trimming is added to the output end of the clock signal CLK after passing through the multistage driving circuit Drivers, and the Trimming proportion and strength of the clock signal CLK can be changed by the voltage control signal of the duty cycle skew Trimming circuit Trimming so that the duty cycle finally reaches an expected value.
It should be noted that, for the sake of simplicity of description, the foregoing method embodiments are expressed as a series of combinations of actions, but it should be understood by those skilled in the art that the present application is not limited by the order of actions described, as some steps may be performed in other order or simultaneously according to the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.
Claims (10)
1. The utility model provides a skew trimming circuit of tunable low-speed clock duty cycle which characterized in that includes variable proportion current mirror, comparator, inverter, drive module, PMOS switch tube, first NMOS switch tube, second NMOS switch tube and condenser, wherein:
the signal input end of the variable proportion current mirror is connected with a control signal, the signal output end is connected with the grid electrode of the PMOS switching tube, the source electrode of the PMOS switching tube is connected with working voltage, and the drain electrode of the PMOS switching tube is connected with the source electrode of the first NMOS switching tube, the non-inverting input end of the comparator and the first end of the capacitor;
the grid electrode of the first NMOS switch tube is connected with a clock input signal CLK_PRE, and the drain electrode and the second end of the capacitor are grounded;
the inverting input end of the comparator is connected with the reference voltage V REF The signal output end is connected with the signal input end of the inverter and the source electrode of the second NMOS switch tube, the grid electrode of the second NMOS switch tube is also connected with the clock input signal CLK_PRE, and the drain electrode is grounded; the signal output end of the inverter is connected with the signal input end of the driving module, and the signal output end of the driving module outputs a clock output signal CLK_OUT with a modified duty ratio.
2. The tunable low-speed clock duty cycle skew trimming circuit according to claim 1, wherein when a duty cycle of the clock output signal clk_out is not equal to a target value, the duty cycle is adjusted to the target value by a preset method, the method comprisingThe preset method comprises adjusting reference voltage V of the comparator REF 。
3. The tunable low-speed clock duty cycle skew trimming circuit of claim 2, wherein the preset method further comprises adjusting a scaling factor of a variable scaling current mirror.
4. The tunable low-speed clock duty cycle skew trimming circuit of claim 2, wherein the preset method further comprises adjusting the current output by the PMOS switching transistor.
5. The tunable low-speed clock duty cycle skew trimming circuit of claim 1, wherein the reference voltage V of the comparator is increased when the duty cycle of the clock output signal clk_out is less than the target value REF Decreasing the scaling factor of the variable ratio current mirror or decreasing the current output by the PMOS switching transistor to increase the high level time, thereby increasing the duty cycle, wherein the increased high level time is:
T ON_add =C1*V REF /(N*I1)
wherein, C1 is the capacitance of the capacitor, N is the proportionality coefficient of the variable proportionality current mirror, and I1 is the current output by the PMOS switch tube.
6. A tunable low-speed clock duty cycle skew trimming method applied to the tunable low-speed clock duty cycle skew trimming circuit of claim 1, the trimming method comprising the steps of:
s1, when a clock input signal CLK_PRE is at a high level, the first NMOS switch tube and the second NMOS switch tube are conducted, and the signal output end of the comparator is grounded, so that the clock output signal CLK_OUT output by the driving module is at the high level;
s2, when the clock input signal CLK_PRE becomes low level, the first NMOS switch tube and the second NMOS switch tube are closed, the charges of the capacitor begin to accumulate gradually, and the voltage V1 at the same phase end of the comparator rises gradually, but stillReference voltage V smaller than the inverting terminal REF So the clock output signal clk_out is still high; when the in-phase terminal voltage V1 of the comparator increases to exceed the reference voltage V REF At this time, the comparator output goes high, the clock output signal clk_out goes low, until the clock input signal clk_pre goes high again;
s3, judging whether the duty ratio of the clock output signal CLK_OUT is equal to a target value, and if so, repeating the step S1 and the step S2; otherwise, the duty cycle is made equal to the target value by a preset method including adjusting the reference voltage V of the comparator REF Step S1 and step S2 are repeated again.
7. The method of claim 6, wherein in step S3, the presetting method further comprises adjusting a scaling factor of a variable-scale current mirror.
8. The method for skew trimming of a duty cycle of a tunable low-speed clock of claim 6, wherein in step S3, said preset method further comprises adjusting a current output by a PMOS switching transistor.
9. The method of claim 6, wherein the reference voltage V of the comparator is increased when the duty cycle of the clock output signal clk_out is less than the target value REF Decreasing the scaling factor of the variable ratio current mirror or decreasing the current output by the PMOS switching transistor to increase the high level time, thereby increasing the duty cycle, wherein the increased high level time is:
T ON_add =C1*V REF /(N*I1)
wherein, C1 is the capacitance of the capacitor, N is the proportionality coefficient of the variable proportionality current mirror, and I1 is the current output by the PMOS switch tube.
10. The timing circuit is characterized by comprising the low-speed clock duty cycle deflection trimming circuit according to any one of claims 1-5, and further comprising an oscillator, a digital logic gate circuit, a multi-stage driving circuit and a direct current converter, wherein the oscillator, the digital logic gate circuit, the multi-stage driving circuit, the low-speed clock duty cycle deflection trimming circuit and the direct current converter are electrically connected in sequence.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310986956.2A CN116707497B (en) | 2023-08-08 | 2023-08-08 | Tunable low-speed clock duty cycle skew trimming circuit, method and timing circuit |
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| CN202310986956.2A CN116707497B (en) | 2023-08-08 | 2023-08-08 | Tunable low-speed clock duty cycle skew trimming circuit, method and timing circuit |
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| US20170054372A1 (en) * | 2015-08-20 | 2017-02-23 | Samsung Electronics Co., Ltd. | Internal voltage trimming device and semiconductor integrated circuit including the same |
| CN105763193A (en) * | 2016-02-14 | 2016-07-13 | 中国电子科技集团公司第二十四研究所 | Clock circuit used for high-speed high-precision SHA-less pipelined analog-to-digital converter |
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