CN116682843B - Nanowire light-emitting device and preparation method thereof - Google Patents
Nanowire light-emitting device and preparation method thereof Download PDFInfo
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Abstract
The application provides a nanowire luminescent device and a preparation method thereof, wherein a nanowire at least comprising a luminescent region is integrated on a Si (100) substrate to form a high-precision nanowire luminescent device, so that the technical prejudice that heterogeneous [100] nanowires cannot be formed by self-assembly is overcome, the technical bottleneck of a silicon-based integrated nanowire luminescent array is solved, and image display can be realized by a single chip. The nanowire luminescent device formed based on the application does not need a huge transfer technology, does not need additional leads or welding spots to connect an array and a circuit, breaks through the problem of integration of the device and the circuit, and has the advantages of ultrahigh pixel point, high brightness, high contrast, small volume, low power consumption, independent driving, convenience for portable use and the like.
Description
Technical Field
The application belongs to a semiconductor light-emitting device, in particular to a nanowire light-emitting device and a preparation method thereof, and particularly relates to a nanowire light-emitting device integrated on a CMOS (complementary metal oxide semiconductor) device.
Background
Aiming at display equipment, the Micro-LED has the characteristics of high resolution, low power consumption, high brightness, high contrast, high color saturation, high reaction speed, thin thickness, long service life and the like, the power consumption can be as low as 10% of that of an LCD (liquid crystal display) and 50% of that of an OLED, and the Micro-LED is the next generation display technology expected in the industry. The industrialization of Micro-LEDs is realized independently of CMOS silicon-based integration technology, and at present, more than 90% of integrated circuit chips all use CMOS process technology.
CMOS (Complementary Metal Oxide Semiconductor ) is an integrated circuit formed by fabricating NMOS and PMOS on the same chip, and CMOS process technology is to use complementary symmetrical circuits to configure and connect PMOS and NMOS to form a logic circuit, achieving a static power consumption near zero. CMOS process technology has been developed for 60 years, and has the advantages of high integration level, strong anti-interference capability, high speed, low static power consumption, wide power supply voltage range, wide output voltage range, etc. Because of its many advantages, it is the first choice for digital, analog and digital-to-analog hybrid circuits, and more than 90% of integrated circuit chips currently use CMOS process technology. While the Si (100) substrate is the dominant substrate in Si integrated circuit technology, this illustrates the potential and value of the Si (100) substrate in the direction of implementing device miniaturization for multi-functional chip integration.
The Si (100) substrate is the dominant substrate of Si integrated circuit technology, especially CMOS, and the obtaining of epitaxial hetero-nanowires on the Si (100) substrate is crucial for realizing a silicon-based integrated light emitting array. The method can not only completely avoid the problems of high cost, edge effect and the like caused by huge transfer, but also realize the independent control of each pixel point. However, there is a problem in that since the growth direction of the nanowire is along the crystal plane direction of the substrate, the nanowire does not have the [100] direction preferential nucleation growth on the Si (100) substrate, i.e., the nanowire perpendicular to the base cannot be self-assembled.
Based on the above general knowledge, to date, the connection of the industrialized Micro-LEDs to the CMOS circuit adopts a huge transfer technology, that is, the Micro-LEDs and the CMOS circuit are grown on substrates of different materials respectively, when the Micro-LEDs are grown on a substrate (such as a sapphire substrate), a large number of Micro-LEDs need to be separated from the substrate and transferred to a target substrate or a driving circuit board through a certain high-precision device, multiple transfers (at least from the sapphire substrate to a temporary substrate to a new substrate) are required, the quantity of chips transferred each time is very large, and the requirements on stability and precision of the transfer process are very high, and serious side wall loss and edge effect are caused. For R/G/B full-color display, since each process can only produce chips with one color, red/green/blue chips are required to be transferred respectively, and very accurate processes are required to position the chips, so that the transfer process difficulty is greatly increased. Micro-LEDs are only a few microns thick, and the difficulty in accurately placing them on the target substrate is very high, and the chip size and pitch are small, and it is also a challenge to attach the chip to the circuit. In addition, since the Micro LED is extremely small in size, it is difficult to use the conventional test equipment, and how to detect and repair the defective pixels in millions or even tens of millions of chips is a great challenge, and how to replace the defective pixels after picking out defective dies by the detection technology is also an indispensable technology. Therefore, the Micro-LED array display cost is high, time and labor are wasted, the precision is low, and the market popularization and the development of wearing equipment are hindered.
Disclosure of Invention
The application aims at overcoming the technical prejudice aiming at the defects of the prior art and directly integrating a Si (100) -based CMOS device and a luminescent nanowire to obtain a high-precision nanowire luminescent device. The application does not need a huge transfer technology, does not need additional leads or welding spots to connect the array and the circuit, breaks through the problem of integration of devices and circuits, and has the advantages of ultrahigh pixel point, high brightness, high contrast, small volume, low power consumption, independent driving, convenience for portable use and the like.
The application adopts the following technical scheme: a nanowire light emitting device is characterized in that nanowires are integrally grown in an active area of a CMOS device, and high integration of a circuit system such as a driving circuit and a control circuit and a light emitting array is realized. The CMOS device substrate is a Si (100) substrate; wherein the nanowire comprises at least one light emitting region.
The CMOS device comprises more than two Si (100) MOS devices, and at least one MOS is an independent control unit. The MOS devices can be classified into N-channel enhancement type, N-channel depletion type, P-channel enhancement type and P-channel depletion type. The MOS device comprises a source electrode, a drain electrode and a grid electrode. Through the design of the CMOS drive circuit, the luminous performance of the nanowire array growing on the MOS device can be independently controlled, the visual transmission of various patterns, numbers, characters and the like is realized, and the display application of near-to-eye, AR/VR, an automobile display screen and the like is facilitated. In some embodiments of the present application, a plurality of MOS devices may also perform association control, and a specific control program may be implemented through a circuit arrangement.
The CMOS device comprises more than two Si (100) MOS devices, and single or multiple nanowires are grown in an active region of the MOS. For a plurality of nanowires contained on one MOS, adjacent nanowires in one MOS control unit can be made of the same material or different materials, and the nanowires in the adjacent MOS control units can be arranged and distributed in the same material or different materials. By the design of the nanowire material, a single-color or multi-color full-color luminous array is realized, and the color can cover multi-color colors such as red, orange, yellow, green, blue and purple.
In the application, the nanowire and the Si (100) substrate are made of heterogeneous materials. The nanowire material adopts a semiconductor material system, so that the ultra-long practical service life, the stable luminous efficiency and the stable luminous color of the luminous array are realized. And the nanowire and the Si (100) substrate are made of heterogeneous materials, so that the limitation that the nanowire can only be made of silicon materials is broken through.
In the application, the nanowire at least comprises two light-emitting areas, and the light-emitting areas are arranged along the radial direction or the axial direction of the nanowire. The number of the luminous areas can be more than 50 through controllable synthesis of the nanowires, and is far higher than the luminous number of the thin film luminous array, so that the luminous brightness of the nanowire luminous array can be adjusted to be high.
The light-emitting area is a nanowire which does not contain a PN junction or a nanowire PN junction area; the nanowire PN junction region is formed by quantum wells, quantum dots or combination of the quantum wells and the quantum dots.
The application also provides a preparation method of the nanowire light-emitting device, which at least comprises the following steps: preparation of nanowires on a Si (100) substrate and construction of CMOS circuits; the sequence of the two links can be adjusted according to actual working conditions, for example, a CMOS circuit is formed on a Si (100) substrate, and then a (111) crystal face is cut out for nanowire growth; or cutting out a (111) crystal face on the Si (100) substrate, forming a CMOS circuit on the Si (111) substrate, and then preparing the nanowire.
Wherein, the preparation of the nanowire on the Si (100) substrate comprises the following steps:
cutting out a (111) crystal face on a Si (100) substrate, and growing a nanowire on the (111) crystal face;
alternatively, nanowires are grown directly on Si (100) substrates.
The (111) crystal face is cut out on the Si (100) substrate, and the nanowire grows on the (111) crystal face because the nanowire does not have the [100] direction preferential nucleation growth, and by the technical method, good nanowire crystal quality can be realized on the Si (100), and the luminous efficiency is improved. The technical method for directly growing the nanowire on the Si (100) substrate avoids the treatment of the silicon (100) wafer, but the nanowire growth constraint is needed to be carried out through the related technical method later, so that the nanowire is perpendicular to the Si (100) substrate. Both techniques have their own advantages and disadvantages, but both propose a process on which to integrate CMOS devices with nanowire light emitting devices.
In some embodiments of the application, the specific process of CMOS circuit construction is as follows:
depositing a first layer of photoresist;
masking, exposing and etching to form an opening structure;
stripping the first photoresist layer;
filling a first insulating medium in the opening to form a shallow trench isolation structure;
sequentially depositing a first insulating layer, a first conductive layer and a second photoresist layer;
masking, exposing and etching to form a grid electrode of the MOS device;
stripping the second photoresist layer;
depositing a third layer of photoresist;
exposing and photoetching a mask to form regions of the source electrode and the drain electrode of the MOS device to be doped;
performing ion implantation to form a source electrode and a drain electrode of the MOS device;
stripping the third layer of photoresist;
depositing a fourth layer of photoresist;
mask exposure, lithography exposes the source or drain of the MOS device (without nanowire array locations);
depositing a second conductive layer and etching the second conductive layer to form metal contact;
removing the fourth photoresist layer;
depositing a fifth layer of photoresist
Mask exposure, lithography exposes the source or drain of the MOS device (the location of the nanowire array);
depositing a third conductive layer and etching the third conductive layer to form metal contact;
and removing the fifth layer of photoresist.
In some embodiments of the application, the CMOS device surface is comprised of the cut-out face formed after the (111) crystal face is cut out. The surface of the CMOS device is formed by the cut-out surface formed by cutting out the (111) crystal face by means of cutting out or filling and the like, which is favorable for the placement of a subsequent growth chamber of the nanowire and the use of subsequent integral display application, and reduces the inclination angle of the integral epitaxial wafer of the array after manually calibrating the optimal array light-emitting direction.
In the present application, the nanowires may be vertically grown on the (111) crystal plane cut out from the Si (100) substrate, including but not limited to, the following ways:
depositing a first photoresist;
masking, exposing and etching to form an opening structure;
depositing a mask material;
stripping the first photoresist, wherein the mask material only exists at the original opening structure position;
the nanowire is grown in the areas without masking material (the areas without masking material correspond to the source or drain of the MOS device);
the masking material is stripped.
Or, the nanowires are grown obliquely on the Si (100) crystal plane, including but not limited to forming a confinement channel on the Si (100) crystal plane, and then the [100] nanowires are grown directionally, specifically as follows:
depositing a first layer of photoresist;
masking, exposing and etching to form an opening structure;
depositing a mask material;
depositing a second layer of photoresist;
masking, exposing and etching the mask material area to form at least one constraint channel;
the second layer of photoresist is stripped.
The first insulating medium and the mask material are SiO 2 、SiO X 、Si 3 N 4 、SiN x 。
The first insulating layer is silicon dioxide, a material with high dielectric constant, a two-dimensional material or a mixed layer between the two materials. The first conductive layer is made of metal gate materials such as TiN and TaN or doped polysilicon.
The second and third conductive layers are made of Cu, al, ti, au metal conductive materials. The nanowire growth method comprises etching, hydrothermal self-assembly, epitaxial growth including MOCVD, LPCVD, MBE and the like.
The nanowire material of the present application is Si, gaAs, inAs, gaN, inGaN or other semiconductor of III-V, oxide material.
The application has the beneficial effects that: the nanowire light-emitting array integrated on the Si (100) substrate overcomes the technical prejudice that heterogeneous [100] nanowires cannot be formed by self-assembly, and provides the technical structure and the preparation technology for realizing the nanowire light-emitting array independently controlled on the Si (100) substrate, so that the technical bottleneck of the silicon-based integrated nanowire light-emitting array is solved, and the image display can be realized by a single chip. Therefore, the display device manufactured by the semiconductor adopting the technology has the advantages of ultrahigh pixel density, small volume, light weight, low power consumption, high luminous brightness, large portability, stable color temperature, long service life, realization of full color/single color and the like. Moreover, the high integration of the CMOS integrated circuit and the light emitting array greatly simplifies the system of the nanowire display device, reduces the production cost and has commercial prospect.
Drawings
FIG. 1 is a schematic diagram of the active area and overall metal electrode connection of various nanowire integrated growth CMOS devices; wherein (a) in fig. 1 is a side view and (b) in fig. 1 is a top view;
FIG. 2 is a schematic diagram of a single nanowire array integrated growth CMOS device source region;
FIG. 3 is a schematic diagram of a plurality of independently selectable nanowire arrays simultaneously integrated grown CMOS device source regions;
FIG. 4 is a schematic view of a nanowire radial structure; wherein (a) in fig. 4 is a side view and (b) in fig. 4 is a top view;
FIG. 5 is a schematic axial structure of a nanowire;
FIG. 6a is a schematic view of the substrate processing after the Si (100) substrate is cut out of the (111) plane;
FIG. 6b is a schematic diagram of the preparation of a pattern to be doped in the source and drain regions of a MOS transistor;
FIG. 6c is a schematic diagram of a MOS transistor fabrication;
FIG. 6d is a schematic diagram of growing nanowires and filling a protective layer on the MOS;
fig. 6e is a schematic diagram of nanowire array electrode fabrication.
The light-emitting diode comprises a Si substrate 1, a doped region 2, a source region 3, a drain region 4, a gate dielectric layer 5, a shallow trench isolation structure 6, a nanowire 7, a filling material 8, a gate electrode 9, an electrode 10, an n-type region 11, a light-emitting layer 12 and a p-type region 13.
Detailed Description
The application will be further described with reference to the drawings and the specific examples.
The drawings are for illustrative purposes only and are not to be construed as limiting the present patent; for the purpose of better illustrating the embodiments, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the actual product dimensions; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationship depicted in the drawings is for illustrative purposes only and is not to be construed as limiting the present patent.
As shown in fig. 1-2, a CMOS integrated, ac driven active addressing NLED micro-display device includes a light emitting component and a CMOS device, wherein the CMOS device includes four types of MOS cells ABCD, and the MOS device includes a source region 3, a drain region 4, and a gate region composed of a gate dielectric layer 5 and a gate electrode 9 as is known in the art. The source region 3 and the drain region 4 are both active regions according to the application; the Nano LED nanowire/Nano LED luminous array grows in the source region 3 or the drain region 4. The shallow trench isolation structure 6 serves as an isolation layer for each MOS group in the MOS circuit.
The size of each MOS can be regulated and controlled according to the existing integration process, each MOS can be independently controlled through a grid electrode of each MOS, so that the MOS and the integrated growth nanowire become an independent pixel point, and each pixel can be LEDs with different colors and has the functions of independently driving and emitting light beams by alternating voltage. Taking a nanowire with a single diameter of 800 nanometers as an example, the density of the nanowire can reach at least 1 ten thousand in the chip size with the width of one inch, the weight of the chip is only a few grams, the threshold voltage is about 5V, the light-emitting brightness of the array can reach 2 vannits per pixel, the power consumption is only one fifth of an LCD or one fourth of an OLED, and the resolution can reach more than 8K. Therefore, by designing the distance between the nanowires and the array density of the MOS devices, the advantages of ultrahigh pixel density, small volume, light weight, low power consumption, high luminous brightness, large portability, stable color temperature, long service life, full color/single color and the like can be realized.
In the figure, class A, class C and class D MOS are NMOS, and have N channels; the class B MOS is PMOS with a P channel. The N-type substrate is a Si (100) substrate doped with pentavalent elements such as arsenic, phosphorus, antimony and the like, and the P-type substrate can be a Si (100) substrate doped with trivalent elements such as boron and the like.
Fig. 2 is a MOS light emitting cell, which may be a class a/C MOS device and an array of nanowires 7 self-assembled to grow in the active region of the MOS device. The MOS device adopts the Si substrate 1 as a (100) crystal face. The nanowire light-emitting array can be composed of AlGaAs, inGaAsP, gaP, gaAsP, alGaInP, inGaN, gaN, siC and other materials and contains single or multiple quantum wells, quantum dots or pure single material structures. The nanowire surface is coated with passivation layers that separate the nanowire and nanowire from other materials and protect the device from the external environment. In fig. 2, the filling material 8 may encapsulate and protect the device. The electrode 10 is a metal material, which serves as the metal electrode of the device.
FIG. 3 is a MOS light emitting cell, which may be a D-type MOS device and self-assembled nanowire 7 array grown in the active region; it should be noted that the unit has two independent nanowire arrays, each using the electrode 10Is connected with a power supply. By controlling the voltage of the nanowire top electrode, the V of the two arrays is enabled DS1 And V DS2 By V, differently G And V DS Independent control of the two nanowire arrays is achieved, and a secondary control effect can be achieved.
For the above nanowire 7, the following five cases are possible:
the contact interface between the source electrode or the drain electrode of the surface of the CMOS device and the nanowire(s) in the area is p-type material which is of a first type;
the contact interface between the source electrode or the drain electrode on the surface of the CMOS device and the nanowire(s) in the area is of a second type, wherein the n-type material is the same;
the contact interface between the source electrode or the drain electrode on the surface of the CMOS device and the nanowire(s) in the area is p-n type material which is of a third type;
the contact interface between the source electrode or the drain electrode on the surface of the CMOS device and the nanowire(s) in the area is n-p type material which is of a fourth type;
the single contact interface of the source electrode or the drain electrode of the surface of the CMOS device and the plurality of nanowires of the region is of the fifth type with p, n, p-n and n-p type materials.
The whole nanowire light-emitting array can be arranged and combined by the five types or the derivative types of the five types.
The nanowires comprise at least one light emitting region, and in certain preferred embodiments more than two light emitting regions. The light-emitting region refers to a light-emitting region of the nanowire, and can emit light for the whole nanowire or emit light for the nanowire locally. Either wholly or partially illuminated, may be comprised of one or more illuminated regions. Each light emitting region is typically carrier radiation recombination light emission (light emission is achieved based on electron and hole recombination); the carrier radiation composite luminescence can be realized based on the intrinsic luminescence of the nanowire material or the PN junction luminescence of the nanowire, so the application is called an intrinsic luminescence region of the nanowire or a PN junction region of the nanowire.
The intrinsic luminescence refers to intrinsic electroluminescence (electroluminescence, EL), which is a phenomenon that a substance emits light when a current passes through the substance or when the substance is under a strong electric field, and is generally considered to be that the energy of electrons is increased by the action of the strong electric field until the energy of electrons in a thermal equilibrium state is far exceeded to become overheated electrons, and the overheated electrons can ionize crystal lattices by collision during movement to form electron and hole pairs, and when the ionized electrons and hole pairs recombine or the excited luminescence center returns to a ground state, light is emitted. The material for realizing the intrinsic luminescence of the application comprises an inorganic electroluminescent material and an organic electroluminescent material. The inorganic electroluminescent material is typically a semiconductor material. The organic electroluminescent materials can be divided into two major classes of small molecules and high molecules according to the difference of molecular weights of the organic luminescent materials. The small molecular OLED material takes organic dye or pigment as a luminescent material, and the high molecular OLED material takes conjugated or non-conjugated high polymer (polymer) as a luminescent material, and the typical high molecular luminescent material is PPV and derivatives thereof.
The PN junction luminescent nanowire PN junction region can be composed of a single quantum well or a plurality of quantum well or quantum dot structures.
In the embodiment of the present application, the manufacturing process of the semiconductor device shown in fig. 3 and 4 will be described by taking InGaN/GaN material as an example.
The radial PN light-emitting structure of FIG. 4 is composed of n-type GaN (n-type region 11), inGaN/GaN quantum well (light-emitting layer 12) and p-type GaN (p-type region 13) grown from inside to outside, wherein the growth mode is that n-type GaN nuclear nanowire is grown in holes formed by source region patterning, and then quantum well and p-type GaN are sequentially grown on the surface of the nuclear nanowire, so that the radial PN structure is formed.
The axial pn structure of fig. 5 is composed of n-type GaN (n-type region 11), inGaN/GaN quantum dots (light emitting layer 12) and p-type GaN (p-type region 13) grown from bottom to top in such a way that n-type GaN core nanowires are grown in holes formed by patterning of the source region, and then quantum dots and n-type GaN are grown above the nanowires in sequence, so as to form the axial pn structure.
The nanowire light emitting arrays integrated into Si (100) substrates disclosed herein can be fabricated by a number of methods. Described below is an example of a method of manufacturing a nanowire light emitting array of a Si (100) substrate as shown in fig. 1, which is disclosed in the present application. Fig. 6a to 6e illustrate a fabrication process for fabricating a nanowire light emitting array as shown in fig. 1.
(1) And cutting out a (111) crystal face on the provided Si (100) substrate, and enabling the substrate of the CMOS device to be horizontally placed and exposing the 111 crystal face which is beneficial to the growth of the nanowire by adopting methods such as cutting out, filling and the like.
(2) Then a layer of photoresist is deposited, then an opening structure is formed by masking, exposing and etching, then an insulating medium is filled in the formed opening to form a shallow trench isolation structure 6, and the structure after the rest of photoresist is stripped is shown in fig. 6 b. The insulating medium is preferably SiO 2 。
(3) Then, a layer of photoresist is deposited, then a pattern to be doped in a source region and a drain region of the MOS transistor is formed by masking, exposing and photoetching, then ion implantation is carried out to form a source region 3 and a drain region 4 of the MOS circuit, an insulating dielectric layer is deposited, and the photoresist is stripped. Next, a layer of photoresist is deposited again, then the gate electrode 9 of the MOS circuit is formed by masking, exposing, etching, and then the remaining photoresist is stripped, as shown in fig. 6 c. The insulating medium layer is made of SiO 2 And one or two layers of structures formed of high-k materials. The gate electrode 9 is a metal such as Ti/Au.
(4) A layer of photoresist is deposited, then an array of holes is formed in the source region 3 by masking, exposing, etching, and the n-type region 11, the light emitting layer 12, and the p-type region 13 of the nanowire light emitting array are grown sequentially by an epitaxial process (preferably MBE). After growing the nanowire array, the transparent organic is filled, and the resulting structure is shown in fig. 6 d.
(5) A layer of photoresist is deposited and then the source and drain top regions are exposed by masking, exposing, etching, depositing a layer of metal and etching the metal to form the electrode 10 as shown in fig. 6 e.
Claims (7)
1. The preparation method of the nanowire luminescent device is characterized in that the nanowire integrally grows on an active area of the CMOS device, and an electrode is arranged at the top end of the nanowire; the CMOS device substrate is a Si (100) substrate; the nanowire comprises at least one light emitting region; the preparation method at least comprises the following steps: preparation of nanowires on a Si (100) substrate and construction of CMOS circuits; wherein, the preparation of the nanowire on the Si (100) substrate comprises the following steps:
forming a CMOS circuit on a Si (100) substrate, and then cutting out a (111) crystal face for nanowire growth; or cutting out a (111) crystal face on the Si (100) substrate, forming a CMOS circuit on the Si (111) crystal face, and then preparing a nanowire;
the surface of the CMOS device is composed of the cut-out surface formed after the (111) crystal surface is cut out.
2. The method of claim 1, wherein the nanowires are grown vertically on a (111) crystal plane cut out of the Si (100) substrate.
3. The method of claim 1, wherein the CMOS device comprises two or more Si (100) MOS devices, at least one MOS being an independent control unit.
4. The method of claim 1, wherein the CMOS device comprises two or more Si (100) MOS devices and the active region of the MOS is grown with a single or multiple nanowires.
5. The method of claim 1, wherein the nanowires are heterogeneous with a Si (100) substrate.
6. The method of claim 1, wherein the nanowire comprises at least two carrier-emitting composite light emitting regions, the light emitting regions being arranged radially or axially along the nanowire.
7. The method of claim 6, wherein the carrier-irradiated composite light-emitting region is an intrinsic light-emitting region of a nanowire or is a nanowire PN junction region; the nanowire PN junction region is formed by quantum wells, quantum dots or combination of the quantum wells and the quantum dots.
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| US8653599B1 (en) * | 2012-11-16 | 2014-02-18 | International Business Machines Corporation | Strained SiGe nanowire having (111)-oriented sidewalls |
| CN107204311A (en) * | 2016-03-16 | 2017-09-26 | 上海新昇半导体科技有限公司 | Nanowire semiconductor device and its manufacture method |
| KR20180074014A (en) * | 2016-12-23 | 2018-07-03 | 포항공과대학교 산학협력단 | Vertical nanowire tunneling field-effect transistor and method for fabricating the same |
| CN113646894A (en) * | 2018-08-24 | 2021-11-12 | 马修·哈滕斯维尔德 | Nanowire light emitting switch device and method thereof |
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| US8937297B2 (en) * | 2011-12-02 | 2015-01-20 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Optoelectronic device including nanowires with a core/shell structure |
| US20170133431A1 (en) * | 2015-11-11 | 2017-05-11 | The Regents Of The University Of Michigan | Direct Growth Of Optoelectronic Devices On CMOS Technology |
| CN109795982A (en) * | 2018-12-30 | 2019-05-24 | 华南师范大学 | A kind of nano-wire array, opto-electronic device and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8653599B1 (en) * | 2012-11-16 | 2014-02-18 | International Business Machines Corporation | Strained SiGe nanowire having (111)-oriented sidewalls |
| CN107204311A (en) * | 2016-03-16 | 2017-09-26 | 上海新昇半导体科技有限公司 | Nanowire semiconductor device and its manufacture method |
| KR20180074014A (en) * | 2016-12-23 | 2018-07-03 | 포항공과대학교 산학협력단 | Vertical nanowire tunneling field-effect transistor and method for fabricating the same |
| CN113646894A (en) * | 2018-08-24 | 2021-11-12 | 马修·哈滕斯维尔德 | Nanowire light emitting switch device and method thereof |
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