CN114420720B - MicroLED display panel manufacturing method and display panel - Google Patents
MicroLED display panel manufacturing method and display panel Download PDFInfo
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- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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Abstract
The invention discloses a manufacturing method of a micro LED display panel and the display panel, belonging to the field of micro LEDs, and the method comprises the steps of arranging a first barrier layer to divide a first multi-quantum well layer into a plurality of first multi-quantum wells; arranging an anode in the first barrier layer, wherein the anode comprises a first anode in contact with the first P layer and a second anode in contact with the N layer; bonding and removing the first substrate until the N layer is exposed; a plurality of second multiple quantum wells with second P layers on the top surfaces are arranged on the N layers, and the second multiple quantum wells are positioned on the periphery of the second anode; and an extension electrode which is in contact with the second P layer and the second anode and is isolated from the second multiple quantum well is arranged, the first multiple quantum well and the second multiple quantum well share a cathode, the required temperature during secondary epitaxy is low, the first multiple quantum well and the metal lead wire can be protected, and the first multiple quantum well and the second multiple quantum well can be actively driven to realize color display.
Description
Technical Field
The invention relates to a manufacturing method of a micro LED display panel and the display panel, and belongs to the field of micro rolled.
Background
The micro LED display technology is a display technology in which a self-luminous micron-sized LED is used as a light-emitting pixel unit, and an LED chip is assembled on a driving panel to form a high-density LED array. Due to the characteristics of small size, high integration level, self-luminescence and the like of the micro LED chip, compared with an LCD (liquid crystal display) and an OLED (organic light emitting semiconductor), the micro LED chip has the advantages of brightness, resolution, contrast, energy consumption, service life, response speed, thermal stability and the like in the aspect of display. The size of the used LED chip is in the micron level, which makes it difficult to assemble the LED chip to the driving panel, and the methods in the prior art include film transfer, laser transfer, electrostatic transfer, electromagnetic transfer, fluid self-assembly, etc., which are microscopically to assemble the LED chip with the driving panel one by one or in batches, and the method is long in use and high in reject ratio. The Hybrid bonding (Hybrid bonding) technology can bond the electrodes of two wafers together at one time, contact electrodes on the two wafers can be strictly aligned through graphical etching, the Hybrid bonding technology is applied to a micro LED in the prior art, the whole LED chip is synchronously assembled on a driving panel, the assembly efficiency of the micro LED panel is greatly improved, but no colorful LED epitaxial wafer exists in the prior art, only an LED epitaxial wafer with a multi-quantum well exists on the market, and after Hybrid bonding, the bonding surface (namely the LED chip and the driving electrode) cannot be processed; if N-type gallium nitride, a second multi-quantum well and P-type gallium nitride are generated on an LED epitaxial wafer with a multi-quantum well in a secondary epitaxial mode, the original multi-quantum well is hidden in the middle of the epitaxial wafer deeply, a large processing depth is needed during processing, and etching difficulty is high, so that the micro LED panel obtained by hybrid bonding in the prior art can only emit light of one color.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a manufacturing method of a micro LED display panel and the display panel manufactured by the method, which can emit light in color.
In a first aspect, the application provides a method for manufacturing a micro led display panel, in which an epitaxial wafer and a driving panel are used as raw materials, the epitaxial wafer sequentially includes a first substrate, an N layer, a first multi-quantum well layer and a first P layer from bottom to top, the driving panel includes a second substrate and a driving electrode embedded in the second substrate, and the method includes the following steps:
providing a first barrier layer to separate the first multi-quantum well layer into a plurality of first multi-quantum wells;
disposing an anode in the first barrier layer, the anode comprising a first anode in contact with the first P layer, and a second anode in contact with the N layer;
bonding the epitaxial wafer and the driving panel to bond the driving electrode and the anode to form a double-layer wafer;
removing the first substrate until the N layer is exposed;
a plurality of second multiple quantum wells with second P layers on the top surfaces are arranged on the N layers, and the second multiple quantum wells are positioned on the periphery of the second anode;
an extension electrode is disposed in contact with the second P layer and the second anode and isolated from the second multiple quantum well.
By the method for manufacturing the micro LED display panel, the color display micro LED display panel can be manufactured, and the secondary epitaxial temperature is low.
It should be noted that as will be appreciated by those skilled in the art, wafers (wafers) are sheet-like in shape, with only one side of the substrate being available for mounting and only the other side being available for processing relative to the substrate. For example, the wafer is inverted once after the first substrate is removed until the N layer is exposed. In the present application, unless otherwise specified, the orientation descriptions such as "upper" and "lower" are both in the wafer level and the substrate down as a frame of reference, and "surface" and "top surface" refer to the surface on the other side with respect to the substrate.
Further, the step of providing a first barrier layer to separate the first multiple quantum well layer into a plurality of first multiple quantum wells includes:
the first multi-quantum well layer is etched in a graphical mode, so that the first multi-quantum well layer is separated into a plurality of first multi-quantum wells;
and generating a first barrier layer covering the epitaxial wafer on the epitaxial wafer.
Further, the step of disposing an anode in the first barrier layer includes:
the first barrier layer is etched in a patterned mode to form an anode groove, and the anode groove comprises a first anode groove etched to the first P layer and a second anode groove etched to the N layer;
generating anode metal covering the epitaxial wafer on the epitaxial wafer;
and grinding the anode metal until the first barrier layer is exposed so as to reserve the first anode in the first anode groove and reserve the second anode in the second anode groove.
Further, the step of disposing a plurality of second multiple quantum wells having a second P layer on top of the N layer includes:
generating a second multi-quantum well layer on the N layer;
generating a second P layer on the second multi-quantum well layer;
and the double-layer wafer is etched in a patterned mode, the top of the second anode is exposed, and the N layer is exposed above the first multi-quantum well, so that the second multi-quantum well layer is separated into a plurality of second multi-quantum wells.
Etching the upper part of the first anode until the N layer is exposed, and avoiding the N layer from being separated, so that the first multiple quantum well and the second multiple quantum well can share the cathode; etching the second anode until the first barrier layer is exposed, namely the second anode is exposed, and the re-deposited metal can be contacted with the second anode.
Further, the step of performing the patterned etching on the bilayer wafer to expose the top of the second anode and expose the N layer above the first multiple quantum well to partition the second multiple quantum well layer into a plurality of second multiple quantum wells includes:
arranging a third photoresist and a fourth photoresist thicker than the third photoresist on the second P layer, wherein the third photoresist is positioned above the first anode, and the fourth photoresist is positioned at the periphery of the second anode;
etching the double-layer wafer to bomb the third photoresist and etch the first anode to expose the N layer, and etching the second anode to expose the top of the second anode;
and removing the residual fourth photoresist.
Further, one of the second multiple quantum wells is disposed beside each of the first multiple quantum wells, and the step of disposing an extension electrode in contact with the second P layer and the second anode and isolated from the second multiple quantum wells includes:
generating a second barrier layer on the bi-layer wafer;
the second barrier layer is etched in a patterned mode to form an extension electrode groove, the extension electrode groove comprises a main extension groove etched to the second anode and an auxiliary extension groove etched to the second P layer;
generating an extension metal on the double-layer wafer to cover the double-layer wafer;
and patterning and etching the extension metal to form a plurality of extension electrodes which are disconnected with each other, wherein the extension electrodes are in contact with the second P layer in the auxiliary extension groove and in contact with the second anode in the main extension groove.
Further, two or more second multiple quantum wells are provided beside each of the first multiple quantum wells, and the step of providing an extension electrode in contact with the second P layer and the second anode and isolated from the second multiple quantum wells includes:
generating a second barrier film on the double-layer wafer;
the second barrier film is etched in a patterned mode, so that a second barrier portion is reserved on the inclined plane of the second multiple quantum well close to one side of the second anode;
generating an extension metal on the double-layer wafer to cover the double-layer wafer;
the extension metal is patterned to leave an extension electrode on top of the second anode in contact with the second P layer.
Further, the step of providing an extension electrode in contact with the second P layer and the second anode and isolated from the second multiple quantum well further comprises:
generating a third barrier layer on the bi-layer wafer covering the bi-layer wafer;
and arranging an optical filter above the second multiple quantum well on the top surface of the third barrier layer.
The epitaxial wafer with the blue light multiple quantum well is purchased as a raw material, the yellow light multiple quantum well is generated through secondary external time delay, and the yellow light is filtered by the green filter and the red filter, so that full-color display can be realized.
In a second aspect, the present application provides a display panel comprising a driving panel and an LED chip, the driving panel comprising a second substrate and driving electrodes embedded in the second substrate, the LED chip comprises a first multiple quantum well and a second multiple quantum well which share the same N layer and have opposite conduction directions, the driving electrode is connected with a first anode and a second anode, a first barrier layer for separating the first anode, the second anode and the first multiple quantum well is arranged below the N layer, the bottom of the first multiple quantum well is provided with a first P layer which is in contact with the first anode, the top of the second anode is connected with an extension electrode which is isolated from the second multiple quantum well, and a second P layer is arranged at the top of the second multiple quantum well and is connected with the driving electrode through the extension electrode and the second anode in sequence.
The application provides a micro LED display panel sharing negative pole, but the colour shows.
Furthermore, the first multiple quantum well emits blue light when being electrified, the second multiple quantum well emits yellow light when being electrified, a third blocking layer is arranged on the top surface of the LED chip, an optical filter is arranged on the top of the third blocking layer, and the optical filter comprises a red optical filter and a green optical filter which are positioned above the second multiple quantum well.
The invention has the beneficial effects that: the invention flexibly applies the mixed bonding technology, a second anode is preset before bonding, a second multi-quantum well is formed by epitaxy after bonding and removing the first substrate, the first multi-quantum well and the second multi-quantum well share an N layer as a cathode, the temperature required during secondary epitaxy is low, the first multi-quantum well and the metal lead in the LED chip can be protected, and after the second multi-quantum well and the second anode are connected by arranging the extension electrode, the first multi-quantum well and the second multi-quantum well can be actively driven, thereby realizing color display.
Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
Fig. 1 is a flowchart of steps S1 to S2 provided in an embodiment of the present application.
Fig. 2 is a flowchart of steps S3 to S4 provided in the embodiment of the present application.
Fig. 3 is a flowchart of step S5 provided in an embodiment of the present application.
Fig. 4 is a flowchart of step S6 provided in the embodiment of the present application.
Fig. 5 is a flowchart of steps S7 to S8 provided in the embodiment of the present application.
Fig. 6 is a flowchart illustrating a manufacturing process of a full-color micro led display panel according to an embodiment of the present disclosure.
Reference numerals: 11. a first substrate; 12. a second substrate; 13. a buffer layer; 2. n layers; 31. a first multiple quantum well; 311. a first multi-quantum well layer; 32. a second multiple quantum well; 321. a second multiple quantum well layer; 41. a first P layer; 42. a second P layer; 51. a first barrier layer; 52. a second barrier portion; 521. a second barrier film; 53. a third barrier layer; 54. a first anode tank; 55. a second anode tank; 56. a second barrier layer; 561. a main extension groove; 562. a secondary extension groove; 61. a first anode; 62. a second anode; 63. a drive electrode; 64. an extension electrode; 641. extending the metal; 73. a third photoresist; 74. a fourth photoresist; 75. a fifth photoresist; 76. a sixth photoresist; 81. a red filter; 82. a green filter.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
The mixed bonding technology is expected to solve the problem that the huge transfer difficulty of the MicroLED is high, but the scheme in the prior art can only be used for manufacturing a MicroLED display panel with monochrome display.
Referring to fig. 1 to 5, in a method for manufacturing a micro led display panel, an epitaxial wafer and a driving panel are used as raw materials, the epitaxial wafer sequentially comprises, from bottom to top, a first substrate 11, an N layer 2, a first mqw layer 311 and a first P layer 41, and the epitaxial wafer with such a structure can be directly purchased from the market. The driving panel includes a second substrate 12 and driving electrodes 63 embedded in the second substrate 12, and is obtained by photo-etching the substrate, depositing metal, and then CMP (chemical mechanical polishing) according to the designed pixel distribution.
The method comprises the following steps:
s1: the first barrier layer 51 is provided to partition the first multi-quantum well layer 311 into a plurality of first multi-quantum wells 31.
S2: an anode is provided in the first barrier layer 51, the anode including a first anode 61 in contact with the first P layer 41, and a second anode 62 in contact with the N layer 2.
S3: the epitaxial wafer and the driving panel are bonded to bond the driving electrode 63 and the anode, thereby forming a double-layered wafer.
S4: the first substrate 11 is removed until the N layer 2 is exposed.
S5: a plurality of second multiple quantum wells 32 having the second P layer 42 on the top surface are provided on the N layer 2, and the second multiple quantum wells 32 are located at the outer periphery of the second anode 62.
S6: an extension electrode 64 is provided in contact with the second P layer 42 and the second anode 62 and isolated from the second multiple quantum well 32.
In the prepared micro LED display panel, the first multiple quantum well 31 and the second multiple quantum well 32 share the same N layer as a cathode, the first multiple quantum well 31 is conducted with a driving electrode 63 through a first P layer 41 and a first anode 61 in sequence, the second multiple quantum well 32 is conducted with the driving electrode 63 through a second P layer 42, an extension electrode 64 and a second anode 62 in sequence, and both the first multiple quantum well 31 and the second multiple quantum well 32 can be actively driven.
The first P layer 41 and the second P layer 42 are made of P-type gallium nitride, the N layer 2 is made of N-type gallium nitride, the first substrate 11 and the second substrate 12 are made of silicon substrates, the bonding capability of silicon and gallium nitride is poor, and the buffer layer 13 is arranged between the silicon and the gallium nitride. When the first multiple quantum well 31 and the second multiple quantum well 32 are electrified, light with different colors is emitted respectively, and the micro LED display panel can display in colors. Those skilled in the art understand that the temperature required to epitaxially grow the N layer is much higher than the temperature required to epitaxially grow the P layer; the currently popular MQW (multiple quantum well) is made of an InGaN/GaN structure (indium gallium nitride/gallium nitride), the forbidden bandwidth is adjusted by changing the content of In (indium), so the temperature required for epitaxially generating N-type gallium nitride is higher than that required for epitaxially generating MQW, after bonding, the first substrate 11 is removed until the N layer 2 is exposed, and the second multiple quantum well 32 and the second P layer 42 are epitaxially generated on the N layer 2 (In the application, "upper" refers to the upper part or the upper surface of some object, and the operation of inverting a wafer exists In the manufacturing step, and the orientation description is based on the figure), so that the N layer does not need to be generated, the energy consumption is reduced, and the damage to the first multiple quantum well 31, the anode and the driving electrode 63 caused by high temperature is avoided.
Referring to fig. 1, in detail, step S1 includes the steps of:
s11: the first mqw layer 311 is patterned to partition the first mqw layer 311 into a plurality of first mqw 31. More specifically, the first photoresist is provided to protect the position where first multiple quantum well 31 is to be formed, the epitaxial wafer is etched to N layer 2, and then the first photoresist is removed. It will be understood by those skilled in the art that patterned etching refers to a series of operations of photo-etching-resist removal to etch trenches or holes in the wafer.
S12: a first barrier layer 51 is grown on the epitaxial wafer covering the epitaxial wafer. The specific operation is to deposit a layer of silicon oxide on the epitaxial wafer using CVD (chemical vapor deposition) techniques or thermal growth techniques.
Referring to fig. 1, in detail, step S2 includes the steps of:
s21: the patterned etching of the first barrier layer 51 forms anode trenches comprising a first anode trench 54 etched to the first P layer 41 and a second anode trench 55 etched to the N layer 2. And setting a second photoresist for protecting the position without generating the anode groove and etching, wherein the position of the anode groove is determined according to the pixel distribution of the designed MicroLED display panel.
S22: and generating anode metal covering the epitaxial wafer on the epitaxial wafer. This step S22 is not shown in fig. 1, and the state after depositing the anode metal can refer to the shape of the extension metal 641 at S63 in fig. 4.
S23: the anodic metal is ground until the first barrier layer 51 is exposed to leave the first anode 61 in the first anode groove 54 and the second anode 62 in the second anode groove 55. The grinding method is CMP, and the first anodes 61 and the second anodes 62 are ground until they are not connected to each other.
Referring to fig. 2, the bonding method may be thermal fusion bonding, such that the first anode 61 is bonded to the driving electrode 63, and the second anode 62 is bonded to the driving electrode 63. The process of removing the first substrate 11 together with the buffer layer 13 may be CMP. Note that the double layer wafer is inverted after the first substrate 11 is removed in the drawings of the specification.
Referring to fig. 3, in particular, step S5 includes the steps of:
s51: the second multiple quantum well layer 321 is generated on the N layer 2. Specifically, the MQW of the InGaN/GaN structure is generated, step S51 is not drawn in fig. 5, and the second P layer 42 can be omitted with reference to S52 in fig. 3.
S52: the second P layer 42 is grown on the second multiple quantum well layer 321.
S53: the bi-layer wafer is patterned to expose the top of the second anode 62 and expose the N layer 2 above the first multi-quantum well 31 to partition the second multi-quantum well layer 321 into a plurality of second multi-quantum wells 32. The gallium nitride on the second anode 62 is completely etched to expose the second anode 62. The second multi-quantum well layer 321 on the first multi-quantum well 31 is isolated to enable the second multi-quantum well layer 321 on two sides of the first multi-quantum well 31 to be separated into two sub-pixels, and light emission of the first multi-quantum well 31 is facilitated; meanwhile, the N layer 2 on the first multiple quantum well 31 is reserved to ensure that the first multiple quantum well 31 and the second multiple quantum well 32 share the cathode, so that etching needs to be performed at different depths, which is achieved in the following four ways.
First, the N layer 2 is first photo-etched over the first anode 61, and then the second anode 62 is photo-etched over the second anode 62 until the top of the second anode 62 is exposed.
Second, the second anode 62 is etched by photolithography until the top of the second anode 62 is exposed, and then the N layer 2 is etched by photolithography and etching until the first anode 61 is exposed.
Referring to fig. 4, the method includes the following steps:
s531: a third photoresist 73 and a fourth photoresist 74 thicker than the third photoresist 73 are disposed on the second P layer 42, the third photoresist 73 is positioned above the first anode 61, and the fourth photoresist 74 is positioned at the outer periphery of the second anode 62. The third photoresist 73 and the fourth photoresist 74 have different thicknesses and can be realized by adjusting the power of the ultraviolet lamp at different positions during curing; the photomask may be made transparent at a position corresponding to the fourth photoresist 74 and semi-transparent at a position corresponding to the third photoresist 73.
S532: etching the bilayer wafer to flash the third photoresist 73 and etch over the first anode 61 to expose the N layer 2 and over the second anode 62 to expose the top of the second anode 62;
s533: the remaining fourth photoresist 74 is removed.
Fourthly, the method comprises the following steps:
s531': the double-layer wafer is etched in a patterning mode until the N layer 2 is exposed, so that the second multi-quantum well layer 321 is isolated to form a plurality of second multi-quantum wells 32;
s532': the N layer 2 is further patterned over the second anode 62 until the first barrier layer 51 is exposed (i.e., the second anode 62 is exposed).
The third mode is preferably selected, so that one-time etching can be reduced, the process is simpler, the phenomenon that the surface appearance of the wafer is changed greatly due to too many times of etching is avoided, and one photomask is used less.
Referring to fig. 4, each first multiple quantum well 31 is provided with two or more second multiple quantum wells 32 on the outer periphery thereof, and specifically, step S6 includes the steps of:
s61: a second barrier film 521 is produced on the bilayer wafer. When the film is formed to be thin (5 to 10 angstroms), the shape of the second barrier film 521 is the same as or very similar to the shape of the upper surface of the double-layer wafer.
S62: the second barrier film 521 is pattern-etched to leave the second barrier 52 on the slope of the second multiple quantum well 32 on the side close to the second anode 62. A fifth photoresist 75 is first provided on the MESA slope, the fifth photoresist 75 is located around the second anode 62, as shown in the step between S61 and S62 in fig. 4, and then the shape of the etched second barrier 52 is shown as S62 in fig. 4.
S63: an extension metal 641 is grown on the bi-layer wafer covering the bi-layer wafer. Specific means may be PVD (physical vapor deposition), CVD, electroplating, or the like.
S64: the extension metal 641 is patterned to leave an extension electrode 64 on top of the second anode 62 in contact with the second P layer 42. That is, the sixth photoresist 76 is first provided at a position where the extension electrode 64 needs to be left, as shown in the step between S63 and S64 in fig. 4, and then etched.
The above process produces a micro led display panel having only two MQWs and thus not full color, and further, referring to fig. 5, the step of providing the extension electrode 64 in contact with the second P layer 42 and the second anode 62 and isolated from the second multiple quantum well 32 further comprises:
s7: a third barrier layer 53 is grown on the bi-layer wafer covering the bi-layer wafer.
S8: an optical filter located above the second multiple quantum well 32 is disposed on the top surface of the third barrier layer 53.
The epitaxial wafer with the blue light multiple quantum well is used as a raw material, the multiple quantum well capable of emitting yellow light is generated by secondary external time delay and used as a second multiple quantum well 32, the green filter 82 and the red filter 81 are coated to filter the yellow light, green light and red light can be respectively transmitted, and full-color display can be achieved.
In the example shown in fig. 5, two or more second multiple quantum wells 32 are provided on the outer periphery of each first multiple quantum well 31, and if the arrangement is to be standardized (the ratio of red, blue, and green sub-pixels is 1: 1: 1), the manufacturing method is as shown in fig. 6, the flow before step S52 is the same as that described above, and the following steps are:
s53: the bi-layer wafer is patterned to expose the top of the second anode 62 and the N layer 2 above the first multiple quantum well 31 to partition the second multiple quantum well layer 321 into multiple second multiple quantum wells 32. Only one second multiple quantum well 32 remains at the periphery of each first multiple quantum well 31.
S61': a second barrier layer 56 is created on the bi-layer wafer. In FIG. 6, the second barrier layer 56 is not shown before being etched, and the morphology of the second barrier layer 56 before being etched can be referred to the first barrier layer 51 of S12 in FIG. 1.
S62': the second barrier layer 56 is patterned to form an extension electrode trench, which includes a main extension trench 561 etched to the second anode and a sub-extension trench 562 etched to the second P layer.
S63': an extension metal is generated on the bi-layer wafer covering the bi-layer wafer.
S64': the extension metal is patterned to form a plurality of extension electrodes 64 disconnected from each other, and the extension electrodes 64 are in contact with the second P layer 42 in the sub extension grooves and in contact with the second anode 62 in the main extension grooves.
S7: a third barrier layer 53 is grown on the bi-layer wafer covering the bi-layer wafer.
S8: an optical filter is disposed on the top surface of third barrier layer 53 above second multiple quantum well 32.
The total area of second multiple quantum well 32 should be twice the total area of first multiple quantum well 31; in each pixel, the area ratio of the second multiple quantum well 32 filtered to green light, the second multiple quantum well 32 filtered to red light, and the first multiple quantum well 31 is 1: 1: 1, thus, a micro LED display panel with a standard array can be manufactured.
The first anode 61, the second anode 62, the driving electrode 63, the extension electrode 64 and other metal leads may be deposited by copper, tungsten or aluminum, and when the metal is etched in step S64, if the extension electrode 64 is copper, wet etching is used, and dry etching is used for etching other metals, silicon oxide and gallium nitride.
The method for manufacturing the MicroLED display panel only needs to etch for 5 times at least, in the photoetching-etching step S21, the conditions of different etching depths are involved, silicon oxide used as a barrier layer and gallium nitride materials forming a PN junction are different, gas used in etching different materials is different from etching parameters set, the etching rate of different materials is different by using the same gas under the same etching parameter, and if the depth difference between a first anode groove and a second anode groove is not large (the depth of the second anode groove is less than twice of the depth of the first anode groove), photoresist can not be set on the first anode groove. If the photoresist is provided, the photoresist with different thickness is provided similarly to steps S531 to S533.
The application also provides a micro LED display panel, which is manufactured by any one of the above manufacturing methods, and referring to S64 in fig. 4 or S64' in fig. 6, the structure of the micro LED display panel includes a driving panel and an LED chip, the driving panel includes a second substrate 12 and a driving electrode 63 embedded in the second substrate 12, the LED chip includes a first multiple quantum well 31 and a second multiple quantum well 32 sharing the same N layer 2 and having opposite conduction directions, the driving electrode 63 is connected with a first anode 61 and a second anode 62, a first barrier layer 51 separating the first anode 61, the second anode 62 and the first multiple quantum well 31 is arranged under the N layer 2, a first P layer 41 contacting the first anode 61 is arranged at the bottom of the first multiple quantum well 31, an extension electrode 64 isolated from the second multiple quantum well 32 is connected at the top of the second anode 62, a second P layer 42 is arranged at the top of the second multiple quantum well 32, the second P layer 42, the extension electrode 64, The second anode 62 is connected to the driving electrode 63.
The micro led display panel uses the N layer 2 as a cathode shared by the first multiple quantum well 31 and the second multiple quantum well 32, the first P layer 41 of the first multiple quantum well 31 is electrically connected to the driving electrode 63 through the first anode 61, and the second P layer 42 of the second multiple quantum well 32 is electrically connected to the driving electrode 63 through the extension electrode 64 and the second anode 62. All MQWs can be driven actively, and the two MQWs emit light with different colors to enable the MicroLED display panel to display in color. The LED chip of the MicroLED display panel has lower secondary external delay processing temperature, and is beneficial to ensuring good structure of MQW and metal leads in the MicroLED display panel.
Preferably, referring to S8 in fig. 5 or S8 in fig. 6, when the first multiple quantum well 31 is energized, blue light is emitted, and when the second multiple quantum well 32 is energized, yellow light is emitted, the top surface of the LED chip is provided with a third barrier layer 53, and the top of the third barrier layer 53 is provided with an optical filter including a red filter 81 and a green filter 82 above the second multiple quantum well 32. Yellow light is filtered into green light and red light, and the two MQWs display three colors and can be actively driven to realize full-color display.
In the description of the present specification, reference to the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A manufacturing method of a MicroLED display panel takes an epitaxial wafer and a driving panel as raw materials, the epitaxial wafer sequentially comprises a first substrate, an N layer, a first multi-quantum well layer and a first P layer from bottom to surface, the driving panel comprises a second substrate and a driving electrode embedded in the second substrate, and the manufacturing method is characterized by comprising the following steps of:
providing a first barrier layer to separate the first multi-quantum well layer into a plurality of first multi-quantum wells;
disposing an anode in the first barrier layer, the anode comprising a first anode in contact with the first P layer, and a second anode in contact with the N layer;
bonding the epitaxial wafer and the driving panel to bond the driving electrode and the anode to form a double-layer wafer;
removing the first substrate until the N layer is exposed;
arranging a plurality of second multiple quantum wells with second P layers on the top surfaces on the N layers, so that the first multiple quantum wells and the second multiple quantum wells share the same N layer as a cathode, and the second multiple quantum wells are positioned on the periphery of the second anode;
an extension electrode is disposed in contact with the second P layer and the second anode and isolated from the second multiple quantum well.
2. A method of fabricating a micro led display panel according to claim 1, wherein the step of providing a first barrier layer to separate the first multiple quantum well layer into a plurality of first multiple quantum wells comprises:
the first multi-quantum well layer is etched in a patterning mode, so that the first multi-quantum well layer is separated into a plurality of first multi-quantum wells;
and generating a first barrier layer covering the epitaxial wafer on the epitaxial wafer.
3. A method of fabricating a micro led display panel according to claim 1, wherein the step of providing an anode in the first barrier layer includes:
the first barrier layer is etched in a patterned mode to form an anode groove, and the anode groove comprises a first anode groove etched to the first P layer and a second anode groove etched to the N layer;
generating anode metal covering the epitaxial wafer on the epitaxial wafer;
and grinding the anode metal until the first barrier layer is exposed so as to reserve the first anode in the first anode groove and reserve the second anode in the second anode groove.
4. A method of fabricating a micro led display panel according to claim 1, wherein the step of providing a plurality of second multiple quantum wells having a second P layer on top of the N layer comprises:
generating a second multi-quantum well layer on the N layer;
generating a second P layer on the second multi-quantum well layer;
and the double-layer wafer is etched in a patterned mode, the top of the second anode is exposed, and the N layer is exposed above the first multi-quantum well, so that the second multi-quantum well layer is separated into a plurality of second multi-quantum wells.
5. A method according to claim 4, wherein the step of patternwise etching the bi-layer wafer to expose the top of the second anode and the N layer above the first multiple quantum well to isolate the second multiple quantum well layer into a plurality of second multiple quantum wells comprises:
arranging a third photoresist and a fourth photoresist thicker than the third photoresist on the second P layer, wherein the third photoresist is positioned above the first anode, and the fourth photoresist is positioned at the periphery of the second anode;
etching the double-layer wafer to bomb the third photoresist and etch the first anode to expose the N layer, and etching the second anode to expose the top of the second anode;
and removing the residual fourth photoresist.
6. A method of fabricating a micro led display panel according to claim 1, wherein one of said second multiple quantum wells is disposed adjacent to each of said first multiple quantum wells, said step of disposing an extension electrode in contact with said second P layer and said second anode and isolated from said second multiple quantum wells comprising:
generating a second barrier layer on the bi-layer wafer;
the second barrier layer is etched in a patterned mode to form an extension electrode groove, the extension electrode groove comprises a main extension groove etched to the second anode and an auxiliary extension groove etched to the second P layer;
generating an extension metal on the double-layer wafer to cover the double-layer wafer;
and patterning and etching the extension metal to form a plurality of extension electrodes which are disconnected with each other, wherein the extension electrodes are in contact with the second P layer in the auxiliary extension grooves and in contact with the second anode in the main extension grooves.
7. A method of fabricating a micro led display panel according to claim 1, wherein two or more second multiple quantum wells are disposed adjacent to each of the first multiple quantum wells, and the step of disposing an extension electrode in contact with the second P layer and the second anode and isolated from the second multiple quantum wells comprises:
generating a second barrier film on the double-layer wafer;
the second barrier film is etched in a patterned mode, so that a second barrier portion is reserved on the inclined plane of the second multiple quantum well close to one side of the second anode;
generating an extension metal on the double-layer wafer to cover the double-layer wafer;
the extension metal is patterned to leave an extension electrode on top of the second anode in contact with the second P layer.
8. A method of fabricating a micro led display panel according to claim 1, wherein said providing an extended electrode in contact with said second P layer and said second anode and isolated from said second multiple quantum well further comprises the steps of:
generating a third barrier layer on the bi-layer wafer covering the bi-layer wafer;
and arranging an optical filter above the second multiple quantum well on the top surface of the third barrier layer.
9. The utility model provides a display panel, includes drive panel and LED chip, the drive panel include the second substrate and inlay drive electrode in the second substrate, its characterized in that, the LED chip is including sharing same N layer and switching on opposite direction's first multiple quantum well and second multiple quantum well, drive electrode is connected with first positive pole and second positive pole, be provided with the separation under the N layer first positive pole the second positive pole with the first barrier layer of first multiple quantum well, the bottom of first multiple quantum well be provided with the first P layer of first positive pole contact, the top of second positive pole be connected with the extension electrode that the second multiple quantum well is kept apart, the top of second multiple quantum well is provided with second P layer, the second P layer pass through in proper order extension electrode, second positive pole with drive electrode connects.
10. The display panel according to claim 9, wherein the first multi-quantum well emits blue light when energized, the second multi-quantum well emits yellow light when energized, a third barrier layer is disposed on a top surface of the LED chip, and an optical filter is disposed on a top of the third barrier layer, the optical filter including a red filter and a green filter above the second multi-quantum well.
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