CN113870770B - Drive chip, display panel and display device - Google Patents
Drive chip, display panel and display device Download PDFInfo
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- CN113870770B CN113870770B CN202111129783.XA CN202111129783A CN113870770B CN 113870770 B CN113870770 B CN 113870770B CN 202111129783 A CN202111129783 A CN 202111129783A CN 113870770 B CN113870770 B CN 113870770B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
Abstract
In the driving chip, each group of binding terminals comprises an input terminal and an output terminal, and the input terminal and the output terminal in the same group of binding terminals are used for respectively realizing input and output of the same signal; the input terminals in each group of binding terminals are positioned on the same side of the driving chip; and/or the output terminals in each group of binding terminals are positioned on the same side of the driving chip. The lines among the driving chips can utilize vertical space, the lines can be widened, the resistance is reduced, and the large-size and high-resolution display panel is supported. The connecting wires can not be overlapped and can not pass through the driving chip, and the risk of short circuit of the connecting wires is reduced. And the number of edge winding wires is reduced, and a narrow frame can be realized.
Description
Technical Field
The application relates to the technical field of display, in particular to a drive chip, a display panel and a display device.
Background
With the continuous development of display technology, light Emitting Diode (LED) display technology has become one of the research hotspots as a new type of display technology, wherein, micro Light Emitting diodes (Micro LEDs) and sub-millimeter Light Emitting diodes (Mini LEDs) with smaller sizes have advantages such as High-Dynamic Range image (HDR) due to their small size and thin backlight thickness, and are applied to large-size backlight more and more. The Micro-LED and mini-LED technologies respectively shrink the size of the existing LED to be below 100um and between 100 and 300 um.
In the display panel, the cathode of the Mini/Micro LED needs to be connected with a driving chip, the driving chip and the Mini/Micro LED are arranged in the display area together, the corresponding relation between the driving chip and the Mini/Micro LED is one-to-one or one-to-many, the anode of the Mini/Micro LED supplies constant voltage through an external driving unit, and the light emitting state of the Mini/Micro LED is realized through the driving chip in the display area.
In the prior art, with the improvement of the requirement on resolution, the number of Mini/Micro LEDs is more and more, and the connecting wires of each driving chip, the Mini/Micro LEDs and an external driving unit are easily overlapped to cause the problems of short circuit, crosstalk and the like. In order to avoid this problem, can adopt and set up each connecting wire in different layers, be located and pass through insulating layer isolation between the connecting wire of different layers, but under this kind of scheme, the connecting wire that is located different layers can produce parasitic capacitance at the crossover place, makes display device such as lamp plate the compensation degree of difficulty when debugging increase on the contrary.
Disclosure of Invention
In order to solve the problems, the application provides a driving chip, a display panel and a display device, and solves the technical problem that crosstalk is easy to occur or parasitic capacitance is generated among the driving chip, a Mini/Micro LED and connecting lines of an external driving unit to influence the display effect in the prior art.
In a first aspect, the present application provides a driver chip, including N groups of binding terminals, where N is greater than or equal to 2;
each group of binding terminals comprises an input terminal and an output terminal, and the input terminal and the output terminal in the same group of binding terminals are used for realizing the input and the output of the same signal respectively;
the input terminals in each group of binding terminals are positioned on the same side of the driving chip; and/or the output terminals in each group of binding terminals are positioned on the same side of the driving chip.
In some embodiments, in the driving chip, N is greater than or equal to 3;
the 1 st group of binding terminals in the N groups of binding terminals comprise first input terminals and first output terminals, and are used for respectively realizing input and output of first signals;
the 2 nd group of binding terminals in the N groups of binding terminals comprise a second input terminal and a second output terminal which are used for respectively realizing the input and the output of a second signal;
and the 3 rd group of binding terminals in the N groups of binding terminals comprise a third input terminal and a third output terminal which are used for respectively realizing the input and the output of a third signal.
In some embodiments, in the above driving chip, the driving chip further includes:
a first switch unit having a control terminal connected to the third input terminal and an input terminal connected to the second input terminal and the second output terminal, for outputting the second signal when the third signal is at an active level;
a shift register unit having an input end connected to the third input terminal and an output end connected to the third output terminal, for outputting the third signal;
and the control end of the second switch unit is connected with the output end of the first switch unit, the input end of the second switch unit is connected with the third output terminal, and the output end of the second switch unit is connected with the first input terminal and the first output terminal, so that the third output terminal and the first input terminal are conducted when the output end of the first switch unit is at an active level.
In some embodiments, in the above driving chip, the driving chip further includes: a voltage conversion unit;
the input end of the first switch unit is connected to the second input terminal and the second output terminal through the voltage conversion unit, and the voltage conversion unit is configured to perform voltage conversion on the second signal input by the second input terminal and output the second signal to the input end of the first switch unit.
In some embodiments, in the above driving chip, the first switching unit includes a first switching tube and a first diode;
the control end of the first switch tube is the control end of the first switch unit, the input end of the first switch tube is the input end of the first switch unit, the output end of the first switch tube is the output end of the first switch unit, the first pole of the first diode is connected with the input end of the first switch tube, and the second pole of the first diode is connected with the control end of the first switch tube.
In some embodiments, in the driving chip, the second switching unit includes a second switching tube and a second diode;
the control end of the second switch tube is the control end of the second switch unit, the input end of the second switch tube is the input end of the second switch unit, the output end of the second switch tube is the output end of the second switch unit, the first pole of the second diode is connected with the input end of the second switch tube, and the second pole of the second diode is connected with the control end of the second switch tube.
In some embodiments, in the above driving chip, the driving chip further includes: an inductance unit;
wherein an input terminal of the second switching unit is connected to the third output terminal through the inductance unit.
In some embodiments, in the above driving chip, the driving chip further includes: a third diode;
the output end of the second switch unit is connected with the first output terminal through the third diode, the first pole of the third diode is connected with the first output terminal, and the second pole of the third diode is connected with the output end of the second switch unit.
In a second aspect, the present application provides a display panel comprising:
the display device comprises a substrate base plate, a display panel and a display panel, wherein the substrate base plate comprises a display area and a non-display area positioned at the periphery of the display area;
a plurality of cascaded driver chips as set forth in any one of the first aspect disposed in the display area;
the plurality of light-emitting units are correspondingly connected with the driving chip respectively and are arranged in the display area;
each output terminal of the driving chip at the upper stage is correspondingly connected with each input terminal of the driving chip at the lower stage;
the first end of the light-emitting unit is connected with a driving signal, and the second end of the light-emitting unit is connected with the corresponding driving chip.
In some embodiments, in the display panel, each output terminal of the driving chip at a previous stage is connected to each input terminal of the driving chip at a next stage through a corresponding first connection line;
and the second end of the light-emitting unit is connected with the output terminal of the Nth group of binding terminals of the driving chip corresponding to the second end of the light-emitting unit through the corresponding second connecting wire.
In some embodiments, in the display panel, the non-display area includes a plurality of binding pins for binding connection with an external driving unit;
the first end of the light-emitting unit and each input terminal of the first-stage driving chip are respectively connected with the corresponding binding pin through the corresponding third connecting line.
In some embodiments, in the display panel, an output terminal of the nth group of bonding terminals of the last stage of the driver chip is connected to the corresponding bonding pin through a fourth connection line.
In some embodiments, in the display panel, an orthogonal projection of the first connecting line, the second connecting line, the third connecting line and the fourth connecting line on the substrate does not overlap an orthogonal projection of a gap between any two terminals in the driving chip on the substrate.
In some embodiments, in the display panel, the first connecting line, the second connecting line, the third connecting line and the fourth connecting line are located in the same layer.
In some embodiments, in the display panel, output terminals of the 1 st group of binding terminals to the N-1 st group of binding terminals of the driver chip at the last stage are all in an idle state.
In some embodiments, in the display panel, N is greater than or equal to 3;
the 1 st group of binding terminals, the 2 nd group of binding terminals and the 3 rd group of binding terminals in the N groups of binding terminals are used for respectively realizing the input and output of a first signal, a second signal and a third signal;
the first signal, the second signal, and the third signal are a power signal, a ground signal, and an address signal, respectively.
In a third aspect, the present application provides a display device comprising the display panel according to any one of the second aspect.
By adopting the technical scheme, the following technical effects can be at least achieved:
the application provides a driving chip, a display panel and a display device, wherein in the driving chip, each group of binding terminals comprises an input terminal and an output terminal, and the input terminal and the output terminal in the same group of binding terminals are used for respectively realizing the input and the output of the same signal; and/or the input terminals in each group of binding terminals are positioned on the same side of the driving chip; the output terminals in each group of binding terminals are positioned on the same side of the driving chip. The lines among the driving chips can utilize vertical space, the lines can be widened, the resistance is reduced, and the large-size and high-resolution display panel is supported. The connecting wires cannot be overlapped and cannot penetrate through the driving chip, and the risk of short circuit of the connecting wires is reduced. And the number of edge winding wires is reduced, and a narrow frame can be realized.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:
FIG. 1 is an external structural diagram of a driving chip;
FIG. 2 is a schematic top view of a display panel;
FIG. 3 is a schematic diagram illustrating an external structure of a driver chip according to an exemplary embodiment of the present application;
FIG. 4 is a schematic diagram of an internal connection frame of a driver chip according to an exemplary embodiment of the present application;
fig. 5 is a schematic circuit diagram of a driving chip according to an exemplary embodiment of the present application;
FIG. 6 is a schematic diagram of another circuit structure of a driver chip according to an exemplary embodiment of the present application;
FIG. 7 is a schematic top view of a display panel shown in an exemplary embodiment of the present application;
FIG. 8 is a schematic flow chart illustrating a method for manufacturing a display panel according to an exemplary embodiment of the present disclosure;
FIG. 9 is a schematic cross-sectional view of a first intermediate structure formed in a process associated with a method of fabricating a display panel according to an exemplary embodiment of the present application;
FIG. 10 is a cross-sectional structural diagram of a second intermediate structure formed in a step associated with a method of fabricating a display panel, according to an exemplary embodiment of the present application;
fig. 11 is a schematic cross-sectional structure diagram of a third intermediate structure formed in a relevant step of a method for manufacturing a display panel according to an exemplary embodiment of the present application.
In the drawings, wherein like parts are designated with like reference numerals, the drawings are not necessarily to scale;
the reference signs are:
11-a substrate base plate; 111-a display area; 112-non-display area; 12-a driver chip; 13-a light-emitting unit; 14-binding pins; 15-a first connection line; 16-a second connecting line; 17-a third connecting line; 18-a fourth connecting line; di-input terminal for addressing signals; out-output terminal of the addressing signal; input terminal of Pwr-power signal; gnd-input terminal for ground signal;
ADDR-addressing signals; PWR-power signal; GND-ground signal; a drive signal-VLED; FB-reflux signal;
21-substrate base plate; 211-a display area; 212-non-display area; 22-a driver chip; 221-a first switching unit; 222-a shift register unit; 223-a second switching unit; 224-a voltage conversion unit; 225-an inductive element; d1-a first diode; d2-a second diode; d3-a third diode; k1-a first opening tube; k2-a second switch tube; 23-a light emitting unit; 24-binding a pin; 25-a third connecting line; 26-a first connection line; 27-a second connecting line; 28-a fourth connecting line; 29-a first binding shim; 30-an inorganic layer; 31-organic layer; 32-opening; gnd In-first input terminal; gnd Out-first output terminal; pwr In-second input terminal; pwr Out-second output terminal; di-a third input terminal; out-a third output terminal.
Detailed Description
The following detailed description will be provided with reference to the accompanying drawings and embodiments, so that how to apply the technical means to solve the technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and various features in the embodiments of the present application can be combined with each other on the premise of no conflict, and the formed technical solutions are all within the protection scope of the present application. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present application, detailed structures and steps will be provided in the following description in order to explain the technical solutions proposed in the present application. The following detailed description of the preferred embodiments of the present application, however, can be practiced otherwise than as specifically described.
An external structure of a driver chip 12 in a display area is shown in fig. 1, which has 4 binding terminals, among them, three input terminals, an input terminal Di of an address signal ADDR, an input terminal PWR of a power signal PWR and an input terminal GND of a ground signal GND, respectively, and an output terminal Out.
The structure of the corresponding display panel is shown in fig. 2, the substrate 11 includes a display region 111 and a non-display region 112, the driving chips 12 are arranged above the display region 111 in a cascade manner, and the light emitting units 13 are arranged above the display region 111 and correspondingly connected to the driving chips 12.
Specifically, the anode of the light emitting unit 13 and the input terminal Di of the address signal ADDR of the first-stage driver chip 12, the input terminal PWR of the power signal PWR of each driver chip 12 and the input terminal GND of the ground signal GND are connected to the corresponding bonding pin 14 through the corresponding first connection line 15, respectively.
The anode of the light emitting unit 13 is connected to the drive signal VLED bonding pin 14, the input terminal Di of the address signal ADDR of the first stage driver chip 12 is connected to the address signal ADDR bonding pin 14, and the input terminal PWR of the power signal PWR and the input terminal GND of the ground signal GND of each driver chip 12 are connected to the power signal PWR bonding pin 14 and the ground signal GND bonding pin 14, respectively.
In order to avoid short circuit caused by overlapping of the first connection lines 15, in the display panel, the first connection lines 15 connecting the input terminal PWR of the power signal PWR of the driver chip 12 with the power signal PWR binding pin 14 pass through the driver chip 12, so that the line width of the connection lines is limited greatly, the resistive load of the connection lines is large, and the signals received by the driver chip 12 at the near end and the driver chip 12 at the far end are inconsistent, so that poor display is caused. And due to the limitation of the line width, the part of the connecting line may be located at a different layer from other connecting lines, and the circuit also may be failed. In addition, the distance between the connection line passing through the interior of the driving chip 12 and each terminal of the driving chip 12 is small, and the risk of short circuit between the connection line and the driving chip 12 is large, so that the requirement on the whole manufacturing process is high.
In the display panel, in the driver chips 12 connected in cascade, the output terminal Out of the driver chip 12 of the previous stage is connected to the input terminal Di of the address signal ADDR of the next stage via the second connection line 16.
The cathodes of the light emitting units 13 are connected to the corresponding driving chips 12 through third connection lines 17.
The anode of the light emitting unit 13 is supplied with a constant voltage VLED by an external driving unit, and the light emitting state of the light emitting unit 13 is controlled by the driving chip 12.
The output terminal Out of the last stage driver chip 12 is connected to the corresponding return signal FB bonding pin 14 through a fourth connection line 18.
In the display panel, the first connection line 15 corresponding to the input terminal Pwr of the driving chip 12 passes through the driving chip 12, and the risk of short circuit is high, so that the requirement on the whole manufacturing process is high.
Therefore, the present embodiment provides a driver chip 22, which includes N groups of binding terminals; each group of binding terminals comprises an input terminal and an output terminal, and the input terminal and the output terminal in the same group of binding terminals are used for respectively realizing input and output of the same signal.
The input terminals in each group of binding terminals are located on the same side of the driver chip 22; and/or the output terminals of each set of binding terminals are located on the same side of the driver chip 22.
This kind of structure makes driver chip 22 when cascading, and the direct output terminal through last level corresponds with the input terminal of next level and is connected and can realize the transmission of signal, the wire winding of the connecting wire that has significantly reduced, and the connecting wire also need not to cross driver chip 22 and sets up, also need not the overlap setting, greatly reduced the short circuit risk of connecting wire. And the connecting lines between the driving chips 22 can be arranged along the same direction, and the line width of the connecting lines can be made as large as possible, so that the resistance can be reduced, and a large-size and high-resolution display panel can be supported.
In some embodiments, the driving chip 22, N is greater than or equal to 3.
Correspondingly, in some embodiments, as shown In fig. 3, the 1 st group of the N groups of binding terminals includes a first input terminal Gnd In and a first output terminal Gnd Out, which are used for respectively implementing input and output of the first signal.
And the 2 nd group of binding terminals In the N groups of binding terminals comprise a second input terminal Pwr In and a second output terminal Pwr Out, and are used for respectively realizing the input and the output of a second signal.
And the 3 rd group of binding terminals in the N groups of binding terminals comprise a third input terminal Di and a third output terminal Out, and are used for respectively realizing the input and the output of a third signal.
In some embodiments, as shown in fig. 4, the driving chip 22 further includes a first switching unit 221, a shift register unit 222, and a second switching unit 223.
The first switch unit 221 has a control terminal connected to the third input terminal Di, and an input terminal connected to the second input terminal Pwr In and the second output terminal Pwr Out, and outputs the second signal when the third signal is at an active level.
The shift register unit 222 has an input terminal connected to the third input terminal Di, and an output terminal connected to the third output terminal Out, for outputting a third signal.
A second switch unit 223, having a control terminal connected to the output terminal of the first switch unit 221, an input terminal connected to the third output terminal Out, and an output terminal connected to the first input terminal Gnd In and the first output terminal Gnd Out, is configured to realize conduction between the third output terminal Out and the first input terminal Gnd In when the output terminal of the first switch unit 221 is at an active level.
In some embodiments, the first signal, the second signal and the third signal are a ground signal GND, a power signal PWR and an address signal ADDR, respectively, the first switching unit 221 is turned on under the control of the address signal ADDR to output the power signal PWR, the second switching unit 223 is used to achieve the conduction between the third output terminal Out and the first input terminal GND In when the output terminal of the first switching unit 221 is at an active level, and the first input terminal GND In is connected to the ground signal GND, so that a current can be delivered from the third output terminal Out to the first input terminal GND In.
The address signal ADDR is shift-output from the third input terminal Di to the third output terminal Out through the shift register unit 222.
In some embodiments, the third output terminal Out is located at an edge position of each output terminal in the driving chip 22 on the side where the output terminal is located, so as to facilitate the subsequent connection with the light emitting unit 23, and reduce the winding.
In some embodiments, as shown In fig. 5, the driving chip 22 further includes a voltage converting unit 224, wherein the input terminal of the first switching unit 221 is connected to the second input terminal Pwr In and the second output terminal Pwr Out through the voltage converting unit 224, and the voltage converting unit 224 is configured to output the second signal input from the second input terminal Pwr In to the input terminal of the first switching unit 221 after performing voltage conversion.
The voltage conversion unit 224 is configured to perform voltage conversion on the second signal input by the second input terminal Pwr In and output the second signal to the input end of the first switch unit 221 as required.
In some embodiments, the driving chip 22 further includes an inductance unit 225, wherein the input terminal of the second switch unit 223 is connected to the third output terminal Out through the inductance unit 225.
Since the inductance unit 225 has a function of flowing through dc and ac, since the address signal ADDR (third signal) is a pulse signal, the address signal ADDR is not transmitted to the input terminal of the second switch unit 223, the address signal ADDR (third signal) is only transmitted to the next-stage driver chip 22, and the signal received at the input terminal of the second switch unit 223 is only a dc voltage signal of the third output terminal Out.
In some embodiments, the driving chip 22 further includes a third diode D3; the output terminal of the second switching unit 223 is connected to the first output terminal Gnd Out through a third diode D3, the first pole of the third diode D3 is connected to the first output terminal Gnd Out, and the second pole of the third diode D3 is connected to the output terminal of the second switching unit 223. The third diode D3 is used to regulate the voltage of the first output terminal Gnd Out.
In some embodiments, as shown in fig. 6, the first switching unit 221 includes a first switching tube K1 and a first diode D1; the control end of the first switch tube K1 is the control end of the first switch unit 221, the input end of the first switch tube K1 is the input end of the first switch unit 221, the output end of the first switch tube K1 is the output end of the first switch unit 221, the first pole of the first diode D1 is connected to the input end of the first switch tube K1, and the second pole of the first diode D1 is connected to the control end of the first switch tube K1.
The first diode D1 is used for stabilizing and protecting the gate of the first switch tube K1, and is used for protecting the first switch tube K1 by breaking down the first diode D1 when the gate voltage of the first switch tube K1 is too high.
In some embodiments, the second switching unit 223 includes a second switching tube K2 and a second diode D2; the control end of the second switch tube K2 is the control end of the second switch unit 223, the input end of the second switch tube K2 is the input end of the second switch unit 223, the output end of the second switch tube K2 is the output end of the second switch unit 223, the first pole of the second diode D2 is connected to the input end of the second switch tube K2, and the second pole of the second diode D2 is connected to the control end of the second switch tube K2.
The second diode D2 is used for stabilizing and protecting the gate of the second switch tube K2, and is used for protecting the second switch tube K2 by breaking down the second diode D2 when the gate voltage of the second switch tube K2 is too high.
In some embodiments, the first switching tube K1 and the second switching tube K2 may be PMOS or CMOS.
Wherein the active level of the PMOS is low. Even if the gate of the PMOS receives a high level, the PMOS does not turn on.
Correspondingly, when the power signal PWR is a high level signal, the high level signal is converted into a low level signal by the voltage conversion unit 224, so as to turn on the second switch tube K2.
Each group of binding terminals comprises an input terminal and an output terminal, and the input terminal and the output terminal in the same group of binding terminals are used for respectively realizing input and output of the same signal; the input terminals in each group of binding terminals are located on the same side of the driver chip 22; the output terminals in each set of binding terminals are located on the same side of the driver chip 22. The lines between the driving chips 22 can utilize a vertical space, and the lines can be made wide, thereby reducing resistance and supporting a large-size and high-resolution display panel. The connecting wires do not overlap and do not pass through the driving chip 22, and the risk of short circuit of the connecting wires is reduced. And the number of edge winding is reduced, and a narrow frame can be realized.
Corresponding to the driving chip 22, the present application further provides a display panel, as shown in fig. 7, including: a base substrate 21, a plurality of the above-described driving chips 22, and a plurality of light emitting units 23.
The substrate base 21 includes a display region 211 and a non-display region 212 located at the periphery of the display region 211.
The plurality of driving chips 22 are arranged in cascade and are disposed in the display region 211. The driver chip comprises N groups of binding terminals, each group of binding terminals comprises an input terminal and an output terminal, the input terminal and the output terminal in the same group of binding terminals are used for respectively realizing input and output of the same signal, and N is larger than or equal to 2. The input terminals in each group of binding terminals are located on the same side of the driver chip 22; and/or the output terminals of each set of binding terminals are located on the same side of the driver chip 22.
Wherein, each output terminal of the previous-stage driver chip 22 is correspondingly connected to each input terminal of the next-stage driver chip 22.
The light emitting units 23 are respectively connected to the driving chips 22 and disposed in the display region 211. The first end of the light emitting unit 23 is connected to the driving signal VLED, and the second end of the light emitting unit 23 is connected to the corresponding driving chip 22.
And a driving chip 22 for controlling a light emitting state of the light emitting unit 23.
This kind of structure makes driver chip 22 when cascading, directly correspond with the input terminal of next stage through the output terminal of last level and be connected and can realize the transmission of signal, the wire winding of the connecting wire that has significantly reduced, and the connecting wire also need not to cross driver chip 22 and sets up, also need not the overlap setting, greatly reduced the short circuit risk of connecting wire. And the connecting lines between the driving chips 22 can be arranged along the same direction, and the line width of the connecting lines can be made as large as possible, so that the resistance can be reduced, and a large-size and high-resolution display panel can be supported.
In some embodiments, each output terminal of the driving chip 22 of the previous stage is connected to each input terminal of the driving chip 22 of the next stage via a corresponding first connection line 26.
The second end of the light emitting unit 23 is connected to the output terminal Out of the nth group binding terminal of the corresponding driving chip 22 through the corresponding second connection line 27.
In some embodiments, the output terminals Out of the nth group of binding terminals are located at the edge of each output terminal in the driving chip 22 on the side where the output terminals are located, so as to facilitate connection with the light emitting unit 23, and reduce winding.
That is to say, in the display panel, in the cascaded driver chip 22, the output terminal directly passing through the previous stage and the input terminal of the next stage are correspondingly connected to realize the signal transmission, and the connecting wire does not need to be arranged around the chip, does not need to be arranged across the driver chip 22, and does not need to be arranged in an overlapping manner, thereby greatly reducing the short circuit risk of the connecting wire. And the connection lines between the driving chips 22 may be arranged in the same direction, and the line width of the connection lines may be made as large as possible, so that the resistance may be reduced, and a large-sized and high-resolution display panel may be supported.
It can be understood that, according to the length of each connection line and the resistance load, the connection line part with longer length can be widened according to the actual requirement.
In some embodiments, the non-display area 212 includes a plurality of binding pins 24 for binding connection with an external driving unit; the first end of the light emitting unit 23 and each input terminal of the first-stage driver chip 22 are connected to the corresponding bonding pin 24 through the corresponding third connection line 25.
That is, except that each input terminal of the first-stage driver chip 22 is connected to the bonding pin 24 to receive each signal output from the external driving unit, the second-stage to last-stage driver chips 22 are not directly connected to the bonding pin 24, but receive signals from the output terminal of the previous-stage driver chip 22, so that the winding of the connection lines is greatly reduced, the connection lines do not need to be transversely arranged on the driver chips 22, the connection lines do not need to be overlapped, and the risk of short circuit of the connection lines is greatly reduced. And the connection lines between the driving chips 22 may be arranged in the same direction, and the line width of the connection lines may be made as large as possible, so that the resistance may be reduced, and a large-sized and high-resolution display panel may be supported.
In some embodiments, the output terminal Out of the nth group of bonding terminals of the last stage driver chip 22 is connected to the bonding pin 24 of the corresponding return signal FB through the fourth connection line 28.
The fourth connection line 28 is disposed at the other side of the driving chip 22 opposite to the light emitting unit 23.
Since the fourth connection line 28 is a return line, and the influence of the transmission quality on the driver chip 22 and the light emitting unit 23 is small, the requirements of the fourth connection line 28 on the resistive load and the line width are low, and therefore, the narrow frame design of the side where the fourth connection line 28 is located can be realized due to the small line width of the fourth connection line 28.
In some embodiments, the orthographic projections of the first connecting line 26, the second connecting line 27, the third connecting line 25 and the fourth connecting line 28 on the substrate base 21 do not overlap with the orthographic projections of the gaps between any two terminals in the driving chip 22 on the substrate base 21.
It can be understood that, in the driving chips 22 in cascade connection, signal transmission can be realized by directly connecting the output terminal of the previous stage with the input terminal of the next stage, and the driving chips 22 do not need to be arranged transversely.
In some embodiments, the first connecting line 26, the second connecting line 27, the third connecting line 25 and the fourth connecting line 28 are located at the same layer. That is to say, since the first connecting line 26, the second connecting line 27, the third connecting line 25 and the fourth connecting line 28 are not overlapped and do not cross the driving chip 22, the first connecting line 26, the second connecting line 27, the third connecting line 25 and the fourth connecting line 28 can be arranged on the same layer, short circuit does not occur, the difficulty of the manufacturing process is reduced, and active single-layer driving is realized.
In some embodiments, the conductive layer may be formed by a magnetron sputtering method or an electroplating method, and then patterned to form the first connection line 26, the second connection line 27, the third connection line 25, and the fourth connection line 28.
The material of the conductive layer comprises copper and can be a MoNb/Cu/CuNi laminated structure.
Correspondingly, a MoNb/Cu/CuNi laminated structure can be formed by a sputtering mode, and an underlayer MoNb (with the thickness of about
) For improved adhesion, an intermediate layer Cu for transmission of electrical signals, and a top layer CuNi (thickness of about
) For preventing oxidation of the interlayer Cu. The stack of MoNb/Cu/CuNi is subsequently patterned to form first 26, second 27, third 25 and fourth 28 connection lines.
In some embodiments, a thicker conductive layer may be formed by multiple sputterings when made because of the limited thickness of a single magnetron sputtering.
In some embodiments, the output terminals of the 1 st to N-1 st groups of bonding terminals of the last stage driver chip 22 are all in an empty state.
In some embodiments, N is greater than or equal to 3; and the 1 st group of binding terminals, the 2 nd group of binding terminals and the 3 rd group of binding terminals in the N groups of binding terminals are used for realizing the input and output of the first signal, the second signal and the third signal respectively.
In some embodiments, the first signal, the second signal, and the third signal are a ground signal GND, a power signal PWR, and an address signal ADDR, respectively.
The first output terminal Gnd Out, the second output terminal Pwr Out, and the third output terminal Out of the driver chip 22 of the previous stage are connected to the first input terminal Gnd In, the second input terminal Pwr In, and the third input terminal Di of the driver chip 22 of the next stage, respectively.
Under the control of the address signal ADDR and the power supply signal PWR, a circuit between the third output terminal Out and the first input terminal Gnd In of the driver chip 22 is turned on.
The driving signal VLED and the power signal PWR may be constant high level signals, the address signal ADDR is a pulse signal, and the address signal ADDR is shifted and output to the third input terminal Di of the driving chip 22 of the next stage through the third output terminal Out by the shift register unit 222 in the driving chip 22 of the previous stage to control the driving chip 22 of the next stage, so as to realize the step-by-step control of the driving chip 22.
In some embodiments, a first end of the light emitting unit 23 is connected to the driving signal VLED, and a second end of the light emitting unit 23 is connected to the third output terminal Out of its corresponding driving chip 22.
Correspondingly, when the circuit between the third output terminal Out of the driving chip 22 and the first input terminal Gnd In is turned on, the circuit between the first end of the light emitting unit 23, the second end of the light emitting unit 23, the third output terminal Out of the driving chip 22 and the first input terminal Gnd In of the driving chip 22 is turned on, and the light emitting unit 23 is turned on under the driving of the driving signal VLED and under the control of the driving chip 22.
When the circuit between the third output terminal Out of the driving chip 22 and the first input terminal Gnd In is opened, the light emitting unit 23 is extinguished, thereby achieving control of the light emitting state of the light emitting unit 23 by the driving chip 22.
In some embodiments, the first end of the light emitting unit 23 is connected to the driving signal VLED bonding pin 24, the input terminal Di of the address signal ADDR of the first-stage driving chip 22 is connected to the address signal ADDR bonding pin 24, and the input terminals PWR In and GND In of the power signals PWR and the ground signals GND of the respective driving chips 22 are respectively connected to the power signal PWR bonding pin 24 and the ground signal GND bonding pin 24.
Since the first end of each light emitting unit 23 is connected to the driving signal VLED bonding pin 24, the third connection line 25 corresponding to each column of light emitting units 23 includes a bus (not labeled) extending along the column direction and a branch (not labeled) for connecting the bus and the first end of the light emitting unit 23, wherein the bus has a longer length, so as to avoid a delay of signal transmission caused by a resistive load, and the line width of the bus can be widened to reduce the resistive load.
The internal circuit structure and the operation principle of the driving chip 22 are the same as those described in the above embodiment of the driving chip 22, and are not described herein again.
In some embodiments, the first end of the light emitting unit 23 is an anode and the second end is a cathode.
In some embodiments, the light emitting unit 23 includes at least one light emitting device sequentially connected in series or in parallel.
It is understood that the light emitting unit 23 includes one or more mini LED or micro LED light emitting devices, and if one light emitting unit 23 includes a plurality of mini LED or micro LED light emitting devices, the mini LED or micro LED light emitting devices are connected in series or in parallel.
On the basis of the display panel, the present application also provides a preparation method of the display panel, as shown in fig. 8, the preparation method includes:
step S110: providing a base substrate 21; the substrate base plate 21 includes a display region 211 and a non-display region 212 located at the periphery of the display region 211.
Step S120: as shown in fig. 9, a first bonding pad 29 and a second bonding pad (not shown in the drawing) for bonding the driving chip 22 and the light emitting unit 23, respectively, are formed over the display region 211.
The first bonding pads 29 include bonding pads for bonding the respective output terminals and the respective input terminals of the driver chip 22, and the second bonding pads include bonding pads for bonding the first and second ends of the light emitting unit 23.
The number of the first bonding pads 29 corresponding to each driver chip 22 is the same as the number of the output terminals and the input terminals of the driver chip 22.
In some embodiments, step S120 includes the steps of:
a first bonding pad 29 and a second bonding pad (not shown in the drawing) for bonding the driver chip 22 and the light emitting unit 23, respectively, are formed over the display region 211, a bonding pin 24 for bonding the external driver unit is formed over the non-display region 212, and a third connection line 25 for connecting the bonding pin 24 and the corresponding first bonding pad 29 and second bonding pad is formed, a first connection line 26 for connecting the first bonding pads 29 corresponding to the two driver chips 22, and a second connection line 27 for connecting the first bonding pads 29 corresponding to the driver chip 22 and the second bonding pads corresponding to the light emitting unit 23 are formed over the display region 211.
It is understood that the bonding pads for bonding the driving chip 22 and the light emitting unit 23 and the bonding pins 24 of the non-display region 212, and the subsequent connection lines for connecting the driving chip 22, the light emitting unit 23 and the bonding pins 24 are formed simultaneously, and the same material may be used for the bonding pads, the bonding pins 24 and the respective connection lines.
It should be noted that fig. 9 shows the positions and structures of the first bonding pads 29 and the first connection lines 26, but the positions and structures of the second bonding pads, the bonding pins 24, and other connection lines can be understood from the top view of the display panel shown in fig. 7.
In some embodiments, the conductive layer may be formed by a magnetron sputtering method or an electroplating method, and then patterned to form the bonding pads, the bonding pins 24, and the respective connection lines.
The material of the conductive layer comprises copper and can be a MoNb/Cu/CuNi laminated structure.
Correspondingly, a MoNb/Cu/CuNi laminated structure can be formed by sputtering, and the bottom layer MoNb (with the thickness of about
) For improved adhesion, an intermediate layer Cu for transmission of electrical signals, and a top layer CuNi (thickness of about
) For preventing oxidation of the interlayer Cu. The stack of MoNb/Cu/CuNi is then patterned to form bond pads, bond pins 24, and various bond wires.
In some embodiments, a thicker conductive layer may be formed by multiple sputterings when made because of the limited thickness of a single magnetron sputtering.
Step S130: as shown in fig. 10, an insulating layer is formed to cover the first bonding pad 29 and the second bonding pad, and an opening 32 is formed through the insulating layer at a position corresponding to the first bonding pad 29 and the second bonding pad, respectively, on the insulating layer, so that an orthographic projection of the insulating layer on the base substrate 21 does not cover an orthographic projection of the first bonding pad 29 and the second bonding pad on the base substrate 21.
The insulating layer includes an inorganic layer 30 and an organic layer 31 covering the silicon nitride layer, the inorganic layer 30 may be a silicon nitride layer, and the organic layer 31 may be an optical glue layer.
In addition, the insulating layer is also formed with openings at corresponding positions of the bonding pins 24 for subsequent bonding of the chip on film. However, no opening is provided above each connection line to protect each connection line by an insulating layer.
Step S140: as shown in fig. 11, the plurality of driving chips 22 and the plurality of light emitting cells 23 are bound on the base substrate 21 by first and second binding pads 29 and 29, respectively; the plurality of driving chips 22 are arranged in a cascade manner, and the driving chips 22 are correspondingly connected with the light emitting units 23.
Through the connecting line connected to the bonding pad and the bonding pin 24, cascade connection of the plurality of driver chips 22, connection of the driver chips 22 and the light emitting unit 23, and connection of the driver chips 22 and the light emitting unit 23 and the bonding pin 24 are achieved, and the specific connection mode is the same as that in the above-described display panel embodiment, and is not described herein again.
After step S140, the following steps may be further included: a flip chip (not shown) is bonded to the substrate 21 through the bonding pins 24 to connect the display panel with an external driving unit.
The embodiment of the application also provides a display device which comprises the display panel.
In some embodiments, the display device further comprises a housing, the display panel being connected to the housing, e.g. the display panel being embedded in the housing. The display device can be any device with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. Although the embodiments disclosed in the present application are described above, the embodiments are merely used for the understanding of the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.
Claims (15)
1. A drive chip is characterized by comprising N groups of binding terminals;
each group of binding terminals comprises an input terminal and an output terminal, and the input terminal and the output terminal in the same group of binding terminals are used for realizing the input and the output of the same signal respectively;
the input terminals in each group of binding terminals are positioned on the same side of the driving chip; and/or the output terminals in each group of binding terminals are positioned on the same side of the driving chip;
n is greater than or equal to 3;
the 1 st group of binding terminals in the N groups of binding terminals comprise first input terminals and first output terminals, and are used for respectively realizing input and output of first signals;
the 2 nd group of binding terminals in the N groups of binding terminals comprise a second input terminal and a second output terminal which are used for respectively realizing the input and the output of a second signal;
the 3 rd group of binding terminals in the N groups of binding terminals comprise a third input terminal and a third output terminal which are used for respectively realizing the input and the output of a third signal;
the driving chip further includes:
a first switch unit having a control terminal connected to the third input terminal and an input terminal connected to the second input terminal and the second output terminal, for outputting the second signal when the third signal is at an active level;
a shift register unit having an input terminal connected to the third input terminal and an output terminal connected to the third output terminal, for outputting the third signal;
and the control end of the second switch unit is connected with the output end of the first switch unit, the input end of the second switch unit is connected with the third output terminal, and the output end of the second switch unit is connected with the first input terminal and the first output terminal, so that the third output terminal and the first input terminal are conducted when the output end of the first switch unit is at an active level.
2. The driver chip of claim 1, wherein the driver chip further comprises: a voltage conversion unit;
the input end of the first switch unit is connected to the second input terminal and the second output terminal through the voltage conversion unit, and the voltage conversion unit is configured to perform voltage conversion on the second signal input by the second input terminal and output the second signal to the input end of the first switch unit.
3. The driving chip according to claim 1, wherein the first switching unit comprises a first switching tube and a first diode;
the control end of the first switch tube is the control end of the first switch unit, the input end of the first switch tube is the input end of the first switch unit, the output end of the first switch tube is the output end of the first switch unit, the first pole of the first diode is connected with the input end of the first switch tube, and the second pole of the first diode is connected with the control end of the first switch tube.
4. The driving chip of claim 1, wherein the second switching unit comprises a second switching tube and a second diode;
the control end of the second switch tube is the control end of the second switch unit, the input end of the second switch tube is the input end of the second switch unit, the output end of the second switch tube is the output end of the second switch unit, the first pole of the second diode is connected with the input end of the second switch tube, and the second pole of the second diode is connected with the control end of the second switch tube.
5. The driver chip of claim 1, wherein the driver chip further comprises: an inductance unit;
wherein an input terminal of the second switching unit is connected to the third output terminal through the inductance unit.
6. The driver chip of claim 1, wherein the driver chip further comprises: a third diode;
the output end of the second switch unit is connected with the first output terminal through the third diode, the first pole of the third diode is connected with the first output terminal, and the second pole of the third diode is connected with the output end of the second switch unit.
7. A display panel, comprising:
the display device comprises a substrate base plate, a display panel and a display panel, wherein the substrate base plate comprises a display area and a non-display area positioned at the periphery of the display area;
a plurality of cascaded driver chips as claimed in any one of claims 1 to 6 disposed within the display area;
the plurality of light-emitting units are respectively correspondingly connected with the driving chip and arranged in the display area;
each output terminal of the driving chip at the upper stage is correspondingly connected with each input terminal of the driving chip at the lower stage;
the first end of the light-emitting unit is connected with a driving signal, and the second end of the light-emitting unit is connected with the corresponding driving chip.
8. The display panel according to claim 7, wherein each output terminal of the driving chip of a previous stage is connected to each input terminal of the driving chip of a next stage via a corresponding first connection line;
and the second end of the light-emitting unit is connected with the output terminal of the Nth group of binding terminals of the driving chip corresponding to the second end of the light-emitting unit through the corresponding second connecting wire.
9. The display panel according to claim 8, wherein the non-display area includes a plurality of binding pins for binding connection with an external driving unit;
the first end of the light-emitting unit and each input terminal of the first-stage driving chip are respectively connected with the corresponding binding pin through the corresponding third connecting line.
10. The display panel according to claim 9, wherein an output terminal of the nth group of bonding terminals of the driving chip at the last stage is connected to the corresponding bonding pin through a fourth connection line.
11. The display panel according to claim 10, wherein orthographic projections of the first connecting line, the second connecting line, the third connecting line and the fourth connecting line on the substrate base plate do not overlap with orthographic projections of a gap between any two terminals in the driving chip on the substrate base plate.
12. The display panel according to claim 10, wherein the first connection line, the second connection line, the third connection line, and the fourth connection line are located in the same layer.
13. The display panel according to claim 7, wherein each of the output terminals of the 1 st to N-1 st groups of binding terminals of the driver chip of the last stage is in an empty state.
14. The display panel according to claim 7, wherein N is 3 or more;
the 1 st group of binding terminals, the 2 nd group of binding terminals and the 3 rd group of binding terminals in the N groups of binding terminals are used for respectively realizing the input and output of a first signal, a second signal and a third signal;
the first signal, the second signal, and the third signal are a ground signal, a power signal, and an address signal, respectively.
15. A display device characterized by comprising the display panel according to any one of claims 7 to 14.
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| CN114677927B (en) * | 2022-03-16 | 2023-08-22 | Tcl华星光电技术有限公司 | display panel |
| CN114420720B (en) * | 2022-03-29 | 2022-06-17 | 季华实验室 | MicroLED display panel manufacturing method and display panel |
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| KR102573291B1 (en) * | 2017-12-29 | 2023-08-30 | 엘지디스플레이 주식회사 | Light emitting display device |
| CN113168817B (en) * | 2018-12-13 | 2022-08-16 | 深圳市柔宇科技股份有限公司 | Repairable GOA driving system, driving method of GOA circuit and display panel |
| US10950194B1 (en) * | 2019-10-04 | 2021-03-16 | Solomon Systech (Shenzhen) Limited | Display panel with distributed driver network |
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| CN214012484U (en) * | 2020-12-17 | 2021-08-20 | 京东方科技集团股份有限公司 | Display device |
| CN116312350A (en) * | 2021-05-06 | 2023-06-23 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
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