CN214012484U - Display device - Google Patents
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- CN214012484U CN214012484U CN202023056358.6U CN202023056358U CN214012484U CN 214012484 U CN214012484 U CN 214012484U CN 202023056358 U CN202023056358 U CN 202023056358U CN 214012484 U CN214012484 U CN 214012484U
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Abstract
The application discloses a display device for avoiding the uneven brightness of a block and improving the display effect. The application provides a display device including: the display panel is provided with a plurality of cascaded driving chips; each driving chip includes: the display device comprises a plurality of display signal input ends, display signal output ends which correspond to the display signal input ends one to one, and at least one voltage compensation circuit; each voltage compensation circuit is electrically connected with one display signal input end and one display signal output end respectively; except the last stage of driving chip, each display signal output end of each driving chip is electrically connected with each display signal input end of the next stage adjacent one by one; the voltage compensation circuit is used for: and according to the display signals received by the display signal input end, performing voltage compensation on the display signals to generate compensated display signals, and outputting the compensated display signals to the display signal output end, so that the difference between the same kind of compensated display signals output by any adjacent driving chips is smaller than a preset value.
Description
Technical Field
The application relates to the technical field of display, in particular to a display device.
Background
In order to reduce the seams of the spliced display screen and improve the display effect of the spliced product, the spliced screen product is usually designed by adopting a narrow frame. The conventional tiled screen generally needs to be provided with a plurality of driver chips, the driver chips are bound with a display panel through a Chip On Flex (COF), and a Printed Circuit Board (PCB) is arranged at the edge of the display screen to provide signals for the driver chips. The display screen has the limit that extends along first direction (X direction) and second direction (Y direction), and one of them scheme of prior art all needs to set up PCB at the edge of X direction and the edge of Y direction, and the cost is higher, and process flow is complicated. In another scheme of the prior art, the PCB on the edge in the Y direction is removed, but the impedance of part of signal traces between different COFs is large, the voltage drop of part of signals is large, the voltage difference of signals output by adjacent driving chips is large, and uneven brightness of blocks (blocks) is likely to occur, which affects the display effect.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides a display device, which is used for avoiding the uneven brightness of a block and improving the display effect.
An embodiment of the present application provides a display device, the display device includes: the display device comprises a display panel, a plurality of cascaded driving chips and a plurality of driving units, wherein the plurality of cascaded driving chips are bound on one side of the display panel;
each of the driving chips includes: the display device comprises a plurality of display signal input ends, display signal output ends which correspond to the display signal input ends one to one, and at least one voltage compensation circuit;
each voltage compensation circuit is electrically connected with one display signal input end and one display signal output end respectively;
except the driving chip of the last stage, the display signal output end of each driving chip is electrically connected with the display signal input end of the next stage adjacent to the display signal output end of the last stage in a one-to-one correspondence manner;
the voltage compensation circuit is used for: and according to the display signal received by the display signal input end, performing voltage compensation on the display signal to generate a compensated display signal, and outputting the compensated display signal to the display signal output end, so that the difference between the compensated display signals output by any adjacent driving chips in the same type is smaller than a preset value.
In some embodiments, the voltage compensation circuit comprises: a comparison unit;
the first input end of the comparison unit is electrically connected with one display signal input end, and the second input end of the comparison unit is electrically connected with a reference signal input end;
the comparison unit is used for: and determining the difference value of the display signal and the reference signal according to the display signal received by the display signal input end and the reference signal received by the reference signal input end, and generating and outputting a voltage compensation signal of the display signal according to the difference value of the display signal and the reference signal.
In some embodiments, the comparison unit comprises: a comparator, and an operational amplifier;
the first input end of the comparator is electrically connected with one display signal input end, the second input end of the comparator is electrically connected with the reference signal input end, the output end of the comparator is electrically connected with the input end of the operational amplifier, and the output end of the operational amplifier outputs the voltage compensation value of the display signal.
In some embodiments, the voltage compensation circuit further comprises: a low dropout linear regulator;
the input end of the low dropout linear regulator is electrically connected with the display signal input end, and the output end of the low dropout linear regulator is electrically connected with the first input end of the comparator.
In some embodiments, the voltage compensation circuit further comprises: an adder;
the first input end of the adder is electrically connected with the output end of the comparison unit, the second input end of the adder is electrically connected with the display signal input end, and the output end of the adder is electrically connected with the display signal output end.
In some embodiments, the voltage compensation signal for each of the display signals generated by different ones of the driving chips has the same value.
In some embodiments, in different driving chips, the difference between the display signal input by the voltage compensation circuit and the signal input by the reference signal terminal is equal.
In some embodiments, the plurality of display signal inputs comprises: a first power signal input, a first voltage signal input, and a second voltage signal input;
at least one of the voltage compensation circuits comprises: the voltage compensation circuit comprises a first voltage compensation circuit electrically connected with the first power signal input end, a second voltage compensation circuit electrically connected with the first voltage signal input end, and a third voltage compensation circuit electrically connected with the second voltage signal input end.
In some embodiments, the display device further comprises: a chip on film circuit board; the driving chip is bound with the display panel through the chip on film circuit board;
the display panel includes: the display device comprises a display area and a peripheral area positioned outside the display area;
the peripheral zone includes: a plurality of first bonding terminals and a plurality of second bonding terminals bonded to each of the COF boards, and a plurality of connection leads;
the first binding terminals are electrically connected with the display signal input ends in a one-to-one correspondence manner through the chip on film circuit board, and the second binding terminals are electrically connected with the display signal output ends in a one-to-one correspondence manner through the chip on film circuit board;
the first binding terminals and the second binding terminals bound with the adjacent chip on film circuit boards are electrically connected in a one-to-one correspondence mode through the connecting leads;
the connecting lead is located at a different film layer from the first binding terminal and the second binding terminal.
In some embodiments, the display area comprises: a source drain electrode layer, a gate electrode layer, and a transparent electrode layer;
the first binding terminal and the second binding terminal are arranged on the same layer as the source and drain electrode layer;
the connection lead includes: the first sub-lead is arranged on the same layer as the grid layer, and the second sub-lead is arranged on the same layer as the transparent electrode layer;
an extending direction of the first sub-lead crosses an extending direction of the first binding terminal and the second binding terminal;
the first sub-lead is electrically connected to the first binding terminal and the second binding terminal through the second sub-lead, respectively.
According to the display device provided by the embodiment of the application, the plurality of driving chips are arranged in a cascade mode, so that a printed circuit board is not required to be arranged to provide signals for the driving chips, the assembling process of the display device can be simplified, and the cost can be saved. And set up the voltage compensation circuit in driver chip, when showing that the signal voltage drop appears in the transmission course, the voltage compensation circuit can compensate the voltage that shows the signal for the difference of the display signal voltage after the same kind compensation of arbitrary adjacent driver chip output is less than the default, avoids the same kind of display signal voltage difference of adjacent driver chip output great, avoids appearing the block luminance inequality, improves the display effect, promotes user experience.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a display device according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a driving chip in a display device according to an embodiment of the present disclosure;
fig. 3 is a schematic view of another display device provided in an embodiment of the present application;
FIG. 4 is a cross-sectional view of AA' of FIG. 3 according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings of the embodiments of the present application. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all embodiments. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the application without any inventive step, are within the scope of protection of the application.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. As used in this application, the terms "first," "second," and the like do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
It should be noted that, in the related art, in the display signal transmission process, since the transmission lead is electrically connected to the driving chip, that is, the transmission lead is electrically connected to the load, the current exists in the line, and thus the transmission lead has impedance, which causes a voltage drop in the display signal transmission process through the transmission lead. When the voltage drop is too large, the voltage value of the display signal may be lower than the voltage range of the driving chip, which may cause abnormal display, and the voltage difference between the display signals output by the adjacent driving chips may be large, which may cause uneven brightness of the block and affect the display effect.
In view of the above problems in the related art, embodiments of the present application provide a display device, as shown in fig. 1 and 2, the display device including: the display device comprises a display panel 1, a plurality of cascaded driving chips 2 bound on one side of the display panel 1;
each of the driving chips 2 includes: the display device comprises a plurality of display signal input ends 3, display signal output ends 4 corresponding to the display signal input ends 3 one by one, and at least one voltage compensation circuit 5;
each voltage compensation circuit 5 is electrically connected with one display signal input end 3 and one display signal output end 4 respectively;
except for the driving chip 2 at the last stage, each display signal output end 3 of each driving chip 2 is electrically connected with each display signal input end 4 of the next adjacent stage in a one-to-one correspondence manner;
the voltage compensation circuit 5 is configured to: according to the display signal received by the display signal input end 3, performing voltage compensation on the display signal to generate a compensated display signal, and outputting the compensated display signal to the display signal output end 4, so that the voltage difference between the display signals output by any adjacent driving chips 2 and subjected to the same type of compensation is smaller than a preset value.
In specific implementation, the preset values may be: when the display device has uneven brightness of the blocks, the adjacent driving chips output the theoretical value of the difference between the voltages of the same display signals.
According to the display device provided by the embodiment of the application, the plurality of driving chips are arranged in a cascade mode, so that a printed circuit board is not required to be arranged to provide signals for the driving chips, the assembling process of the display device can be simplified, and the cost can be saved. And set up the voltage compensation circuit in driver chip, when showing that the signal voltage drop appears in the transmission course, the voltage compensation circuit can compensate the voltage that shows the signal for the difference of the display signal voltage after the same kind compensation of arbitrary adjacent driver chip output is less than the default, avoids the same kind of display signal voltage difference of adjacent driver chip output great, avoids appearing the block luminance inequality, improves the display effect, promotes user experience.
In a specific implementation, in the display device provided in the embodiment of the present application, the display panel includes a plurality of sub display panels that are tiled.
In some embodiments, as shown in fig. 2, the voltage compensation circuit 2 includes: a comparison unit 6;
a first input terminal of the comparison unit 6 is electrically connected to one of the display signal input terminals 3, and a second input terminal of the comparison unit 6 is electrically connected to a reference signal input terminal 20;
the comparison unit 6 is configured to: according to the display signal received by the display signal input terminal 3 and the reference signal received by the reference signal input terminal 20, the difference value between the display signal and the reference signal is determined, and according to the difference value between the display signal and the reference signal, the voltage compensation signal δ V of the display signal is generated and output.
It should be noted that the display signal received by the display signal input terminal is a signal in which a voltage drop occurs through the transmission lead. The reference signal corresponds to the display signal received by the voltage compensation circuit, and when the voltage compensation circuit is implemented specifically, the reference signal can be received through the non-load lead wire, so that even if the reference signal with the thin lead wire width does not generate voltage drop, the wiring space of the driving chip can be saved. The specific value of the reference signal can be set according to actual needs.
In some embodiments, as shown in fig. 2, the comparison unit 6 comprises: a comparator 7, and an operational amplifier 8;
a first input terminal of the comparator 7 is electrically connected to one of the display signal input terminals 3, a second input terminal of the comparator 7 is electrically connected to the reference signal input terminal 20, an output terminal of the comparator 7 is electrically connected to an input terminal of the operational amplifier 8, and an output terminal of the operational amplifier 8 outputs a voltage compensation value of the display signal.
In specific implementation, the amplification factor of the operational amplifier can be adjusted as required to adjust the voltage compensation value of the display signal.
In some embodiments, as shown in fig. 2, the voltage compensation circuit further includes: a low dropout linear regulator (LDO) 9;
the input end of the low dropout linear regulator is electrically connected with the display signal input end, and the output end of the low dropout linear regulator is electrically connected with the first input end of the comparator.
Namely, the first input end of the comparator is electrically connected with the display signal input end through the LDO.
In specific implementation, the LDO and the operational amplifier are arranged to play a role in isolating the load, so that the load capacity and the impedance matching performance of the display signal are improved.
In some embodiments, as shown in fig. 2, the voltage compensation circuit further includes: an adder 10;
a first input terminal of the adder 10 is electrically connected to the output terminal of the comparison unit 6, a second input terminal of the adder 10 is electrically connected to the display signal input terminal 3, and an output terminal of the adder 10 is electrically connected to the display signal output terminal 4.
In some embodiments, the display panel includes a gate driving circuit, and the driving chip including the voltage compensation circuit is electrically connected to the gate driving circuit. In a specific implementation, the driving chip further includes an output unit electrically connected to the gate driving circuit, and the output unit is electrically connected to the output end of each voltage compensation circuit, so that the driving chip can provide the compensated display signal to the gate driving circuit.
In some embodiments, as shown in fig. 2, a plurality of the display signal input terminals 3 includes: a first power signal input terminal 11, a first voltage signal input terminal 12, and a second voltage signal input terminal 13;
the corresponding driver chip includes three voltage compensation circuits 5, three of the voltage compensation circuits 5 including: a first voltage compensation circuit 14 electrically connected to the first power signal input terminal 11, a second voltage compensation circuit 15 electrically connected to the first voltage signal input terminal 12, and a third voltage compensation circuit 16 electrically connected to the second voltage signal input terminal 13.
Correspondingly, the display signal output end comprises: a first power signal output terminal 17, a first voltage signal output terminal 18, and a second voltage signal output terminal 19.
In a specific implementation, the first power signal input terminal receives a first power signal (DVDD), the first voltage signal input terminal receives a first voltage signal (VGH), and the second voltage signal input terminal receives a second voltage signal (VGL). The first power supply signal may be, for example, a high level voltage signal. The gate driving circuit includes a thin film transistor, and the first voltage signal may be, for example, a voltage signal for controlling the thin film transistor to be turned on, and the second voltage signal may be, for example, a voltage signal for controlling the thin film transistor to be turned off. Therefore, the display device provided by the embodiment of the application has the advantages that the voltage compensation circuit is arranged on the driving chip electrically connected with the grid driving circuit, so that voltage compensation can be carried out on the VGH and the VGL, the thin film transistor is prevented from being started due to the fact that the voltage drop of the VGH and the VGL is large, and abnormal display is avoided.
In a specific implementation, as shown in fig. 2, in the first voltage compensation circuit 14, the reference voltage signal terminal 20 receives a reference signal of the first voltage signal, and the voltage value of the reference signal of the first voltage signal is Vdd'. In the second voltage compensation circuit 15, the reference voltage signal terminal 20 receives the reference signal of the first voltage signal, and the voltage value of the reference signal of the first voltage signal is Vgh'. In the third voltage compensation circuit 16, the reference voltage signal terminal 20 receives a reference signal of the second voltage signal, and the voltage value of the reference signal of the second voltage signal is Vgl'.
In addition to DVDD, VGH, and VGL, display signals such as a ground level signal (GND), a Vertical Clock signal (CPV), a Start signal (Start Vertical, STV), an Output control signal (Output Enable, OE1), an Output all-On control (XON), an Up and down control signal (UD), and a common voltage signal (VCOM) are supplied to the gate driver circuit. The display signals except for DVDD, VGH, and VGL may not be connected to the voltage compensation circuit, but a corresponding display signal input terminal and a corresponding display signal output terminal still need to be provided on the driving chip, and the output unit electrically connected to the gate driving circuit in the driving chip also needs to output other display signals except for DVDD, VGH, and VGL.
In some embodiments, as shown in fig. 1, the display device further includes: a Chip On Film (COF) 21; the driving chip 2 is bound with the display panel 1 through the chip on film circuit board 21.
In a specific implementation, as shown in fig. 1, the display panel 1 includes: a display area 22, and a peripheral area 23 outside the display area 22. According to the display device provided by the embodiment of the application, the Printed Circuit Board (PCB) for providing signals for the driving chips is not arranged on one side of the gate driving circuit, so that the driving chips arranged in the Y direction are sequentially and electrically connected. Since the driver chips are bonded to the display panel through the COF, as shown in fig. 1, connection signal lines are required to be disposed in the COF and the peripheral region of the display panel to provide display signals to the driver chips. In specific implementation, as shown in fig. 1, a plurality of source COFs 24 are required to be arranged in the X direction and bound to the edge of the display panel, the display device further includes a Timing Controller (TCON) for generating display signals to be transmitted through the source COFs 24, and the display signals are transmitted to the display signal input end of the first driving chip 2 arranged in the Y direction through a first connection signal line 25 electrically connected to the source COFs 24, and the transmission of the display signals between adjacent driving chips 2 is realized through a second connection signal line 26. It should be noted that fig. 1 only shows a part of the display device, and fig. 1 only illustrates transmission of DVDD, VGH, and VGL.
In specific implementation, the example of setting 8 cascaded driving chips in the Y direction is taken to exemplify voltage compensation of the display device provided by the embodiment of the present application on DVDD, VGH, and VGL.
The voltage of DVDD generated by TCON is Vdd, the voltage of VGH generated by TCON is Vgh, the voltage of VGL generated by TCON is Vgl, and the voltage drops of Vdd, Vgh and Vgl transmitted to the display signal input end of the first driving chip through the first connecting signal line are respectively a, b and c, so that the voltages of DVDD, VGH and VGL received by the display signal input end of the first driving chip are respectively Vdd-a, Vgh-b and Vgl-c, the voltage compensation value generated by the first voltage compensation circuit is delta V1, the voltage compensation value generated by the second voltage compensation circuit is delta V2, and the voltage compensation value generated by the third voltage compensation circuit is delta V3, so that the voltages of DVDD, VGH and VGL after compensation output by the display signal output end of the first driving chip are respectively Vdd-a + delta V1, Vgh-b + delta V2, Vgl-c + delta V3.
For any two adjacent driving chips, the display signals output by the output terminals of the DVDD, VGH and VGL are transmitted to the display signal input terminal of the next driving chip through the second connection signal line, and the voltage drops of the DVDD, VGH and VGL in the transmission process are V1V 2V 3 respectively. Therefore, the voltages of DVDD, VGH and VGL received by the display signal input end of the second driving chip are Vdd + delta V1-a- & ltV & gt 1, Vgh + delta V2-b- & ltV & gt 2 and Vgl + delta V3-c- & ltV & gt 3 respectively, the voltage compensation value generated by the first voltage compensation circuit in the second driving chip is delta V1 ', the voltage compensation value generated by the second voltage compensation circuit is delta V2', the voltage compensation value generated by the third voltage compensation circuit is delta V3 ', therefore, the voltages of the compensated DVDD, VGH and VGL output by the display signal output end of the second driving chip are Vdd-a + delta V1- & ltV 1+ delta V1', gh-b + delta V2- & ltV 2+ delta V2 ', Vgl-c + delta V3- & ltV 3- & ltV 7', and the voltage difference between the voltages of the second driving chip and the voltage output by the second driving chip is Vdd + delta V3-V The voltage difference of the VGH and the voltage difference of the VGL are δ V1 '-, -V1, δ V2' -, -V2, δ V3 '-, -V3 respectively, wherein the preset value of the difference of the display signal voltages output by adjacent driving chips is V0, so δ V1' -, -V1 < V0, δ V2 '-, -V2 < V0, δ V3' - > V3 < V0.
By analogy, in the (n + 1) th driving chip, the voltage compensation value generated by the first voltage compensation circuit is delta V1n', the voltage compensation value generated by the second voltage compensation circuit is delta V2n', the voltage compensation value generated by the third voltage compensation circuit is delta V3n'. The voltage difference output by the n +1 th driving chip and the nth driving chip is delta V1n’-▽V1、δV2n’-▽V2、δVn3' -. V3, thus δ V1n’-▽V1＜V0、δV2n’-▽V2＜V0、δVn3' -. V3 < V0. Thus, the voltage difference of the DVDD, the voltage difference of the VGH and the voltage difference of the VGL output by the first driver chip and the last driver chip are respectively delta V1' + delta V1 "+ … + delta V17’-7▽V1，δV2’+δV2”+…+δV27’-7▽V2，δV3’+δV3”+…+δV37’-. 7V3, and δ V1' + δ V1 "+ … + δ V17’-7▽V1＜V0，δV2’+δV2”+…+δV27’-7▽V2＜V0，δV3’+δV3”+…+δV37’V7V 3 is less than V0, so that when the difference between the voltages of the display signals output by any adjacent driver chips after the same compensation is smaller than a preset value, the voltage difference between the voltage signals output by the first driver chip and the last driver chip can be ensured to meet the Specification (SPEC) of the driver chips, the voltage range of the display signals lower than the voltage range of the driver chips can be avoided, and abnormal display is avoided.
In some embodiments, the voltage compensation signal for each of the display signals generated by different ones of the driving chips has the same value.
In specific implementation, the same specification driving chips are usually adopted on the same side of the display panel, and the voltage compensation signals of each display signal generated by different driving chips have the same value, so that the voltage compensation multiples of the display signals by the driving chips with the same specification are consistent. Taking the example of 8 cascaded driving chips arranged in the Y direction, it is necessary to satisfy δ V1 ═ δ V1 ═ … … ═ δ V17’、δV2’＝δV2”＝……＝δV27’、δV3’＝δV3”＝……＝δV37’。
In order to ensure that the compensation multiples of different driving chips for the display signals are consistent, in some embodiments, the difference between the display signal input by the voltage compensation circuit and the signal input by the reference signal terminal is equal in different driving chips.
Still taking the example of 8 cascaded driver chips arranged in the Y direction, since the voltage differences of DVDD, VGH, and VGL with respect to the respective reference voltages in the first driver chip are: a. b, c; the voltage differences of DVDD, VGH, and VGL in the second driver chip with respect to the respective reference voltages are: δ V1-, (V1), δ V2-, (V2), δ V3-, (V3); the voltage differences of DVDD, VGH, and VGL in the third driver chip with respect to the respective reference voltages are: δ V1 ^ V1, δ V2 ^ V2, δ V3 ^ V3, and so on, in order to ensure that the voltage compensation multiples of the display signals by the driving chips are consistent, the voltage difference between the voltage of the display signals received by the compensation modules of different driving chips and the reference voltage needs to be equal. That is, δ V1 ═ V1 ═ a, δ V2 ═ V2 ═ b, δ V3 ═ V3 ═ c needs to be satisfied.
In specific implementation, the wiring space of each first connecting signal line electrically connected with the first driving chip is large, and the line width of the first connecting signal line can be adjusted to enable the values of a, b and c to be very small, so that the impedance of the first connecting signal line can be reduced, and the voltage drop of the display signal can be further reduced.
In some embodiments, as shown in fig. 3 and 4, wherein fig. 4 is a cross-sectional view along AA' of fig. 3, the peripheral area 23 includes: a plurality of first bonding terminals 26 and a plurality of second bonding terminals 27 bonded to each of the chip on film circuit boards 21, and a plurality of connecting leads 28;
the first binding terminals 26 are electrically connected with the display signal input ends in a one-to-one correspondence manner through the chip on film circuit board 21, and the second binding terminals 27 are electrically connected with the display signal output ends in a one-to-one correspondence manner through the chip on film circuit board 21;
the first bonding terminals 26 and the second bonding terminals 27 bonded to the adjacent chip on film circuit board 21 are electrically connected in a one-to-one correspondence manner through the connection leads 28;
the connecting lead 28 and the first and second binding terminals 26 and 27 are located at different film layers.
The first binding terminal, the second binding terminal, and the connecting lead may be a portion of the second connecting signal line on the display panel.
The embodiment of the application provides a display device, the display panel edge is provided with the first terminal of binding that connects adjacent driver chip electricity, terminal and connecting lead are bound to the second, connecting lead and first terminal and the second of binding are located different retes, the connecting lead that is located different retes is bound terminal and second with first terminal and the conflict of binding terminal wiring space, thereby can increase first terminal of binding, the terminal is bound to the second, the line width of connecting lead, further reduce the impedance of the second connecting signal line with adjacent driver chip electricity connection, further reduce the voltage difference between the display signal of adjacent driver chip output, avoid appearing the uneven demonstration of block luminance etc. bad, improve display effect.
In specific implementation, the connecting leads positioned on different film layers are not in conflict with wiring spaces of the first binding terminal and the second binding terminal, so that the widths of the first binding terminal and the second binding terminal bound with the chip on film circuit board can be increased, and the binding impedance can be reduced.
In some embodiments, the display area comprises: a source drain electrode layer, a gate electrode layer, and a transparent electrode layer;
as shown in fig. 3 and 4, the first binding terminal 26 and the second binding terminal 27 are disposed in the same layer as the source/drain electrode layer;
the connection lead includes: a first sub-lead 29 provided in the same layer as the gate electrode layer, and a second sub-lead 30 provided in the same layer as the transparent electrode layer;
the extending direction Y of the first sub-lead 29 intersects the extending direction X of the first binding terminal 26 and the second binding terminal 27;
the first sub-lead 29 is electrically connected to the first binding terminal 26 and the second binding terminal 27 through the second sub-lead 30, respectively.
In specific implementation, as shown in fig. 4, the display panel further includes: a substrate base 31, a first insulating layer 32 between the first binding terminal 26 and the first sub-lead 29, and a second insulating layer 33 between the first binding terminal 26 and the second sub-lead 30. The second sub-lead 30 is electrically connected to the first binding terminal 26 through a via hole penetrating the second insulating layer 33, and the second sub-lead 30 is electrically connected to the first sub-lead 29 through a via hole penetrating the second insulating layer 33 and the first insulating layer 32.
In a specific implementation, the overall impedance of the connection lead, the first bonding terminal and the second bonding terminal can be adjusted by adjusting the line width of the first sub-lead.
In particular implementations, the via hole may have a pore size of, for example, 3 microns to 5 microns.
In specific implementation, the display panel provided in the embodiment of the present application may be a liquid crystal display panel, and the liquid crystal display panel includes: the liquid crystal display panel comprises an array substrate, an opposite substrate and a liquid crystal layer, wherein the array substrate and the opposite substrate are oppositely arranged, and the liquid crystal layer is positioned between the array substrate and the opposite substrate. In specific implementation, the array substrate includes: a thin film transistor, a pixel electrode; the source-drain electrode layers include, for example, a source electrode and a drain electrode of a thin film transistor, the gate electrode layer includes, for example, a gate electrode of a thin film transistor, and the transparent electrode layer includes, for example, a pixel electrode. The material of the transparent electrode layer may include Indium Tin Oxide (ITO), for example. In a specific implementation, the thin film transistor may be, for example, a bottom gate structure, the first insulating layer includes a gate insulating layer, and the second insulating layer includes a passivation layer. Of course, the thin film transistor may have a top gate structure, the first insulating layer may include an interlayer insulating layer, and the second insulating layer may include a passivation layer.
The display device provided by the embodiment of the application is as follows: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the present application.
To sum up, the display device that this application embodiment provided, a plurality of driver chip cascade sets up to need not to provide the signal to each driver chip through setting up printed circuit board, can simplify display device's assembly process, can also save the cost. And set up the voltage compensation circuit in driver chip, when showing that the signal voltage drop appears in the transmission course, the voltage compensation circuit can compensate the voltage that shows the signal for the difference of the display signal voltage after the same kind compensation of arbitrary adjacent driver chip output is less than the default, avoids the same kind of display signal voltage difference of adjacent driver chip output great, avoids appearing the block luminance inequality, improves the display effect, promotes user experience.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A display device, characterized in that the display device comprises: the display device comprises a display panel, a plurality of cascaded driving chips and a plurality of driving units, wherein the plurality of cascaded driving chips are bound on one side of the display panel;
each of the driving chips includes: the display device comprises a plurality of display signal input ends, display signal output ends which correspond to the display signal input ends one to one, and at least one voltage compensation circuit;
each voltage compensation circuit is electrically connected with one display signal input end and one display signal output end respectively;
except the driving chip of the last stage, the display signal output end of each driving chip is electrically connected with the display signal input end of the next stage adjacent to the display signal output end of the last stage in a one-to-one correspondence manner;
the voltage compensation circuit is used for: and according to the display signal received by the display signal input end, performing voltage compensation on the display signal to generate a compensated display signal, and outputting the compensated display signal to the display signal output end, so that the difference between the compensated display signals output by any adjacent driving chips in the same type is smaller than a preset value.
2. The display device according to claim 1, wherein the voltage compensation circuit comprises: a comparison unit;
the first input end of the comparison unit is electrically connected with one display signal input end, and the second input end of the comparison unit is electrically connected with a reference signal input end;
the comparison unit is used for: and determining the difference value of the display signal and the reference signal according to the display signal received by the display signal input end and the reference signal received by the reference signal input end, and generating and outputting a voltage compensation signal of the display signal according to the difference value of the display signal and the reference signal.
3. The display device according to claim 2, wherein the comparison unit includes: a comparator, and an operational amplifier;
the first input end of the comparator is electrically connected with one display signal input end, the second input end of the comparator is electrically connected with the reference signal input end, the output end of the comparator is electrically connected with the input end of the operational amplifier, and the output end of the operational amplifier outputs the voltage compensation value of the display signal.
4. The display device according to claim 3, wherein the voltage compensation circuit further comprises: a low dropout linear regulator;
the input end of the low dropout linear regulator is electrically connected with the display signal input end, and the output end of the low dropout linear regulator is electrically connected with the first input end of the comparator.
5. The display device according to claim 2, wherein the voltage compensation circuit further comprises: an adder;
the first input end of the adder is electrically connected with the output end of the comparison unit, the second input end of the adder is electrically connected with the display signal input end, and the output end of the adder is electrically connected with the display signal output end.
6. The display device according to claim 2, wherein the voltage compensation signal for each of the display signals generated by different ones of the driving chips has the same value.
7. The display device according to claim 6, wherein the difference between the display signal inputted from the voltage compensation circuit and the signal inputted from the reference signal terminal is equal between the different driving chips.
8. The display device of claim 1, wherein the plurality of display signal inputs comprises: a first power signal input, a first voltage signal input, and a second voltage signal input;
at least one of the voltage compensation circuits comprises: the voltage compensation circuit comprises a first voltage compensation circuit electrically connected with the first power signal input end, a second voltage compensation circuit electrically connected with the first voltage signal input end, and a third voltage compensation circuit electrically connected with the second voltage signal input end.
9. The display device according to claim 1, further comprising: a chip on film circuit board; the driving chip is bound with the display panel through the chip on film circuit board;
the display panel includes: the display device comprises a display area and a peripheral area positioned outside the display area;
the peripheral zone includes: a plurality of first bonding terminals and a plurality of second bonding terminals bonded to each of the COF boards, and a plurality of connection leads;
the first binding terminals are electrically connected with the display signal input ends in a one-to-one correspondence manner through the chip on film circuit board, and the second binding terminals are electrically connected with the display signal output ends in a one-to-one correspondence manner through the chip on film circuit board;
the first binding terminals and the second binding terminals bound with the adjacent chip on film circuit boards are electrically connected in a one-to-one correspondence mode through the connecting leads;
the connecting lead is located at a different film layer from the first binding terminal and the second binding terminal.
10. The display device according to claim 9, wherein the display area comprises: a source drain electrode layer, a gate electrode layer, and a transparent electrode layer;
the first binding terminal and the second binding terminal are arranged on the same layer as the source and drain electrode layer;
the connection lead includes: the first sub-lead is arranged on the same layer as the grid layer, and the second sub-lead is arranged on the same layer as the transparent electrode layer;
an extending direction of the first sub-lead crosses an extending direction of the first binding terminal and the second binding terminal;
the first sub-lead is electrically connected to the first binding terminal and the second binding terminal through the second sub-lead, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023056358.6U CN214012484U (en) | 2020-12-17 | 2020-12-17 | Display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023056358.6U CN214012484U (en) | 2020-12-17 | 2020-12-17 | Display device |
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| CN214012484U true CN214012484U (en) | 2021-08-20 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113870770A (en) * | 2021-09-26 | 2021-12-31 | 合肥京东方瑞晟科技有限公司 | Drive chip, display panel and display device |
| CN114373416A (en) * | 2021-11-30 | 2022-04-19 | 长沙惠科光电有限公司 | Display panel |
-
2020
- 2020-12-17 CN CN202023056358.6U patent/CN214012484U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113870770A (en) * | 2021-09-26 | 2021-12-31 | 合肥京东方瑞晟科技有限公司 | Drive chip, display panel and display device |
| CN114373416A (en) * | 2021-11-30 | 2022-04-19 | 长沙惠科光电有限公司 | Display panel |
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